JPH11196578A - Multiplex inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a multiplex inverter device which, even if a short circuit failure, etc., occurs in at least one unit inverter among a plurality of unit inverters, can keep on operating an AC load while the operations of the remaining nondefective inverter units are not discontinued. SOLUTION: A multiplex inverter device converts the DC power of a rectifier 2 into an AC power and has a plurality of voltage-type unit inverters 9 whose input sides are connected in parallel to the rectifier 2 respectively with smoothing capacitors 3 therebetween and whose output sides are connected in series to each other and, further, connected to an AC load 10. In the multiplex inverter device, a bypass switch control means 15 which, if both an operation abnormality detecting means 13 and a DC abnormality detecting means 14 detect an abnormality, gives a closing command to a bypass switch 11 corresponding to the unit inverter 9 in question to fuse down a fuse 4 corresponding to the unit inverter 9 in question is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex inverter device for supplying a high voltage output obtained by connecting the output sides of a plurality of unit inverters in series to an AC load.

[0002]

2. Description of the Related Art Conventionally, there is a need for energy saving by variable speed operation of an AC motor, for example, an induction motor. In particular, an existing high-voltage motor is replaced with, for example, a 3KV system.
There is a need for a drive device that can be directly applied to 6KV systems and 4.2KV systems and 2.4KV systems overseas.

Conventionally, as a multiplex type inverter device used for such an application, USP. No. 5,625,545 are known in which the outputs of a plurality of unit inverters are connected in series.

FIG. 13 shows an example of a specific circuit using such a conventional multiplex type inverter device.
Hereinafter, FIG. 13 will be described. That is, the rectifier 2 converts the AC voltage of the AC power supply 1 into a DC voltage, and converts the DC power of the rectifier 2 into AC power.
Are connected in parallel via a smoothing capacitor 3, for example, 4
Gate control means for giving a firing command in a predetermined order to a unit inverter 9 in which semiconductor elements 5, 6, 7, 8 such as IGBTs are bridge-connected, and semiconductor elements 5 to 8 constituting unit inverter 9 40 is provided.

Although not shown in FIG. 13, a plurality of unit inverters 9 including the same smoothing capacitor 3 as the above-described configuration are prepared, and the input side of each unit inverter 9 is connected to the rectifier 2 in parallel. The output side of each unit inverter 9 is connected in series, and an AC load 10 such as an induction motor is connected to the output side of the multiplexed inverter connected in this way.

The unit inverter 9 is provided with a bypass circuit described below to protect the unit inverter 9. The bypass circuit is connected between the input-side buses of the AC load 10 and includes, for example, a bypass switch 41 composed of a thyristor, a bypass switch 41 and the AC load 1.
Diodes 42, 43, 44, 45 connected between zero
, A current detection circuit 46 for detecting a load current, and a switch operation circuit 47 for giving an ON command to the bypass switch 41 when the current value detected by the current detection circuit 46 exceeds a predetermined value. Have been.

The above-described bypass circuit is similarly configured in other unit inverters (not shown) other than the unit inverter 9 shown.

[0008]

In FIG. 13, when the unit inverter 9 is in a normal state in which no short-circuit accident or the like occurs, the bypass circuit 41 does not operate at all because the bypass switch 41 remains off.

However, among the unit inverters 9, for example, when the semiconductor elements 5 and 8 of one unit inverter 9 are not completely short-circuited but short-circuited with the semiconductor elements such as IGBT bonding wires remaining, Since the current value detected by the current detection circuit 46 exceeds a predetermined value, the switch operation circuit 47 operates and the bypass switch 41 is turned on. As a result, the short-circuit current flowing through the load 10 flows in the direction of the arrow of the bypass circuit.

The above operation is an ideal circuit in which there is no operation delay until the current detection circuit 46 detects the abnormality of the unit inverter 9 and turns on the bypass switch 41, and an operation delay actually occurs. Therefore, the unit inverter 9
The short-circuit fault causes a short-circuit current to flow through the AC load 10. Therefore, if the operation of the unit inverter 9 having the short-circuit fault is not stopped once, the AC load 10 may be burned.

The present invention has been made in view of such circumstances, and even if a short-circuit failure or the like occurs in at least one of a plurality of unit inverters, the operation of the remaining sound unit inverters is stopped. It is an object of the present invention to provide a multiplex type inverter device that can continue the operation of an AC load without any operation.

[0012]

In order to achieve the above object, an invention corresponding to claim 1 includes a rectifier for converting AC power to DC power and a DC power for converting the DC power of the rectifier to AC power. A plurality of voltage-type unit inverters each comprising a plurality of semiconductor elements bridge-connected, and the input side of each unit inverter is connected in parallel to the rectifier via a smoothing capacitor, and the output side of each unit inverter. Series, and an inverter group connected to an AC load, a fuse connected in series between the rectifier and the unit inverter, between the rectifier and the unit inverter, and connected in parallel to the unit inverter. A bypass switch that forms a flow path for circulating a load current when electrically closed, and a semiconductor element that constitutes the unit inverter. A unit inverter control unit for giving a firing command in a predetermined order, an operation abnormality detection unit for detecting an abnormal operation state of the unit inverter based on an AC output of the unit inverter, and detecting an abnormality of the DC input of the unit inverter. When both the DC abnormality detecting means and the operation abnormality detecting means and the DC abnormality detecting means detect an abnormality, the closing instruction is given to the bypass switch corresponding to the corresponding unit inverter by giving the closing instruction. A multiplex inverter device including bypass switch control means for blowing the fuse corresponding to a unit inverter.

In order to achieve the above object, the invention according to claim 2 is the multiplex inverter device according to claim 1, wherein the DC abnormality detecting means detects a DC abnormality accompanying the blowing of the fuse. It is.

According to a third aspect of the present invention, the DC abnormality detecting means determines that the DC voltage applied to the unit inverter is an overvoltage or an undervoltage with respect to a reference value. 2. The multiplex type inverter device according to claim 1, wherein the multiplex type inverter device detects.

In order to achieve the above object, the invention according to claim 4 is characterized in that the operation abnormality detecting means detects an output AC voltage of the unit inverter and the detected voltage falls within a predetermined range with respect to a reference value. 2. The multiplex inverter device according to claim 1, wherein an abnormality of the unit inverter is detected when the number exceeds the threshold.

To achieve the above object, an invention according to claim 5 includes a rectifier for converting AC power to DC power,
The DC power of the rectifier is converted into AC power, a plurality of voltage-type unit inverters are provided by bridging a plurality of semiconductor elements, and the input side of each of the unit inverters is respectively connected via a smoothing capacitor. An inverter group connected in parallel to a rectifier, the output side of each unit inverter is connected in series, and connected to an AC load; a fuse connected in series between the rectifier and the unit inverter; the rectifier and the unit inverter A bypass switch that is connected in parallel with the unit inverter and forms a flow path that circulates a load current when electrically closed, and a predetermined switch for a semiconductor element constituting the unit inverter. Pulse width modulation unit inverter control means for giving a firing command in order, and a failure related to the unit inverter control means A multiplex inverter device comprising an abnormality determining means for determining, and a bypass switch control means for blowing the fuse by giving a closing command to a bypass switch of a corresponding unit inverter when the abnormality determining means determines an abnormality. is there.

In order to achieve the above object, the invention according to claim 6 is characterized in that the abnormality determining means is configured to determine a relation between an output voltage of the unit inverter and an output voltage of the unit inverter control means, and an output of the unit inverter control means. Voltage waveform,
6. The multiplex inverter device according to claim 5, wherein the determination is made based on any one of a power supply abnormality of the unit inverter control means.

In order to achieve the above object, the invention according to claim 7 comprises a rectifier for converting AC power to DC power,
The DC power of the rectifier is converted into AC power, a plurality of voltage-type unit inverters are provided by bridging a plurality of semiconductor elements, and the input side of each of the unit inverters is respectively connected via a smoothing capacitor. An inverter group connected in parallel to a rectifier, the output side of each unit inverter is connected in series, and connected to an AC load; a fuse connected in series between the rectifier and the unit inverter; the rectifier and the unit inverter A bypass switch that is connected in parallel with the unit inverter and forms a flow path that circulates a load current when electrically closed, and a predetermined switch for a semiconductor element constituting the unit inverter. A pulse width modulation type unit inverter control means for giving a firing command in order; and Operation abnormality detection means for detecting an abnormal operation state of the inverter, DC abnormality detection means for detecting an abnormality of the DC input of the unit inverter, and when the operation abnormality detection means and the DC abnormality detection means have both detected abnormality, A bypass switch control means for blowing the fuse by giving a closing command to the bypass switch corresponding to the corresponding unit inverter, wherein the unit inverter of the inverter group in which an abnormality has occurred in the inverter group by the unit inverter control means Is a multiplex type inverter device operated at a modulation factor of 1 or more.

To achieve the above object, an invention according to claim 8 comprises a rectifier for converting AC power to DC power,
The DC power of the rectifier is converted into AC power, a plurality of voltage-type unit inverters are provided by bridging a plurality of semiconductor elements, and the input side of each of the unit inverters is respectively connected via a smoothing capacitor. An inverter group connected in parallel to a rectifier, the output side of each unit inverter is connected in series, and connected to an AC load; a fuse connected in series between the rectifier and the unit inverter; the rectifier and the unit inverter A bypass switch that is connected in parallel with the unit inverter and forms a flow path that circulates a load current when electrically closed, and a predetermined switch for a semiconductor element constituting the unit inverter. A pulse width modulation type unit inverter control means for giving a firing command in order; and Operation abnormality detection means for detecting an abnormal operation state of the inverter, DC abnormality detection means for detecting an abnormality of the DC input of the unit inverter, and when the operation abnormality detection means and the DC abnormality detection means have both detected abnormality, By providing a bypass command to the bypass switch corresponding to the corresponding unit inverter, a bypass switch control means for blowing the fuse is provided. This is a multiplex inverter device that operates the number of operations of the inverter group of the phase.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 shows a main circuit of a multiplex type inverter (inverter group) to which the present invention is applied. , 24U1, 24U2, 24U3, 24V1, 24
V2, 24V3, 24W1, 24W2, and 24W3 are connected in combination of three each. Specifically, the unit inverters 24U1, 24U2, 24U3, 24V1,
The fuses 4U1, 4U2, 4U3, 4 are connected to the input sides of 24V2, 24V3, 24W1, 24W2, 24W3, respectively.
V1, 4V2, 4V3, 4W1, 4W2, 4W3 were connected in series and connected in parallel to the rectifier 2, and the output side of the unit inverter was connected in series for each phase and connected to an AC load 10, for example, an induction motor. Things.

FIG. 2 is a block diagram for explaining the first embodiment of the present invention, which is one unit inverter 9 of the inverter group (multiplex inverter) of FIG.
And the semiconductor elements 5, 6, 7, 8 of the unit inverter 9
Only a unit inverter control means 12 for controlling the ignition of the motor and a bypass circuit including a bypass switch 11, an operation abnormality detection means 13, a DC abnormality detection means 14, and a bypass switch control means 15, which will be described later, are shown. There are a plurality of unit inverters 9, and each unit inverter 9 is provided with the bypass circuit.

FIG. 3 is a diagram for explaining an example of the unit inverter control means 12. The unit inverter control means 12 detects the rotational speed of the AC motor 68 and performs speed feedback so that the slip frequency becomes a slip frequency according to the torque command. , The inverter frequency is controlled, and a current control loop is additionally provided. Specifically, the rotation speed of the AC motor 68 is detected by the rotation detector 69 and the speed detector 70, and the detected speed value is compared with the set value of the speed setting device 60 by the comparator 61. Amplified by the control amplifier 62, the amplified value is converted to a predetermined frequency by the slip frequency pattern generator 71, and the converted frequency is compared with the detected speed value detected by the speed detector 70 by the comparator 72.
The obtained inverter frequency f command is supplied to the PWM control circuit 67.

The output of the speed control amplifier 62 is input to a current pattern generator 63, where it is converted into a current. The converted current is compared with a detected current detected by a current detector 64 by a comparator 65. The deviation is input to the current control amplifier 66, and the obtained motor primary terminal voltage V1 command is supplied to the PWM control circuit 67. PW
The M control circuit 67 gives a gate command corresponding to the ratio between the inverter frequency f command and the motor primary terminal voltage V1 command to the gate of each unit inverter.

In the multiplex type inverter device configured as described above, when all of the plurality of unit inverters 9 are in a normally operable state, the unit inverter control means 12 controls the semiconductor elements 5 to 8 of the unit inverter 9. Is controlled to fire, thereby supplying a high-voltage AC power to the AC load 10.

In this case, since each unit inverter 9 is normal, no abnormality detection signal is output from the operation abnormality detection means 13 and no abnormality detection signal is output from the DC abnormality detection means 14 on the rectifier 2 side. No closing command is given from the switch control means 15 to the bypass switch 11. For this reason, the bypass switch 11 remains off.

In a state where each unit inverter 9 is operating normally, for example, the semiconductor elements 5 and 8 of one unit inverter 9 are short-circuited (however, the bonding wires in the IGBT constituting the unit inverter are not connected). Then, the following operation is performed. In this case, since the AC output current of the unit inverter 9 increases or the AC output voltage decreases, the operation abnormality detection means 13 outputs an abnormality detection signal, which is given to the bypass switch control means 15.

On the other hand, since the DC input current of the inverter bridge 9 increases, an abnormality detection signal is output from the DC abnormality detection means 14, and is supplied to the bypass switch control means 15. As a result, a closing command, that is, a gate-on signal is given to the bypass switch 11 from the bypass switch control means 15, and the bypass switch 11 is turned on. Since the short-circuit current that has flowed flows through the path of the bypass switch 11, the fuse 4, and the smoothing capacitor 3, the fuse 4 is blown. When the fuse 4 is blown, the mode automatically switches to the output bypass mode. As a result, in the healthy unit inverter 9 in which a short-circuit failure or the like does not occur, each semiconductor element is controlled to be fired in a predetermined order by the unit inverter control means 12, power is supplied to the AC load 10, and the AC load 10 is maintained. You can drive.

Therefore, it is not necessary to temporarily stop the operation of the multiplex inverter to protect the AC load from an excessive current due to a short circuit accident of the conventional unit inverter. Can continue.

<Second Embodiment> FIG. 4 is a block diagram showing a part of a second embodiment of the present invention. As shown in FIG. 9, a unit inverter control means 12 for controlling the ignition of the semiconductor elements 5, 6, 7, and 8;
1, only a bypass circuit composed of an operation abnormality detection means 13, a DC abnormality detection means 14, and a bypass switch control means 15 is shown, but the actual configuration has a plurality of unit inverters 9 and each unit inverter 9 has a corresponding one. A bypass circuit is provided.

FIG. 4 shows an operating contact 4a which is closed on the input side of the DC abnormality detecting means 14 in FIG.
2 is different from FIG.

<Third Embodiment> FIG. 5 is a block diagram showing a part of a third embodiment of the present invention. As shown in FIG. 9, a unit inverter control means 12 for controlling the ignition of the semiconductor elements 5, 6, 7, and 8;
1, only the bypass circuit comprising the operation abnormality detection means 13, the level determination means 17, and the bypass switch control means 15 is shown. However, the actual configuration has a plurality of unit inverters 9, and each unit inverter 9 has its own bypass circuit. A circuit is provided.

The DC voltage applied to the unit inverter 9 is detected by the voltage detecting means 16 and the level determining means 17
Is to detect that the value detected by the voltage detecting means 16 has become overvoltage or undervoltage with respect to the reference value. The point that the bypass switch control means 15 operates when an output is generated from the level determination means 17 and a detection signal is generated from the operation abnormality detection means 13 is the same as in FIG.

<Fourth Embodiment> FIG. 6 is a block diagram showing a part of a fourth embodiment of the present invention. As shown in FIG. 9, a unit inverter control means 12 for controlling the ignition of the semiconductor elements 5, 6, 7, and 8;
1, only a bypass circuit comprising DC abnormality detecting means 14, level judging means 18 and bypass switch control means 15 is shown, but the actual configuration is that there are a plurality of unit inverters 9 and each unit inverter 9 has a corresponding bypass circuit. A circuit is provided.

The level judging means 18 includes the unit inverter 9
Is detected by the voltage detecting means 25, and when the detected voltage exceeds a predetermined range with respect to the reference value, an abnormality of the unit inverter is detected. The point at which the bypass command is output from the bypass switch control means 15 to the bypass switch 11 when the determination signal is obtained from the level determination means 18 and the detection signal is generated from the DC abnormality detection means 14 is shown in FIG. Same as 2.

<Fifth Embodiment> FIG. 7 is a block diagram showing a part of a fifth embodiment of the present invention. As shown in FIG. 9, a unit inverter control means 12 for controlling the ignition of the semiconductor elements 5, 6, 7, and 8;
1, only a bypass circuit comprising output detection means 35, 36, 37, 38, an inverter output detector 19, and an abnormality determination means 20 is shown.
, And each unit inverter 9 is provided with the bypass circuit.

The abnormality judging means 20 inputs the output voltage detected by the inverter output detector 19 and the voltage detected by any one of the output detectors 35 to 38 of the unit inverter control means 12, and outputs The difference from FIG. 2 is that an abnormality of the unit inverter control means 12, that is, a failure due to an external factor is detected.

<Sixth Embodiment> FIG. 8 is a block diagram showing a part of a sixth embodiment of the present invention. As shown in FIG. 9, a unit inverter control means 12 for controlling the ignition of the semiconductor elements 5, 6, 7, and 8;
1, only a bypass circuit composed of the output detectors 35, 36, 37, 38 and the abnormality determining means 21 is shown, but the actual configuration is that there are a plurality of unit inverters 9 and each unit inverter 9 has its own bypass circuit. Is provided.

The voltage waveforms detected by the output detectors 35 to 38 of the unit inverter control means 12 are input to the abnormality determination means 21, and the voltage waveform is compared with the reference voltage waveform to determine an abnormality due to an external factor. It is different from FIG.

<Seventh Embodiment> FIG. 9 is a block diagram showing a part of a seventh embodiment of the present invention. As shown in FIG. 9, a unit inverter control means 12 for controlling the ignition of the semiconductor elements 5, 6, 7, and 8;
1, only a bypass circuit including the abnormality determination unit 21 and the power supply abnormality detection unit 22 is shown. However, the actual configuration includes a plurality of unit inverters 9 and each unit inverter 9 is provided with the bypass circuit. .

The power supply abnormality detecting means 22 detects a power supply abnormality of the unit inverter control means 12, inputs the detection output to the abnormality determination means 21 and compares it with a reference voltage to determine an abnormality due to an external factor. This is different from FIG.

<Eighth Embodiment> FIG. 1 shows a multiplexed inverter having a three-phase unit and unit inverters of each phase V, V, W, each having 24U1, 24U2, 24U3, 24V.
1,24V2,24V3,24W1,24W2,24W
3 and 3 in combination, and each unit inverter has a fuse 4U in the same manner as in the above-described embodiments.
1,4U2,4U3,4V1,4V2,4V3,4W
Needless to say, connect 1,4W2,4W3,
In addition, it goes without saying that a bypass circuit having a configuration similar to that of each of the above-described embodiments is provided in each unit inverter.

<Ninth Embodiment> FIGS. 10 and 11 are views for explaining a ninth embodiment of the present invention.
0 indicates a part of the PWM control circuit 67 of FIG. 3 in which the main circuit is a three-phase circuit as shown in FIG.
Converters are shown, and reference numerals 30, 31, and 32 denote proportional calculators.

With such a configuration, in a multiplex inverter, for example, when one of the unit inverters continues to operate with the remaining healthy unit inverter due to a fault such as a short circuit, the unit inverter of the phase in which the abnormality has occurred Is configured to be 1 or more.

FIG. 11 shows the voltage waveform of the output of each phase of the multiplex type inverter in this case. In this way, it is possible to compensate for the decrease in the output voltage of each phase inverter group due to the decrease in the number of unit inverters. .

<Tenth Embodiment> In the multiplex type inverter device constructed in the same manner as the ninth embodiment in the main circuit of FIG. 1, for example, the unit of the phase detected by each of the operation abnormality detecting means 13 described above. In accordance with the number of inverters, the number of operating unit inverters in the healthy phase is operated.

<Modification> In the above embodiment, the case where a semiconductor switch such as a thyristor is used as the bypass switch 11 has been described, but a mechanical switch may be used instead of the semiconductor switch. A mechanical switch has a smaller heat loss than a semiconductor switch, but has a slower operation than a semiconductor switch. Therefore, it is impossible to protect and continue operation while driving.

In the above-described embodiment, a case has been described where all the unit inverter groups for each phase are operated when the inverter bridge is normal. However, when the inverter bridge is normal, a plurality of unit inverters for each phase are operated. At least one of them may be used as a spare. In this case, the operation of the unit inverter group for each phase and the standby which is not operated may be automatically switched, or may be manually performed by an operator using, for example, a copper bar.

Further, in the above embodiment, the semiconductor element constituting the unit inverter has been described using an IGBT as an example, but a thyristor is connected in anti-parallel as shown in FIG. ), The GTOs may be connected in anti-parallel. Further, as the rectifier 2 of the above-described embodiment, as shown in FIG. 12C, a series circuit of a semiconductor element S1 with a control electrode for short-circuit and a saturable reactor L1 may be connected to the output side of the diode bridge. Further, as shown in FIG. 12D, the diodes D1 and D1 serve as bypass switches for bypassing the output of the unit inverter 9.
A bridge connection may be made using D2 and the semiconductor elements S1 and S2 with control poles to short-circuit the DC output.

[0050]

According to the present invention described above, even if a short circuit fault or the like occurs in at least one of the plurality of unit inverters, the operation of the remaining healthy unit inverters is not stopped, and the AC load is maintained. Can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main circuit of a multiplex type inverter to which the present invention is applied.

FIG. 2 is a circuit diagram showing only essential parts for describing a first embodiment of the multiplex type inverter device of the present invention.

FIG. 3 is a diagram for explaining an example of a unit inverter control unit of FIG. 2;

FIG. 4 is a circuit diagram showing only essential parts for describing a second embodiment of the multiplex inverter device of the present invention.

FIG. 5 is a circuit diagram showing only a main part for explaining a third embodiment of the multiplex type inverter device of the present invention.

FIG. 6 is a circuit diagram showing only essential parts for explaining a fourth embodiment of the multiplex inverter device of the present invention.

FIG. 7 is a circuit diagram showing only essential parts for describing a multiplex inverter device according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing only a main part for describing a sixth embodiment of the multiplex inverter device of the present invention.

FIG. 9 is a circuit diagram showing only main parts for describing a multiplex inverter device according to a seventh embodiment of the present invention.

FIG. 10 is a circuit diagram showing only essential parts for explaining a ninth embodiment of a multiplex inverter device of the present invention.

FIG. 11 is a circuit diagram showing only a main part for describing a ninth embodiment of the multiplex inverter device of the present invention.

FIG. 12 is a view for explaining a modification of the embodiment of the multiplex inverter device of the present invention.

FIG. 13 is a circuit diagram showing only main parts for explaining a conventional multiplex type inverter device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... AC power supply 2 ... Rectifier 3 ... Smoothing capacitor 4 ... Fuse 5-8 ... Semiconductor element such as IGBT 10 ... AC load 11 ... Bypass switch such as thyristor 12 ... Unit inverter control means 13 ... Operation abnormality detection means 14 ... DC abnormality detection means 15: bypass switch control means 16: DC voltage detection means 17, 18 ... level determination means 19 ... AC voltage detection means 20, 21 ... abnormality determination means 22 ... power supply abnormality detection means

Claims (8)

[Claims] 1. A rectifier for converting AC power into DC power, and a plurality of voltage-type unit inverters for converting the DC power of the rectifier into AC power, wherein a plurality of semiconductor elements are bridge-connected. An inverter group in which the input side of each unit inverter is connected in parallel to the rectifier via a smoothing capacitor, and the output side of each unit inverter is connected in series and connected to an AC load; and the rectifier and the unit A fuse connected in series between the inverters, a bypass switch between the rectifier and the unit inverter, connected in parallel with the unit inverter, and forming a flow path for circulating a load current when electrically closed. A unit inverter control means for giving a firing command in a predetermined order to the semiconductor elements constituting the unit inverter; Operating abnormality detecting means for detecting an abnormal operating state of the unit inverter based on an AC output of the inverter, DC abnormal detecting means for detecting an abnormal DC input of the unit inverter, operating abnormal detecting means and DC abnormal detecting means When both detect an abnormality, by providing a closing command to the bypass switch corresponding to the corresponding unit inverter, bypass switch control means for blowing the fuse corresponding to the unit inverter given the closing command, Multiplexed inverter device equipped. 2. The apparatus according to claim 1, wherein the DC abnormality detecting means detects a DC abnormality in accordance with a blow of the fuse.
A multiplex inverter device as described in the above. 3. The multiplex inverter device according to claim 1, wherein said DC abnormality detecting means detects that a DC voltage applied to said unit inverter has become an overvoltage or an undervoltage with respect to a reference value. . 4. The operation abnormality detecting means detects an output AC voltage of the unit inverter and detects an abnormality of the unit inverter when the detected voltage exceeds a predetermined range with respect to a reference value. Item 2. The multiplex inverter device according to Item 1. 5. A rectifier for converting AC power to DC power, and a plurality of voltage type unit inverters for converting the DC power of the rectifier to AC power, wherein a plurality of semiconductor elements are bridge-connected. An inverter group in which the input side of each unit inverter is connected in parallel to the rectifier via a smoothing capacitor, and the output side of each unit inverter is connected in series and connected to an AC load; and the rectifier and the unit A fuse connected in series between the inverters, a bypass switch between the rectifier and the unit inverter, connected in parallel with the unit inverter, and forming a flow path for circulating a load current when electrically closed. A pulse width modulation unit inverter for giving a firing command in a predetermined order to semiconductor elements constituting the unit inverter. Control means, abnormality determination means for determining a failure related to the unit inverter control means, and when the abnormality determination means determines an abnormality, by giving a closing command to a bypass switch of the corresponding unit inverter, to fuse the fuse A multiplex inverter device comprising: a bypass switch control means for fusing; 6. The abnormality judging means includes any one of a relation between an output voltage of the unit inverter and an output voltage of the unit inverter control means, a waveform of an output voltage of the unit inverter control means, and a power supply abnormality of the unit inverter control means. 6. The multiplex inverter device according to claim 5, wherein the determination is made based on the following. 7. A rectifier for converting AC power to DC power, and a plurality of voltage-type unit inverters for converting the DC power of the rectifier to AC power, wherein a plurality of semiconductor elements are bridge-connected. An inverter group in which the input side of each unit inverter is connected in parallel to the rectifier via a smoothing capacitor, and the output side of each unit inverter is connected in series and connected to an AC load; and the rectifier and the unit A fuse connected in series between the inverters, a bypass switch between the rectifier and the unit inverter, connected in parallel with the unit inverter, and forming a flow path for circulating a load current when electrically closed. A pulse width modulation unit inverter for giving a firing command in a predetermined order to semiconductor elements constituting the unit inverter. Control means; operation abnormality detection means for detecting an operation abnormality state of the unit inverter based on an AC output of the unit inverter; DC abnormality detection means for detecting an abnormality of a DC input of the unit inverter; and the operation abnormality detection means And a bypass switch control means for blowing the fuse by giving a closing command to the bypass switch corresponding to the corresponding unit inverter when both the DC abnormality detection means and the DC abnormality detection means detect an abnormality. A multiplex inverter device, wherein the unit is operated by setting the modulation factor of the unit inverter of the phase in which an abnormality has occurred in the inverter group to be 1 or more. 8. A rectifier for converting AC power into DC power, and a plurality of voltage source unit inverters for converting the DC power of the rectifier into AC power, wherein a plurality of semiconductor elements are bridge-connected. An inverter group in which the input side of each unit inverter is connected in parallel to the rectifier via a smoothing capacitor, and the output side of each unit inverter is connected in series and connected to an AC load; and the rectifier and the unit A fuse connected in series between the inverters, a bypass switch between the rectifier and the unit inverter, connected in parallel with the unit inverter, and forming a flow path for circulating a load current when electrically closed. A pulse width modulation unit inverter for giving a firing command in a predetermined order to semiconductor elements constituting the unit inverter. Control means; operation abnormality detection means for detecting an operation abnormality state of the unit inverter based on an AC output of the unit inverter; DC abnormality detection means for detecting an abnormality of a DC input of the unit inverter; and the operation abnormality detection means And a bypass switch control means for blowing the fuse by giving a closing command to the bypass switch corresponding to the corresponding unit inverter when both the DC abnormality detection means and the DC abnormality detection means detect an abnormality. A multiplex inverter device in which the number of operation of the inverter group of the healthy phase is operated according to the number of the inverter group of the phase detected by the means.