JPH1039969A - Computer system and input/output interface device applied to the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an accident such as the malfunction of a peripheral device by normally executing the initializing processing of the peripheral device even when the phenomenon turning around a current from the peripheral device to an input/output interface is generated at the time of turning on a power source. SOLUTION: Before turning on the power source of a main body 1 of computer and just after the power source of a printer 2 is turned on, power source supply (so-called current turn-around phenomenon) from the printer 2 to the side of an input/output interface 10 is generated. At such a time, the input/ output interface 10 keeps the state of an interface signal high. Thus, since the printer 2 can maintain an interface signal PI in the state of logic level 'H', at the time of turning on the power source, initializing processing can be normally executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output interface device for controlling a peripheral device provided in a computer main body, and more particularly, to an input / output interface device having a parallel port for connecting the peripheral device. The present invention relates to a computer system including an input / output interface device that outputs a necessary interface signal via a parallel port.

[0002]

2. Description of the Related Art Conventionally, a personal computer is provided with an input / output interface for connecting peripheral devices such as a printer and outputting various interface signals necessary for the operation of the peripheral devices. As the input / output interface, there is a system having a parallel port for outputting a plurality of interface signals in parallel in addition to the serial communication port.

As an example, an input / output interface having this parallel port is provided on the computer main body 1 as shown in FIG. 5, and is connected via signal lines 3a and 3b (here, two ports) of the parallel port. To a peripheral device (here, a printer is assumed) 2. The input / output interface includes a plurality of I / Os corresponding to each port.
It has / O buffers 4a and 4b and an I / O buffer control circuit 5, and is constituted by a gate array. I / O
The buffer control circuit 5 is usually included in an internal core circuit together with other circuits.

The I / O buffers 4a and 4b output interface signals ST and PI necessary for the operation of the printer 2 in accordance with input control (control signals PD and ND) of the I / O buffer control circuit 5. Here, an interface signal ST which is a strobe signal and an initialization signal PIN of the printer are used as interface signals.
Assume two types of interface signals PI that are T.

[0005] The I / O buffer control circuit 5 sets the logic levels of the control signals PD and ND so as to set the logic levels ("H" or "L") of the interface signals ST and PI according to a preset interface definition. The input control is executed by the combination of. That is, the control signals PD,
If each logic level of ND is “H” and “L”, I / O
The buffers 4a and 4b output, for example, interface signals ST and PI of a logic level "H".

Incidentally, in recent personal computers, various power saving methods have been adopted in order to reduce power consumption. As one of the power saving methods, there is a method of separating the system power supply of the computer main body 1 according to the power supply specification of each circuit. Specifically, in the input / output interface, the I / O buffers 4a and 4b and the I / O buffer control circuit 5 have different power supply specifications. For example, the former is a + 5V power supply, and the latter is a + 3V power supply.

For this reason, I / O buffers 4a, 4b and I
Each power supply circuit of the / O buffer control circuit 5 is separated. Therefore, the I / O buffers 4a and 4b are dedicated I / O buffers.
Power is supplied from the O-buffer power supply 6. However,
By the system power switch of the computer body 1,
I / O buffers 4a, 4b and I / O buffer control circuit 5
, Power is supplied simultaneously from the respective power supplies.

[0008]

The input / output interface of the power saving method as described above has the following problems when a peripheral device such as the printer 2 is started. That is, when the power is turned on in the order of turning on the power of the computer main body 1 after the dedicated power of the printer 2 is turned on, the current I is supplied from the printer 2 to the input / output interface during the power on of the computer main body 1. Phenomenon (current wraparound phenomenon) may occur. This is caused by a configuration in which the signal lines 3a and 3b of the ports are connected to the power supply terminals via the pull-up resistors on the printer 2 side as shown in FIG. Less than,
With reference to the flowchart of FIG. 6, a problem when the current sneak phenomenon occurs will be described.

First, it is assumed that the power of the printer 2 is turned on when the system power of the computer main body 1 is off as described above (step S1). In this state, a current sneak occurs from the printer 2 as described above, and the current I is supplied to the input / output interface (step S2). Therefore, the I / O interface I
/ O buffers 4a and 4b are activated (step S
3). At this time, since the system power supply of the computer main body 1 is off, the I / O buffer control circuit 5 is inactive. Therefore, the input states (control signals PD, ND) of the I / O buffers 4a, 4b are undefined.

Thus, the I / O interface I
The / O buffers 4a and 4b may indicate an output state of, for example, a logical level "L" (step S5). Along with this buffer output state, the signal lines of the parallel port signals ST and PI of the printer 2 may be at an intermediate level (intermediate potential) within the range of the logical level "L". This intermediate level is determined according to the pull-up resistance value of the printer 2 and the circuit state of the I / O buffers 4a and 4b.

Here, peripheral devices such as the printer 2 include:
A general method is to execute an initialization process for performing a normal operation immediately after the power is turned on. In a normal printer 2,
When the signal lines of the parallel port signals ST and PI are at an intermediate level within the range of the logical level "L" when the power is turned on, the initialization processing is often not performed normally (step S).
6). For this reason, when the system power supply of the computer main unit 1 is turned on, the I / O buffer control circuit 5 enters an operating state. For example, even if the output states of the I / O buffers 4a and 4b are set to the logic level "H", the initial state is maintained. Printer 2 does not operate normally because the
A malfunction occurs (step S7). In a normal printer 2, for normal initialization, it is desirable that the signal lines of the parallel port signals ST and PI have high impedance (HI-Z) when the power is turned on.

An object of the present invention is to perform initialization processing of a peripheral device normally and cause the peripheral device to malfunction even if a current sneak phenomenon from the peripheral device to the input / output interface occurs when the power is turned on. The purpose is to prevent such a situation.

[0013]

According to the present invention, power is supplied from the peripheral device to the input / output interface side (so-called current sneak phenomenon) before the power supply of the computer main body is turned on and immediately after the power supply of the peripheral device is turned on. Even in such a case, the present invention is a computer system having a function of setting the state of an interface signal to a peripheral device so as to be suitable for performing the initialization operation of the peripheral device.

More specifically, in the interface signal output means and the control means which constitute the input / output interface, the interface signal output means which is in operation due to current sneakage is used to control the non-operation state before turning on the power of the computer main body. The input control state of the means maintains, for example, the logic level state of the interface signal in a high impedance state so as to be compatible with performing the initialization operation of the peripheral device.

With the input / output interface having such a configuration, when the power of the peripheral device is turned on before the power of the computer body is turned on, the initialization processing immediately after the power of the peripheral device can be normally performed. Become. Therefore, when the input / output interface is in a normal operation state after the power supply of the computer main body is turned on, the normal initialization processing has been completed, and the peripheral device does not malfunction.
The operation is reliably executed according to the interface signal from the input / output interface.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a system configuration related to the present embodiment, FIGS. 2 and 3 are diagrams for explaining the operation of the input / output interface of the present embodiment, and FIG. FIG. 3 is a block diagram illustrating a specific circuit of an output interface. (System Configuration) The computer system of the present embodiment assumes a personal computer as the computer body 1 and a printer 2 as a peripheral device. As shown in FIG. 1, the computer main body 1 has an input / output interface 10 having a parallel port (here, two signal lines 3a and 3b) constituted by a gate array. I / O interface 10
Are a plurality of I / O buffers 14a, 14a,
14b and an I / O buffer control circuit 15. I
The / O buffer control circuit 15 is usually included in an internal core circuit together with other circuits.

The I / O buffers 14a and 14b have a circuit configuration as described later (see FIG. 4). The I / O buffers 14a and 14b control the printer 2 in accordance with input control (control signals PD and ND) of the I / O buffer control circuit 15. It outputs interface signals ST and PI necessary for the operation. Here, an interface signal ST which is a strobe signal and an initialization signal PIN of the printer are used as interface signals.
Assume two types of interface signals PI that are T.

The I / O buffer control circuit 15 sets the logic level ("H" or "L") of the interface signals ST and PI according to a preset interface definition.
Is set in accordance with the combination of the logic levels of the control signals PD and ND (see FIGS. 2 and 3).

Further, the computer main body 1 is provided with a power saving device 11 of a power saving type of a power supply separated type. In the present embodiment, the power supply device 11 includes the I / O buffers 14a,
An I / O buffer power supply 6 for supplying power to 14b and an internal core power supply 12 for supplying power to an internal core circuit including the I / O buffer control circuit 5 are provided. The power supply specifications for the I / O buffer power supply 6 and the internal core power supply 12 are different from each other. The former is, for example, a +5 V power supply, and the latter is, for example, a +3 V power supply. Power supply 11
Are configured such that the power supplies 6 and 12 are simultaneously turned on by a power switch of the computer main body 1 (not shown).

The printer 2 has an input / output interface 1
It operates according to the interface signals ST and PI output from the 0 parallel port (signal lines 3a and 3b).
In particular, when the interface signal PI is in the high impedance (HI-Z) state, the printer 2 normally performs a predetermined initialization process immediately after turning on the power. Here, the parallel port (signal lines 3a and 3b) is connected to a pull-up resistor 13
a and 13b are connected to a power supply terminal. (Specific Configuration of I / O Buffers 14a and 14b) I / O
The buffers 14a, 14b are roughly divided into inverters 40 to 41 and MOS transistors 43, 44, as shown in FIG. Since the I / O buffer 14b has the same configuration as the I / O buffer 14a, it is omitted in FIG.

The inverters 40 to 41 are activated by power supply, and output signals having inverted logic levels of the input control signals PD and ND. MOS transistors 43 and 4
4 is a P-channel transistor and an N-channel transistor, respectively. The P-channel transistor 43 is turned off between the source S and the drain D when the logic level of the signal input to the gate G is “H”, and turned on when the logic level is “L”. On the other hand, the N-channel transistor 44
Is turned on between the source S and the drain D at the logic level "H" of the signal input to the gate G, and turned off at the logic level "L".

The P-channel transistor 43 has
It is assumed that a parasitic diode 45 exists between the source S and the drain D. The diode 45 enables a current to flow between the source S and the drain D even when the logic level of the signal input to the gate G is “H” and the connection between the source S and the drain D is off.

The I / O buffer control circuit 15 includes a P-channel transistor 43 of the I / O buffer 14a (14b).
And input control signals PD and ND for controlling the input signal of each gate G of the N-channel transistor 44.
That is, the output state of the I / O buffer 14a (14b) is controlled by the combination of the logic levels of the input control signals PD and ND. The I / O buffer control circuit 15 of the present embodiment has a configuration in which one-stage inverters 50 and 51 are provided at the output terminal of the control signal ND of the conventional I / O buffer control circuit 5.

In the present embodiment, the output state of the I / O buffer 14a (14b) is set as the interface definition of the input / output interface 10, as shown in FIG. Accordingly, as shown in FIG. 3, the I / O buffers 14a and 14b are in the logic level state (HI-Z) corresponding to the combination (four types) of the logic levels of the control signals PD and ND of the I / O buffer control circuit 15. And the prohibition are included). (Operation and Effect of First Embodiment) First, it is assumed that the power supply device 11 of the computer main body 1 is in the off state and the power supply of the printer 2 is turned on first. Therefore, as shown in FIG. 1, since the power supply device 11 is off, the power supply 6 for the I / O buffer and the power supply 12 for the internal core are both off, and the I / O buffers 14a and 14b and the I / O buffer The control circuits 5 are both inactive.

Here, as shown in FIG. 4, when the power of the printer 2 is turned on, a current sneak phenomenon in which the current I is supplied from the printer 2 via the signal line 3a of the port of the input / output interface 10 is performed. Is assumed to occur. The current I passes through a diode 45 parasitic on the P-channel transistor 43 of the I / O buffer 14a.
It is supplied to each circuit element of the I / O buffers 14a and 14b. Therefore, the I / O buffers 14a and 14b
When the buffer power supply 6 is off, the power is supplied and the operation state is established.

Further, in the non-operating state where the power supply is stopped, the I / O buffer control circuit 5 controls the control signals PD and ND.
Are set to logic level "L". If both of the input control signals PD and ND are at the logical level “L”, the I / O buffer 14a
Since the gate G of the P-channel transistor 43 is at the logic level “H”, the portion between the source S and the drain D is turned off. In addition, since the gate G of the N-channel transistor 44 is at the logical level “L”, the source S and the drain D are turned off. Therefore, the signal line 3a of the port connected to the drain D of the N-channel transistor 44
Are in a high impedance (HI-Z) state.

On the other hand, since the I / O buffer 14b has the same configuration as the I / O buffer 14a, the signal line 3b of the port of the input / output interface 10 is also in a high impedance (HI-Z) state. That is, as shown in FIGS. 2 and 3, the output states of the I / O buffers 14a and 14b are determined when the input control signals PD and ND are both at the logical level "L".
It becomes a high impedance (HI-Z) state.

When the port (signal line 3b) of the input / output interface 10 is in a high impedance (HI-Z) state when the power is turned on, the printer 2 pulls up the pull-up resistor 13b.
As a result, the interface signal PI of the initialization process
At the logic level "H". As a result, the printer 2 normally executes the predetermined initialization processing immediately after the power is turned on.

Next, the power supply device 11 of the computer body 1
Is turned on in accordance with the switch, the I / O buffer control circuit 5 is activated along with the I / O buffers 14a and 14b. At this time, the I / O buffer control circuit 5 sets the state of each of the control signals PD and ND to the logic level “L”.
, The output states of the I / O buffers 14a and 14b maintain a high impedance (HI-Z) state. Therefore, the printer 2 uses the pull-up resistor 13
Due to a and 13b, both of the interface signals ST and PI are maintained at the logic level "H". Thereafter, the I / O buffer control circuit 5 changes the output levels of the I / O buffers 14a and 14b by changing the logic levels of the control signals PD and ND, as shown in FIG. To work properly.

As described above, according to the present embodiment, when the peripheral device such as the printer 2 is started, the power is turned on in the order of turning on the dedicated power of the printer 2 and then turning on the power of the computer 1. Even if the phenomenon that the current I is supplied from the printer 2 to the input / output interface (current sneak phenomenon) occurs, the I / O
The output state of the O buffers 4a and 4b can be set to a high impedance (HI-Z) state. Further, the output state of the I / O buffers 4a and 4b of the input / output interface can be maintained in a high impedance (HI-Z) state immediately after the power of the computer main body 1 is turned on.

Therefore, on the printer 2 side, the interface signal PI required for the initialization processing at the time of power-on can be maintained at the logical level "H", so that the initialization processing can be performed reliably. In other words, regardless of the order of the power operations of the computer body 1 and the peripheral device 2, normal initialization of the peripheral device can be realized, and the peripheral device can be reliably operated. Therefore, it is possible to reliably prevent a situation in which a peripheral device such as the printer 2 malfunctions after the power is turned on.

[0032]

As described above in detail, according to the present invention, when the power supply of the peripheral device is turned on before the power supply of the computer main body is turned on, the current flows from the peripheral device to the input / output interface of the computer main body. Even when the phenomenon occurs, the state of the interface signal can be maintained so that the peripheral device can execute the initialization processing normally. Therefore, the power is also turned on to the computer itself,
When the system is started, the normal operation of the initialization process can prevent the peripheral device from malfunctioning and can always operate it reliably.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration related to an embodiment of the present invention.

FIG. 2 is an exemplary view for explaining the operation of the input / output interface according to the embodiment;

FIG. 3 is an exemplary view for explaining the operation of the input / output interface according to the embodiment;

FIG. 4 is a block diagram showing a specific circuit of an input / output interface according to the embodiment;

FIG. 5 is a block diagram showing a configuration of a conventional computer system.

FIG. 6 is a flowchart for explaining the operation of a conventional system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Computer main body 2 ... Printer (peripheral device) 3a, 3b ... Parallel port (signal line) 4a, 4b ... I / O buffer 5 ... I / O buffer control circuit 6 ... I / O buffer power supply 10 ... I / O interface Reference Signs List 11 power supply device (system power supply of computer body) 12 internal core power supply 13a, 13b pull-up resistor 14a, 14b I / O buffer (interface signal output means) 15 ... I / O buffer control circuit (control means) 40-42 ... Inverter 43 ... P-channel transistor 44 ... N-channel transistor 45 ... Parasitic diode of P-channel transistor

Claims (7)

[Claims] 1. A computer system including a computer main body having a function of outputting an interface signal to a peripheral device having a dedicated power supply and controlling the operation of the peripheral device, wherein the computer system is provided with the computer main body. An interface signal output unit that is operated by a predetermined power supply included in the system power supply connected to the peripheral device and outputs the interface signal, and a power supply to the interface signal output unit immediately after the peripheral device is turned on. Control means for controlling an input of the interface signal output means so as to set a state of an interface signal suitable for performing an initialization operation of the peripheral device even when a supply state occurs. Computer system. 2. A computer system comprising a computer main body having a function of controlling an operation of the peripheral device by outputting an interface signal to a peripheral device having a dedicated power supply, and outputting the interface signal. Interface signal output means, controlling input of the interface signal output means,
Control means for controlling a logic level of the interface signal; and power supply means provided in the computer main body for supplying power to each of the interface signal output means and the control means; During the immediately following initialization operation,
The interface signal suitable for performing the initialization operation when the power supply to the interface signal output unit occurs in a state where the power supply of the control unit is stopped or an input control state corresponding thereto. A computer system configured to maintain a logic level state. 3. When the power supply from the power supply of the peripheral device to the interface signal output unit occurs immediately after the power supply of the peripheral device is turned on, the control unit stops operating and the peripheral device outputs a signal. 3. The computer system according to claim 1, wherein a logic level state of an interface signal output from said interface signal output means is maintained in a high impedance state so that an initialization operation of the device can be performed. . 4. Immediately after power-on of the peripheral device, in a state where power supply from a power supply provided in the computer main body to the control means and the interface signal output means is stopped, the interface signal output means is turned off. On the other hand, even when a power supply state from the power supply of the peripheral device occurs, the logic level state of the interface signal is maintained in a high impedance state so that the initialization operation of the peripheral device can be performed; And when the interface signal output means is supplied with power from a power supply provided in the computer main body, the interface signal output means sets the interface signal to a logical level effective for operation of the peripheral device. 2. The method according to claim 1, wherein: Of 2, wherein the computer system. 5. A computer system comprising a computer main body and a peripheral device, wherein the input / output interface device is provided in the computer main body and outputs an interface signal necessary for the operation of the peripheral device, the input / output interface device being connected to the peripheral device. The interface signal is output through the signal line provided, and the power can be supplied from the power supply of the peripheral device through the signal line when the power supply from the power supply provided in the computer is stopped. Interface signal output means, controlling input of the interface signal output means,
When the power supply is stopped or the state of input control corresponding thereto, the logic level state of the interface signal corresponding to the initialization operation is maintained among the interface signals so that the initialization operation of the peripheral device can be performed. And an input / output interface device comprising: control means for setting a logic level state of the interface signal in accordance with an operation of the peripheral device when power is supplied. 6. When the power supply of the peripheral device from the power supply of the peripheral device occurs to the interface signal output device immediately after the power supply of the peripheral device is turned on, the interface device operates in a state where the operation of the control device is stopped. 6. The input / output interface device according to claim 5, wherein the signal output means maintains a logic level state of a corresponding interface signal in a high impedance state so that an initialization operation of the peripheral device can be performed. 7. The control means outputs a plurality of control signals for controlling an input of the interface signal output means, and a predetermined logic level of each of the control signals corresponding to a stop state of power supply of the control means. According to the first combination of
A logic level state of the interface signal is maintained in a high impedance state so that an initialization operation of the peripheral device can be performed, and a predetermined second set of logic levels of the control signals is supplied when power is supplied to the control means. The output of the interface signal is prohibited according to the combination, and when the power of the control unit is supplied, the operation of the peripheral device is performed according to the combination of the control signals other than the first combination and the second combination. 7. The input / output interface device according to claim 5, wherein the input / output interface device is configured to set a logic level state of the interface signal.