JPH10260661A - Driving circuit for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the chip area of a driving circuit for display device. SOLUTION: A liquid crystal driving circuit 32 which drives an active matrix type liquid crystal panel 31 uses on driving circuit 190 for two data bus lines 120 and 121. In the driving circuit 190, an input-side changeover switch for switching sampling latches 210A and 210B of two systems is provided, and gradation display data are latched separately in the former half and latter half of one horizontal scanning period and converted into analog voltages. On the side of the liquid crystal panel 31, an output-side changeover switch 140 consisting of a TFT is provided and the data bus lines 120 and 121 are switched in the former half and latter half of the horizontal scanning period to supply the output from a D/A converting circuit 230. The data bus lines 120 and 121 are provided with auxiliary capacitors 150 and 151 to securely hold driving voltages which are applied in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a display device in which display elements are arranged in a matrix type to perform gradation display.

[0002]

2. Description of the Related Art FIG.
FIG. 15 shows the configuration of the prior art disclosed as a diagram, and FIG.
Shows the operation timing of this prior art disclosed as FIG. An input analog video signal Vv is supplied to an analog / digital (hereinafter, abbreviated as “A / D”) converter 1
Is converted into, for example, an 8-bit digital signal. The output of the A / D converter 1 is supplied to an 8-bit parallel input horizontal scanning shift register 2 and a horizontal clock HC.
It is sequentially shifted every K. Horizontal scan shift register 2
Are input to a counter 3 operating as a pulse phase modulator. The counter 3 is loaded with data as a digital video signal during, for example, a horizontal synchronization period in a horizontal retrace period of the analog video signal Vv.
Counter 3 is, for example, an 8-bit synchronous counter, and counts clock signal Vcl.

The sawtooth voltage generator 4 generates a sawtooth voltage as an output Vout which linearly increases in synchronization with the clock signal Vcl and rapidly decreases during the horizontal synchronization period. The output of the sawtooth voltage generator 4 is applied to the drain of the switching MOS transistor 5. The output of the counter 3 is supplied to the gate of the switching MOS transistor 5. The source of the switching MOS transistor 5 is connected to a hold capacitor 6 and a column signal electrode 7. A plurality of column signal electrodes 7
Intersects a plurality of row scanning electrodes 8, and a display element 10 of a liquid crystal cell is connected to the intersection via a switching MOS transistor 9. The row scanning electrodes 8 are sequentially selected by the vertical scanning shift register 11 every horizontal scanning period. An active matrix type liquid crystal display panel 12 is constituted by the column signal electrodes 7, the row scanning electrodes 8, the switching MOS transistors 9 and the display elements 10.

After the digital video signal is loaded, the counter 3 performs a counting operation, and when the count value reaches a constant value, gives an output for turning on the switching MOS transistor 5 to the gate. That is, the switching MOS transistor 5 is controlled to be turned on for a certain period of time at a timing corresponding to each digital video signal input data. On the other hand, the drain of the switching MOS transistor 5 is connected to a sawtooth voltage generating circuit 4.
Is applied.
Therefore, the column signal electrode 7 and the hold capacitor 6 connected to the source of the switching MOS transistor 5 have:
The sawtooth voltage Vc1 from the sawtooth voltage generator 4 is applied through the switching MOS transistor 5 only during the time t shown in FIG. Hold capacity 6
The voltage immediately before the switching MOS transistor 5 is turned off is held, and the display element 10 of the display panel 12 is held.
Are driven by the voltage held in the hold capacitor 6. In FIG. 15, T1 and T2 have A / D converter 1
And the operation timing of the horizontal scanning shift register 2 and the counter 3 as a pulse phase modulator.
The driving of the liquid crystal display device by such a method is hereinafter referred to as a time division driving method.

As a driving method of an active matrix type liquid crystal display device, a method in which a data line is divided into a plurality of driving areas and driven by one data side driving circuit is conceivable in addition to the above-described time division driving method. ing. Such a prior art is disclosed, for example, in Japanese Patent Laid-Open No. 7-181933. FIG. 16 shows the circuit configuration of this prior art disclosed as FIG. 1, and FIG. 17 shows the timing of the operation disclosed as FIG. 16, the display device 20 includes a scan-side shift register 22 and a data-side shift register 23 formed on a glass substrate 21, and the analog line memory 2 provided outside the glass substrate 21.
4, a display voltage is applied to the data lines DL1 to DLn. The scanning lines SL1 to S
Lm and data lines DL1 to DLn are formed, and the thin film transistors Tr11 to Trmn and the pixel capacitance C
11 to Cmn are arranged. Each data line DL1 to D
One end of Ln is connected to switching transistors TG1 to TG
n output terminals. Data lines DL1 to DL
n is because the input terminals of the switching transistors TG1 to TGn are commonly connected by half of the total number thereof,
The driving area is divided into two equal driving areas Ar1 and Ar2.

In the data-side shift register 23, each output terminal is divided into two and connected to respective control terminals of switching transistors TG1 to TGp and TGp + 1 to TGn at corresponding positions. Two switching transistors TG1
By simultaneously driving TGn, the output signal of one stage of the data-side shift register 23 causes a corresponding data line in a plurality of drive regions, for example, DLi, D
Lp + i connected to thin film transistors Tri1 to Tri
m and Tr (p + i) 1 to Tr (p + i) n can be turned on / off simultaneously. Therefore, the time for writing data to each of the pixel capacitors C11 to Cmn, that is, the time for turning on one thin film transistor Tr11 to Trmn can be lengthened in proportion to the number of divided data lines DL1 to DLn.

[0007] As shown in FIG.
Gm is one horizontal scanning period, for example, 6 for an NTSC signal.
During the 1H period of 3.5 μs, each of the scan lines SL1 to SLm
Become high level sequentially. Thereby, each scanning line S
Thin film transistor Tr1 connected to L1 to SLm
1 to Trmn are turned on, and the liquid crystal cells connected to the scanning line can be sequentially selected.

The data side shift register 23 sequentially outputs drive signals S1 to Sp of a number p which is half the number n of the data lines DL1 to DLn, ie, p = n / 2. This output is divided into two drive regions Ar
Switching transistor TG corresponding to 1, Ar2
1 to TGn. When the drive signals S1 to Sp are input to the switching transistors TG1 to TGn, the switching transistors TG1 to TGp and the switching transistors TGp + 1 to TGn at positions corresponding to the drive regions Ar1 and Ar2 are simultaneously turned on.
Switching transistors TG1 to T in driving region Ar1
Gp and the switching transistor T in the driving region Ar2.
Gp + 1 to TGn are stored in one side 24a and the other side 24b of the analog line memory 24 divided into two, respectively.
An activation signal Y1 for the left half of H and an activation signal Y2 for the right half are provided.

Therefore, the pixel capacitances C11 to Cmn, the scanning lines SL1 to SLm, and the data lines DL1 to DL
The switching transistors TG1 to TGp connected to the data lines DL1 to DLp of the drive region Ar1 divided into two by one data side shift register 23 provided on the glass substrate 21 on which Ln is formed, and the data of the drive region Ar2 The switching transistors TGp + 1 to TGn connected to the lines DLp + 1 to DLn are simultaneously
As a whole, they can be driven one by one sequentially. As a result, the period during which the switching transistors TG1 to TGn connected to the data lines DL1 to DLn are on is determined by using a value obtained by dividing one horizontal period 1H by 2 which is the number of divisions of the data lines DL1 to DLn. The time interval is further divided, that is, 2H / n.

[0010]

In recent years, liquid crystal display panels have been required to be larger and have higher definition, and the number of column signal electrodes 7 in FIG. 14 and the number of data lines DL1 to DLn in FIG. There is a strong demand for multiple outputs. As the number of pixels of the liquid crystal panel increases, the number of outputs of the liquid crystal drive circuit for driving the data lines also increases. As a result, the chip area of the liquid crystal driving circuit formed as a semiconductor integrated circuit increases, which leads to an increase in cost.

In the prior art as shown in FIG. 14, a liquid crystal drive circuit for driving a column signal electrode side of the liquid crystal panel 12 has one output of a liquid crystal signal output circuit corresponding to one column signal electrode. Since they are connected, the number of output circuits increases as the number of column signal electrodes 7 increases, and the above-described cost increase due to an increase in chip area cannot be avoided.

In the prior art as shown in FIG.
The thin-film transistors Tr11 to Trmn connected to the corresponding data lines DLi and DLp + i of the plurality of driving regions Ar1 and Ar2 are simultaneously turned on / off by signals output from the data-side shift registers 23 for the stages. I have. The time for writing data to one pixel, that is, the time for turning on one thin film transistor Tr11 to Trmn can be lengthened in proportion to the number of divisions of the data lines DL1 to DLn, thereby improving image quality. Is possible.

However, the data-side shift register 2
3 and the switching transistor TG
Drive signals S1 to Sp for driving 1 to TGn are transmitted, and the number of bus lines for controlling on / off of switching transistors TG1 to TGn is increased. When the number of data lines increases as the size of the liquid crystal panel increases, the number of bus lines for the drive signals S1 to Sp also increases, and the area of a non-display area where no display is performed on the liquid crystal panel increases. In addition, since the number of bus lines is large, power consumption increases. Further, since the drive circuit has a configuration in which a D / A converter is connected for each data line, it is necessary to provide a D / A converter for each data line, which increases the chip area of the drive circuit. Also, since an input terminal of the liquid crystal panel is required for each data line, the number of input terminals of the liquid crystal panel increases as the number of pixels increases. Therefore, the data-side shift register 2
Although it is possible to reduce the number of stages of 3, it is not possible to solve the problem that the chip area of the drive circuit increases and leads to an increase in cost.

An object of the present invention is to reduce the number of conversion circuits for performing gray scale display to be smaller than the number of data lines, and to suppress an increase in the chip area of a drive circuit even when the number of data lines increases. It is an object of the present invention to provide a driving circuit for a display device which can be used.

[0015]

According to the present invention, a data line of a display device in which display elements are formed in a matrix at an intersection with a scanning line is driven by a signal having a gradation level corresponding to video signal data. A conversion circuit that is provided for each of a plurality of predetermined data lines, is provided for each of the conversion circuits, and converts the video signal data to a corresponding gradation level a plurality of times during one scanning period. An output-side switching circuit that switches the plurality of data lines a plurality of times for each scanning period and connects the plurality of data lines to an output of a conversion circuit;
A data holding circuit provided corresponding to each data line, for holding video signal data to be displayed on each data line, and switching the outputs of the plurality of data holding circuits a plurality of times every one scanning period; An input-side switching circuit for performing conversion by giving to the conversion circuit. According to the present invention, a conversion circuit is provided for each of a plurality of data lines of a display device in which display elements are formed in a matrix and is switched by an input-side switching circuit and an output-side switching circuit to handle video signal data a plurality of times. The data is converted into a gradation level and sequentially applied to each data line. The video signal data is held in a data holding circuit provided corresponding to each data line, and is sequentially switched by an input side switching circuit and applied to a conversion circuit. Since only one conversion circuit is required for a plurality of data lines, the chip area when the drive circuit is configured as a semiconductor integrated circuit is reduced, and the increase in the chip area is suppressed even when the number of data lines increases. Can be.

Further, in the present invention, the output-side switching circuit is formed on a display device side. According to the present invention, since the output-side switching circuit is formed on the display device side, the input terminals of the display device need only be the number obtained by dividing the data lines by the plurality, and the number of input terminals of the display device is reduced, Costs can be reduced by reducing the number of connection lines to the circuit.

Further, in the present invention, the display device is an active matrix type liquid crystal display device using TFTs, and the output side switching circuit is an analog switch using TFTs. According to the present invention, an analog switch using a TFT is formed as an output-side switching circuit in an active matrix type TFT liquid crystal display device. Circuits can be incorporated.

Further, the present invention is characterized in that an auxiliary capacitance is provided for each of the data lines. According to the present invention, although the time for driving each data line is shorter than the case where one driving circuit drives one data line, the provision of the auxiliary capacitance allows the auxiliary capacitance driving voltage to be charged and stable. Display can be performed.

Further, the present invention is characterized in that a buffer circuit is provided between an output of each of the conversion circuits and each of the output-side switching circuits. According to the present invention, the driving voltage charged by the auxiliary capacitance can be reduced in impedance by the buffer circuit and supplied to each data line, so that each data line can be sufficiently driven even if the auxiliary capacitance is small. .

According to the present invention, a buffer circuit is provided between the output side switching circuit and each data line.
A storage capacitor is provided on the input side of each buffer circuit. According to the present invention, since the output-side switching circuit is provided on the drive circuit side, a highly efficient switching circuit can be configured by using a process similar to a process for forming a drive circuit as a semiconductor integrated circuit.

[0021]

FIG. 1 shows a schematic electrical configuration of an embodiment of the present invention. The liquid crystal panel 31 is driven by a liquid crystal driving circuit 32 to scan bus lines 110, 111,.
Data bus lines 120 provided so as to intersect with
Are driven. Scan bus lines 110 and 11
, And the data bus lines 120, 121,..., Through thin film transistors (hereinafter, abbreviated as “TFTs”) 130, 131,.
VC2,... Are connected. The gates of the TFTs 130, 131, are connected to the scanning bus lines 110, 111,..., And the drains are connected to the data bus lines 120, 121,. The scanning signals Gj, Gj + 1,... Are sequentially applied to each of the scanning bus lines 110, 111,. As the liquid crystal gate circuit, those equivalent to the vertical scanning shift register 11 in FIG. 14 and the scanning side shift register 22 in FIG. 16 can be used.

Two data bus lines 120 and 121
Are driven by being switched by an output side switch 140. Auxiliary capacitors 150 and 151 are provided in each of the data bus lines 120 and 121.

The liquid crystal drive circuit 32 is provided with one drive circuit 190 corresponding to the two data bus lines 120 and 121. Each drive circuit 190 includes a shift register 2
00, two-system sampling latches 210A, 210
B, an input-side switch 220, which is an analog switch for switching the two-system sampling latches 210A and 210B, and a D / A conversion circuit 230 are provided. The shift register 200 generates a clock signal for taking in gray scale display data into the two systems of sampling latches 210A and 210B according to the sampling clock signal. The input-side switch 220 for switching the sampling latches 210A and 210B is controlled by an externally supplied control signal before and after one horizontal period (1H). Control is performed so as to switch to the B system indicated by the broken line. D
The / A conversion circuit 230 includes sampling latches 210A and 210 switched by the input side switch 220.
Since the n-bit gray scale display data is converted into a gray scale display analog voltage level based on the output of B, the first half of 1H and 1
It is possible to derive a gradation display voltage for the different data bus lines 120 and 121 in the latter half of H. The output side switch 140 is connected to the output side of the D / A conversion circuit 230, and is switched to the data bus line 120 in the first half of 1H, and is switched to the data bus line 121 in the second half of 1H. Therefore, during one horizontal scanning period 1H,
Two data bus lines 120 and 121 are connected to one D / A
It can be driven by the output from the conversion circuit 230.

The D / A converter 230 shown in FIG. 1 includes a decrement counter 240 and a 0 detection decoder 2 as shown in FIG.
50 and an output analog switch 260. When the load signal LOAD is input to the decrement counter 240, the contents of the sampling latches 210A and 210B switched by the input-side switch 220 are loaded and are sequentially subtracted according to the gradation clock CK.
The 0 detection decoder 250 outputs the output analog switch 26 until the contents of the decrement counter 240 become all “0”.
A signal for turning on 0 is output. When all the contents of the decrement counter 240 become “0”, the output analog switch 26
Since 0 is turned off, the output terminals OS1, OS2,... Enter a high impedance state. When the output analog switch 260 is on, the output terminals OS1, OS2,.
Outputs a voltage from a reference power supply provided to a reference voltage terminal 270. The reference power supply voltage is the load signal LOAD
And changes in synchronization with the grayscale clock CK.

On the liquid crystal panel 31 side, output side changeover switches 140 and 141 are provided as analog switches formed by the same process as the TFT for the active matrix, and a data bus line is provided by a control signal for switching between the A system and the B system. Switching between the output terminals 120 and 121 and the output terminal OS1 is performed. Therefore, if the mode is switched to the A side in the first half of the horizontal scanning period, the auxiliary capacitance 150 is charged, and in the latter half of the horizontal scanning period, the auxiliary capacitance 151 is charged.

FIG. 3 shows a specific circuit configuration example of the decrement counter 240, the 0 detection decoder 250, and the output analog switch 260 when the gray scale display data is n = 6 bits. An arbitrary bit configuration can be similarly realized. The 6-bit data D0 to D5 are provided from the input side switch 220. Load signal LOA
When D becomes the high level of the logical value “1”, the D flip-flops F0 to F5 change the data D0 to D5 to the logical value “1”.
Is set via NAND gates NG0 to NG5, and when data D0 to D5 are logical value "0", inverters N0 to N5 and NAND gates NG00 to NG are set.
Reset via G05. In each of the D flip-flops F0 to F5, the data input D is connected to the inverted output / Q, and the output Q is connected to the clock input CK of the next stage. The clock input CK of the first stage D flip-flop F0 is
The output of NAND gate NGI0 is provided. NAND
The grayscale clock CLK and the output of the 0 detection decoder 250 are supplied to the input of the gate NGI0 via the inverter NI0. The 0 detection decoder 250 is configured by a 6-input NOR gate. Each input terminal is connected to the output Q of each of the D flip-flops F0 to F5.

When the load signal LOAD is input, each of the D flip-flops F0 to F0 constituting the decrement counter 240
The display data from the sampling latch 210A or 210B is loaded into F5. Next, the gradation clock signal C
The display data loaded is decremented according to the LK. The NOR gate constituting the 0 detection decoder 250 has:
While each of the D flip-flops F0 to F5 holds data of a logical value "1" even with one bit, it generates a decode signal for turning on the output analog switch 260. When all the contents of the outputs Q of the D flip-flops F0 to F5 constituting the decrement counter 240 become a logical value "0", the output of the NOR gate is inverted and the output analog switch 260 is turned off. It becomes a high impedance state. At the same time, the clock input CK of the first stage D flip-flop F0 of the decrement counter 240 is disconnected from the grayscale clock signal CLK, so that the decrement operation stops and this state is maintained until the load signal LOAD is input again.

FIG. 4 shows a timing chart of the liquid crystal signal output circuit of the present embodiment. 1/2 of one horizontal period
In the first half period, the gradation display data "3" latched by the A system of the sampling latch 210A is applied to the pixel capacitor VC1 via the analog switch 140A of the liquid crystal panel, and the sampling latch is applied in the second half of the remaining half period. 21
The gradation display data “2” latched by the B system of 0B is switched and applied to the pixel capacitance VC2 via the analog switch 140B of the liquid crystal panel 31. This makes it possible to drive two display pixels with one liquid crystal signal output terminal OS. As described above, in the present embodiment, two data bus lines can be switched and driven by one terminal of the liquid crystal signal output circuit, and the number of output lines can be reduced to half. Cost can be reduced by reducing the chip area.

FIG. 5 shows a schematic configuration of another embodiment of the present invention. The configuration of the present embodiment is similar to the configuration shown in FIG. 2, and corresponding portions are denoted by the same reference numerals and redundant description is omitted. In this embodiment, the liquid crystal panel 41 includes auxiliary capacitors 150 and 15 such as the liquid crystal panel 31 shown in FIG.
1, ... is not provided. Data bus lines 120, 12
The number of the data bus lines 120 and 12 is sufficiently large even if the driving is performed twice in one horizontal scanning period.
, Can be driven, the auxiliary capacity 15
., And the cost of the liquid crystal panel 41 can be reduced.

FIG. 6 shows a configuration of still another embodiment of the present invention. In the present embodiment, portions corresponding to the configuration in FIG. 2 are denoted by the same reference numerals, and redundant description will be omitted. In the present embodiment, a buffer circuit using an operational amplifier 280 is provided on the output side of the D / A conversion circuit 233 in each drive circuit 195 constituting the liquid crystal drive circuit 42, and the output impedance of the drive circuit 195 is converted to a low impedance.
The time constant for writing data to the data bus lines 120, 121,... Provided with the auxiliary capacitors 150, 151,. Examples of the operational amplifier 280 include the features 95-2275 and 96-33 filed by the present applicant.
9 and the like, a full-range compatible operational amplifier can be suitably used.

FIG. 7 shows a configuration of still another embodiment of the present invention. In the present embodiment, portions corresponding to the configuration in FIG. 2 are denoted by the same reference numerals, and redundant description will be omitted. The liquid crystal drive circuit 52 of this embodiment includes a counter 300, a data latch 330 as a D / A conversion circuit 235 provided for each drive circuit 290, a comparison circuit 340, and an output analog switch 260. Display data of two pixels is distributed and taken in one pixel at a time into the two sampling latches 210A and 210B. The input-side switch 220 is controlled by an external control signal.
In the first half of one horizontal period, sampling latch 2
The output of 10A is provided to data latch 330. In the latter half of one horizontal period, the output of the sampling latch 210B is given to the data latch 330 as the B system. Counter 300
Are initialized by the latch signal LS, and are configured to count the grayscale clock CLK. Comparison circuit 340
Is the count value from the counter circuit 300 and the data latch 3
The output analog switch 260 is turned on until the display data latched by 30 is compared with the display data. The reference voltage terminal 270 has a latch signal LS
Since the reference power supply voltage waveform synchronized with the 周期 cycle is input, the output voltage that changes following the reference power supply voltage can be applied to the liquid crystal panel 31 while the output analog switch 260 is on. it can. Comparison circuit 340
Turns off the output analog switch 260 when the output value of the counter 300 matches the data latched by the data latch 330, and outputs the output voltage at that time to the auxiliary capacitors 150, 151,. Capacity VC
n. Therefore, the operation of the configuration of FIG. 7 is performed in the same manner as in FIG.

FIG. 8 shows an embodiment in which the auxiliary capacitors 150, 151,... Are omitted using the liquid crystal panel 41 shown in FIG. In the present embodiment, portions corresponding to the above-described embodiments are denoted by the same reference numerals, and redundant description will be omitted. When the output impedance of each drive circuit 290 of the liquid crystal drive circuit 52 is low, or when a low impedance conversion circuit such as an operational amplifier is provided, stable display is performed without providing the auxiliary capacitors 150, 151,. be able to.

FIG. 9 shows a schematic electrical configuration of still another embodiment of the present invention. In the present embodiment, the output side switch 350 is provided not on the liquid crystal panel 61 but on each drive circuit 295 side of the liquid crystal drive circuit 62. From the liquid crystal drive circuit 62, each data bus line 12 of the liquid crystal panel 61
.. Can be obtained for each of 0, 121,.
As 1, a conventional product can be used. In the liquid crystal drive circuit 62, since one D / A conversion circuit 230 can be used for the two data bus lines 120 and 121, the chip area as the semiconductor integrated circuit can be reduced to reduce the cost. Can be.

FIG. 10 shows a schematic electrical configuration of still another embodiment of the present invention. In the present embodiment, portions corresponding to the above-described embodiments are denoted by the same reference numerals, and redundant description will be omitted. In the present embodiment, the D / D provided for each drive circuit 390 on the liquid crystal drive circuit 72 side
A buffer by an operational amplifier 280 is inserted between the output side of the D / A converter 365 of the A conversion circuit 360 and the output side switch 350. Since the output impedance is converted to a low impedance by the buffer of the operational amplifier 280, the data bus lines 120 and 121 provided with the supplementary capacitors 150, 151,... Can be sufficiently driven with a short time constant.

FIG. 11 shows an example of the configuration of the D / A converter 365 of the embodiment shown in FIG. This D / A converter 365 is
A 6-bit resistor string is configured as a single-stage D / A conversion circuit, and 63 resistors R connected in series
1 to R63 are replaced with six-stage switch circuits SW11 to SW61.
Is switched according to 6-bit digital data, and an analog output of 64 gradations can be obtained. FIG.
An example in which the output side changeover switch 350 is configured by S will be described. N-channel MOS transistor 351 and P-channel M
The gate composed of the OS transistor 352 and the gate composed of the N-channel MOS transistor 353 and the P-channel MOS transistor 354 can be commonly connected on the output side, and can be switched on the input side.

FIG. 13 shows a schematic electrical configuration of still another embodiment of the present invention. In the present embodiment, portions corresponding to the preceding embodiments are denoted by the same reference numerals, and redundant description will be omitted. In the present embodiment, the liquid crystal panel 8
1 includes storage capacitors 150 and 15 such as the liquid crystal panel 61.
Are not provided, auxiliary capacitors 410 and 411 for each of the data bus lines 120 and 121 and a buffer circuit using an operational amplifier 280 are provided in each drive circuit 400 on the liquid crystal drive circuit 82 side to provide stable and low impedance. Each of the data bus lines 120 and 121 is driven.
In the present embodiment, the liquid crystal panel 81 is a system in which display data of a plurality of systems is distributed and sampled in one output circuit.
The liquid crystal drive circuit 82 can compensate for the reduction in the time for writing to the display pixel by providing the auxiliary capacitors 410 and 411, thereby reducing the manufacturing cost of the liquid crystal panel 81.

In each of the embodiments described above, gray scale display is performed with a gray scale number n of 6 bits. However, when gray scale display is performed with another bit count as described above, basically, The same can be done. Although the display device is described as an active matrix type liquid crystal display device, a matrix display device capable of gradation display according to a voltage level, for example, an electroluminescence (abbreviated as “EL”) or plasma display device is also used. Similarly, gradation display can be performed, and the number of conversion circuits can be reduced. Also,
A configuration in which three or more data bus lines are switched and driven by one drive circuit is also possible.

[0038]

As described above, according to the present invention, the number of conversion circuits can be reduced with respect to the number of data lines, so that the chip area of a drive circuit formed as a semiconductor integrated circuit is reduced, and power consumption is reduced. Can be reduced. Further, even if the display device has a large screen and the number of data lines is large, the number of drive circuits is reduced to one-fourth of the number, so that the number of liquid crystal signal output circuits used can be reduced and the display device can be assembled. The cost as a combined display module can also be effectively reduced.

According to the present invention, since the output-side switching circuit is formed on the display device side, the number of input terminals of the display device can be reduced, and the number of signal lines connected to the signal output circuit can be reduced. it can.

According to the present invention, an output-side switching circuit using TFTs is integrally formed in an active matrix type liquid crystal display device using TFTs, so that the number of input terminals can be reduced.

Further, according to the present invention, since an auxiliary capacitor is provided for each data line, stable display can be performed even if the time for driving the data line is shortened.

Further, according to the present invention, even if an auxiliary capacitor is provided in each data line and the load increases, the data line can be sufficiently driven by the buffer circuit.

According to the present invention, since the output-side switching circuit is provided on the drive circuit side, there is no need to supply a control signal to the display device side. Further, a conventional display device can be used as it is, and a chip area can be reduced on the driving circuit side.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic electrical configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a more specific configuration of the D / A conversion circuit 230 of FIG.

FIG. 3 is a decrement counter 240 and a 0 detection decoder 2 shown in FIG. 2;
FIG. 3 is a logic circuit diagram showing a more specific configuration of the analog switch 50 and the output analog switch 260.

FIG. 4 is a timing chart showing the operation of the embodiment of FIG.

FIG. 5 is a block diagram showing a schematic electrical configuration of another embodiment of the present invention.

FIG. 6 is a block diagram showing a schematic electrical configuration of still another embodiment of the present invention.

FIG. 7 is a block diagram showing a schematic electrical configuration of still another embodiment of the present invention.

FIG. 8 is a block diagram showing a schematic electrical configuration of still another embodiment of the present invention.

FIG. 9 is a block diagram showing a schematic electrical configuration of still another embodiment of the present invention.

FIG. 10 is a block diagram showing a schematic electrical configuration of still another embodiment of the present invention.

11 is a D / A converter 235 of the embodiment shown in FIG.
3 is an equivalent electric circuit diagram of FIG.

FIG. 12 is an equivalent electric circuit diagram of the output side changeover switch 350 of the embodiment of FIGS. 9 and 10;

FIG. 13 is a block diagram showing a schematic electrical configuration of still another embodiment of the present invention.

FIG. 14 is a block diagram showing a schematic electrical configuration of one prior art.

FIG. 15 is a timing chart showing the operation of the prior art of FIG.

FIG. 16 is a block diagram showing a schematic electrical configuration of another prior art.

FIG. 17 is a timing chart showing the operation of the prior art of FIG. 16;

[Explanation of symbols]

31, 41, 61, 81 Liquid crystal panel 32, 42, 52, 62, 72, 82 Liquid crystal drive circuit 110, 111 Scan bus line 120, 121 Data bus line 130, 131 TFT 140, 141 Output side changeover switch 150, 151 410, 411 Auxiliary capacitance 190, 195, 290, 295, 390, 400 Driving circuit 200 Shift register 210A, 210B Sampling latch 220 Input side changeover switch 230, 233, 235, 238, 360 D / A conversion circuit 240 Decrease counter 250 0 Detection decoder 260 Output analog switch 270 Reference voltage terminal 280 Operational amplifier 300 Counter 330 Data latch 340 Comparison circuit 365 D / A converter

Claims (6)

[Claims] 1. A circuit for driving a data line of a display device in which display elements are formed in a matrix at intersections with scanning lines with a signal having a gradation level corresponding to video signal data, A conversion circuit that is provided for each of a plurality of predetermined data lines and converts the video signal data to a corresponding gray level a plurality of times during one scanning period; and a conversion circuit that is provided for each conversion circuit and An output-side switching circuit that switches the plurality of data lines by a plurality of times and connects to the output of the conversion circuit; and a data holding circuit provided corresponding to each data line and holding video signal data to be displayed on each data line. And an input-side switching circuit that switches the outputs of the plurality of data holding circuits a plurality of times for each scanning period and provides the converted data to the conversion circuit for conversion. Driving circuit of a display device according to claim. 2. The driving circuit according to claim 1, wherein the output-side switching circuit is formed on a display device side. 3. The driving circuit according to claim 2, wherein the display device is an active matrix type liquid crystal display device using TFTs, and the output side switching circuit is an analog switch using TFTs. 4. The drive circuit according to claim 1, wherein an auxiliary capacitor is provided for each of the data lines. 5. The drive circuit according to claim 4, wherein a buffer circuit is provided between an output of each of the conversion circuits and each of the output-side switching circuits. 6. The buffer circuit according to claim 1, wherein a buffer circuit is provided between the output switching circuit and each data line, and an auxiliary capacitor is provided on an input side of each buffer circuit. The driving circuit of the display device according to the above.