JPH10243548A - Line-to-ground fault detector for high-voltage distribution line - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a line-to-ground fault with high reliability by outputting a line-to-ground fault signal when the total time for which a phase difference anomaly signal is output when a specified time has passed after the detection of both a detection signal for zero-phase- sequence voltage and a detection signal for zero-phase-sequence current, exceeds a specified value. SOLUTION: The results of detection output from the zero-phase-sequence voltage level detecting circuit 4 and zero-phase-sequence current level detecting circuit 5 of the detector are input to a NAND gate 9. The inverted value of the conjunction of the two inputs is input to a specified time averaging circuit 10, and the result of comparison is also input from a zero-phase-sequence voltage/zero-phase-sequence current phase comparing circuit 6. The circuit 10 is actuated when both a zero-phase-sequence voltage and a zero-phase- sequence current are detected. Then the circuit 10 measures a time for which the value of input from the circuit 6 is '1', calculates a ratio of the measured time to a time which has passed after the stating point of the measurement, and sends the calculated value to a judging circuit 11. The judging circuit 11 judges whether the value of output when a specified time has passed after the start of the operation of the circuit 10 is larger than a specified value. If the output value is larger than the specified value, the judging circuit 11 outputs a line-to- ground fault signal. As a result line-to-ground faults can be detected with reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting a ground fault generated in a high-voltage distribution line.

[0002]

2. Description of the Related Art Conventionally, ground faults generated in a high-voltage distribution line have been detected by monitoring the zero-phase of the high-voltage distribution line. In other words, abnormalities in the levels of the zero-phase voltage (hereinafter referred to as Vo) and the zero-phase current (hereinafter referred to as Io) of the high-voltage distribution line and the occurrence of a ground fault are considered when there is a deviation between the phases of Vo and Io. I was FIG. 4 is a block diagram showing a configuration of a conventional ground fault detecting device. Reference numeral 1 denotes a well-known zero-phase extracting unit, which includes a transformer for an instrument, a current transformer, and the like, and extracts a zero-phase from a high-voltage distribution line. The extracted zero-phase voltage and current are input to a zero-phase voltage filter 2 and a zero-phase current filter 3, respectively, and then input to a zero-phase voltage level detection circuit 4 and a zero-phase current level detection circuit 5, respectively. It is determined whether the phase current and the zero-phase voltage are each equal to or higher than a predetermined level.

More specifically, Vo and Io composed of analog signals are converted into full-wave rectified DC, and whether or not the peak value is equal to or greater than a certain threshold value is determined. , And output as a rectangular wave signal clipped to an amplitude corresponding to a continuous cycle. The zero-phase current and the zero-phase voltage input as analog signals are converted into rectangular wave signals each having a zero cross point detected and clipped to a constant amplitude, and input to the zero-phase voltage / zero-phase current phase comparison circuit 6. Is done. The comparison circuit 6 compares the two phases, determines whether the lead / lag is equal to or greater than a predetermined value, and outputs the determination result to an AND gate 7.
To enter. Here, when the zero-phase voltage level and the zero-phase current level are equal to or higher than a certain value and there is a difference between the phase of the zero-phase voltage and the phase of the zero-phase current, the AND condition of the AND gate 7 is satisfied and the output is performed. You. The output result of the satisfaction of the logical product condition is input to the timer 8, and after a certain period of time, a ground fault detection signal is output.

FIG. 5 is a timing chart showing the operation in FIG. 4. When a ground fault occurs, an AND output is made for substantially the same period as the occurrence period, and when the period is longer than the timer value T0, a ground fault occurs. A detection signal is output. Incidentally, the waveforms of Vo and Io at the time of a ground fault involving an insulator arc or a cable arc often have a steep pulse shape.
Therefore, to distinguish it from high-frequency noise, a capacitor C
A CR type analog integrator circuit using a combination of a resistor and a resistor R is used.

[0005]

However, this C
In an R-type analog integrating circuit, Vo and Io
If the phase difference fluctuates with time, it is difficult to detect accurately. As a result, the phase comparison determination data of the ground fault detection device becomes unstable, and even if a ground fault occurs for a specified time period or more, the ground fault is not detected and proper protection of the high-voltage distribution line may not be performed. Was. FIG. 6 is a timing chart showing the operation in that case. That is, if the waveform distortion of Vo and Io is large at the time of the ground fault, an error (such as a load-side ground fault but a power-supply-side ground fault) occurs in the phase comparison result, and the AND output is partially lost. A valid signal within the detection time limit will not be counted. As a result, despite the fact that the ground fault occurs more than the prescribed time period in total, since each of the AND output periods T1, T2, T3 is shorter than the timer value T0, a situation occurs in which the ground output is not detected as a ground fault. .

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a first aspect of the present invention provides a means for extracting a zero-sequence voltage and a zero-sequence current of a high-voltage distribution line. A zero-phase voltage filter that passes only the predetermined frequency band, a zero-phase current filter that receives the extracted zero-phase current and passes only the predetermined frequency band, and a zero-phase voltage level output from the zero-phase voltage filter is constant. A zero-phase voltage detection circuit that outputs a zero-phase voltage detection signal when the value is equal to or greater than
A zero-phase current detection circuit that outputs a zero-phase current detection signal when the zero-phase current level output from the zero-phase current filter is equal to or higher than a predetermined value; and zeros output from the zero-phase voltage filter and the zero-phase current filter, respectively. A zero-phase voltage / zero-phase current phase comparison circuit for comparing the phases of the phase voltage and the zero-phase current and outputting a phase difference abnormality signal when the phase difference between the two is abnormal; In a high-voltage distribution line ground fault detection device that outputs a ground fault detection signal when all signals of a voltage detection signal, a zero-phase current detection signal, and a phase difference abnormality signal are output for a predetermined time or more, a zero-phase voltage detection signal It operates while the zero-phase current detection signal is output, measures the total time during which the phase difference abnormal signal is output, and outputs the zero-phase voltage detection signal and the zero-phase current detection signal together for a predetermined time. Has elapsed, Has been read output total time of the phase difference error signal, the value to output a ground fault detection signal if exceeds a predetermined value.

According to a second aspect of the present invention, in the first aspect of the present invention, while the zero-phase voltage detection signal and the zero-phase current detection signal are both being output, the value of the binarized phase difference abnormal signal is cycled. An up-down counter that counts up when the value is 1 and counts down when the value is 0, reads the count value of the up-down counter after a predetermined time has elapsed, and reads the count value when the value is positive. Outputs a fault detection signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention. The configuration shown in FIG. 1 is a modification of the conventional configuration shown in FIG. 4, and a description of common parts is omitted, and only different parts will be described. The detection results output from the zero-phase voltage level detection circuit 4 and the zero-phase current level detection circuit 5
The input is input to the gate 9, and the inverted value of the logical product of the two inputs is input to the specified time averaging circuit 10.

Also, a zero-phase voltage / zero-phase current phase comparison circuit 6
Is also input to the specified time averaging circuit 10.
The circuit 10 starts operation when the input from the NAND gate 9 is 0, that is, when both the zero-phase voltage and the zero-phase current are detected, measures the time when the input value from the circuit 6 is 1, and measures the time. The ratio between the time and the elapsed time from the start of the measurement is calculated, and the value is sent to the determination circuit 11. The ratio obtained here takes a value from 0 to 1, and becomes larger as the zero-phase phase difference abnormality occurrence time is longer. Discrimination circuit 11
Determines whether the output value is greater than a predetermined value, here 0.5, from the circuit 10 when a predetermined time has elapsed after the operation of the circuit 10 is started, and outputs a ground fault detection signal if the output value is larger than 0.5. I do.

FIG. 2 is a block diagram showing a specific configuration of the specified time averaging circuit 10 and the discriminating circuit 11 shown in FIG. 1, and FIG. 3 is a timing chart showing signals input to and output from each section shown in FIG. is there. Hereinafter, the operation of each unit in FIG. 2 will be described with reference to the timing chart of FIG. A flip-flop (F / F) 21 in FIG. 2 corresponds to the zero-phase voltage / zero-phase current phase comparison circuit 6 in FIG. Is entered.
The zero-phase voltage level c and the zero-phase current level d are input to the NAND gate 9, and the output e thereof is output to the F / F 21, the up / down counter 22, and the reset terminal R of the counter 23.
Is input to

That is, the F / F 21 and the counters 22 and 2
In the case of No. 3, when the inputs c and d of the NAND gate 9 both become 1 and the output e is inverted to 0, the reset is released and the operation starts. When the F / F 21 starts operation,
At the timing of the rising edge of the zero-phase current phase b, the value of the zero-phase voltage phase a is sent to the next-stage counter 22 as the F / F output f. Here, the F / F output f becomes 1 when the phase difference between the zero-phase voltage and the current is abnormal due to a ground fault.

The up / down counter 22 also starts operating when the output e is inverted to 0, counts up / down the value of the F / F output f at the timing of the sampling clock g, and outputs h while the count value is 0 or positive. Is set to 1 and 0 is output during a negative period. That is, the count value is incremented while the value of the F / F output f is 1, and decremented while the value of the F / F output f is 0, so that the period during which the F / F output f is 1 exceeds half of the whole. , The counter output h becomes 1. The output h of this counter 22 is F / F2
4 is input.

The counter 23 functions as a timer, and starts operating when the output e is inverted to 0. When a predetermined number of time counting clocks are counted, the counter output i
Is inverted to 1 and input to the C terminal of the next stage F / F 24. The F / F 24 outputs the value of the output h of the counter 22 as a ground fault detection output j at the timing when the output i of the counter 23 is inverted to 1.

In the phase determination in the present invention, the zero cross point of Vo and Io is detected, converted into a rectangular wave signal clipped to a constant amplitude, and the state of the other signal is changed at the rise / fall timing of one signal. Judgment is made, an edge is detected using a flip-flop or the like in accordance with a predetermined phase relationship between the two (in this case, a phase fault in which a ground fault has occurred on the load side), and a phase judgment result is output. The time from the fall of the NAND output to the rise of the NAND output is counted by the detection time counter, and the ground fault direction is determined with reference to the average data of the up / down counter at the time when the detection time is satisfied.

In this way, even if data that cannot be determined to be positive or negative occurs due to lack of waveforms of Vo and Io, a majority test is performed based on the number of positive and negative data within the detection time period. If the number of positive data is half or more, it can be determined that a ground fault has occurred. In the above-described embodiment, the output can be determined by averaging the NAND output for a certain period of time. For example, 1
This can be dealt with by simple processing such as taking a majority decision with sampling of / 0 data at 10 ms. Also, the averaging process in the present invention can be realized by software, and the averaging determination threshold can be set to another ratio other than the same number of positive and negative data. It is.

[0016]

As described above, according to the present invention, the phase difference between the zero-sequence voltage and the zero-sequence current changes with time and is detected as in a ground fault accident involving an arc. Even if the abnormality becomes discontinuous, the ground fault can be reliably detected,
It is possible to improve the reliability of the ground fault detecting device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a main part of FIG. 1;

FIG. 3 is a timing chart showing signals input to and output from each unit in FIG. 2;

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a timing chart showing the operation in FIG.

FIG. 6 is a timing chart showing the operation in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Zero-phase extraction means 2 Zero-phase voltage filter 3 Zero-phase current filter 4 Zero-phase voltage level detection circuit 5 Zero-phase current level detection circuit 6 Zero-phase voltage / zero-phase current phase comparison circuit 9 NAND gate 10 Specified time averaging circuit 11 Discrimination circuit 21 Flip-flop (F / F) 22 Up / down counter 23 Counter 24 F / F

Claims (2)

[Claims] 1. Means for extracting a zero-phase voltage and a zero-phase current of a high-voltage distribution line, a zero-phase voltage filter that receives the extracted zero-phase voltage and passes only a predetermined frequency band, and an extracted zero-phase current A zero-phase current filter that inputs only a predetermined frequency band and a zero-phase voltage detection circuit that outputs a zero-phase voltage detection signal when the zero-phase voltage level output from the zero-phase voltage filter is equal to or more than a certain value. A zero-phase current detection circuit that outputs a zero-phase current detection signal when the zero-phase current level output from the zero-phase current filter is equal to or greater than a certain value; and a zero-phase voltage filter and a zero-phase current filter. A zero-phase voltage / zero-phase current phase comparison circuit that compares the phases of the zero-phase voltage and the zero-phase current and outputs a phase difference abnormality signal when there is an abnormality in the phase difference between the two. Zero-phase voltage detection signal A zero-phase voltage detection signal and a zero-phase current in a high-voltage distribution line ground-fault detection device that outputs a ground-fault detection signal when all of the zero-phase current detection signal and the phase difference abnormality signal are output for a certain period of time or more. A means that operates while the detection signal is output to measure the total time during which the phase difference abnormality signal is output, and a predetermined time when both the zero-phase voltage detection signal and the zero-phase current detection signal are output. Means for reading the total output time of the phase difference abnormality signal measured up to that time, and outputting a ground fault detection signal if the value exceeds a predetermined value. Ground fault detector for high voltage distribution lines. 2. The ground fault detecting device for a high-voltage distribution line according to claim 1, wherein the binary phase difference is output while both the zero-phase voltage detection signal and the zero-phase current detection signal are being output. An up / down counter that periodically samples the value of the abnormal signal, counts up when the value is 1, and counts down when the value is 0, reads the count value of the up / down counter after a predetermined time has elapsed, and reads the value A ground fault detection device for a high-voltage distribution line, which outputs a ground fault detection signal when positive.