JPH09121549A - Ac output controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an inverter which shows a high control precision and excellent stability. SOLUTION: In an inverter for DC-AC conversion which has an inverter bridge controlled by a PWM controller, the PWM control is performed in a first control loop 22a by using the difference between the AC instantaneous value of an inverter output and the amplitude of a waveform datum which is read out of an AC waveform memory. Further, the amplitude value of the waveform datum is multiplied by a factor which is adjusted in accordance with the error between the AC average value of the current or voltage of the inverter output and a control target value and the PWM control is performed in a second control loop 22b by using the waveform datum having the adjusted amplitude. As the factor by which the waveform datum is multiplied is adjusted by a delta method wherein only a minute increase/decrease is operated, an inverter which shows a high precision and excellent stability can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC output control device, and more particularly to an inverter for converting DC power into AC power and feeding the load to the load, that is, a DC voltage is chopped by a switching element to generate positive and negative pulses. A switching circuit for generating alternating alternating voltage, and a PWM for giving a PWM pulse to the switching circuit so that the alternating output voltage becomes a sinusoidal alternating voltage of a predetermined frequency in time series.
The present invention relates to an alternating-current output control device that is preferably applied to a so-called electronic inverter having a controller.

[0002]

2. Description of the Related Art The above-mentioned switching circuit of an inverter of this type will be described with reference to FIG. 1 showing an embodiment of the present invention.
b) between one of the AC output terminals (4a) and one of the DC voltage input terminals (2a), and between the other of the AC output terminals (4b) and the other of the DC voltage input terminals (2b). , A first set of switching circuits (Qu, Qy, 3u, 3y) that are turned on / off synchronously at the same time,
And between the one of the AC output terminals (4a) and the other of the DC voltage input terminals (2b), and the other of the AC output terminals (4b)
The second set of switching circuits (Qv, Qx, 3v,
3x), and the boost latons at its AC output terminals (4a, 4b).
(6) The primary winding is connected and the secondary winding is connected to the load output terminal.
It is connected to (14a, 14b).

The first and second sets of switching circuits (Q
u, Qy, 3u, 3y), (Qv, Qx, 3v, 3x), the rectangular wave voltage obtained by the PWM pulse switching is the step-up transformer (6)
At 0), it is smoothed to a low frequency AC voltage (eg 50Hz) and output from the load output terminals (14a, 14b) to the load (LD). This AC output voltage and current are fed back to the power control circuit (16). The power control circuit (16) controls the duty ratio of the PWM pulse so that the output voltage has a target value.

In the case of such AC output voltage control by PWM (pulse width control), the relationship of Vout = 2Vin (D-0.5) is established between the duty ratio D of the PWM pulse and the AC output voltage instantaneous value Vout. Is substantially established, and the output AC voltage is increased to 50H by increasing / decreasing the duty ratio D at, for example, 50 Hz.
z.

In the PWM system, sine wave level data (high level width of PWM pulse, duty, etc.) corresponding to an address using a phase as an address in a memory such as a ROM.
Stored for 0 to 90 degrees, 0 to 180 degrees, or 0 to 360 degrees, counts clock pulses to form phase data, reads the level data corresponding to the phase data from the memory, and reads the read level. PWM based on data
A pulse is generated, and based on this PWM pulse, the ON / OFF drive of each of the above-mentioned switching circuits is performed. As a result, a sine wave AC voltage with high waveform accuracy is generated.

Since such an inverter (DC / AC power converter) has characteristics of small size and high efficiency, it has been widely used in recent years as a power supply circuit for various electronic equipment such as an information processing apparatus. Conventionally, most of the power control circuits (16) used dedicated analog ICs, but in recent years analog ICs have been used.
A digital processing device, specifically a microcomputer or a one-chip microcomputer or CP
It has been realized by replacing it with U and incorporating a control program into it. Since the digital processing device can realize high-level control of the inverter circuit with a small number of elements, a highly functional and inexpensive inverter is provided. When the digital processing device is the main body of the power control circuit (16),
The AC output voltage is converted into voltage data by A / D conversion, the duty ratio D of the drive pulse, that is, the PWM pulse given to the above-mentioned switching circuit is determined by the reference sine wave level data, and this duty ratio D is corrected by the voltage data. Thus, the AC output voltage can be controlled to a target level. The duty ratio D of the PWM pulse is generally proportional to the input data (reference sine wave level data, voltage data) and is 0 to 100% or α to (100-α).
% And α vary within a range of several%.

[0007]

However, when electric power is supplied to the load, the AC voltage applied to the load becomes a sine wave due to the electric characteristics or fluctuations of the load and the characteristics of the electric circuit including the switching circuit to the load. It may be distorted, the AC voltage level may fluctuate, an overcurrent may flow, or a DC component may be included (AC level shift in the positive or negative direction). These not only occur temporarily but also steadily, which not only causes power loss but also causes a failure in the load and / or the inverter itself. In particular, for a load requiring a constant current, a constant voltage and / or a high sine wave waveform accuracy, the load may cause an operation error or a functional deterioration.

The output load of the above-mentioned switching circuit may include an inductance element such as a step-up transformer (6) and a reactor (10), and the load element (LD) may also have a similar inductance element. In this case, when a direct current component is superimposed on the alternating current output, the direct current component saturates the magnetic core of the inductance element, and as a result, the inductance of the inductance element decreases, impairing the normal operation or function of the inductance element. Be done. Even if the switching circuit described above performs switching operation to output only the AC component, the DC component may be superimposed on the AC output due to variations in the characteristics of other inverter components and the effects of external noise. , It is necessary to suppress or suppress the DC component.

Therefore, in the case of the conventional analog IC, a method of biasing the feedback voltage with the DC voltage for correcting the DC component is adopted. Similarly, when a digital processing device is used, the feedback voltage A / D
By applying a DC bias to the voltage before conversion,
Similarly, the DC component can be corrected. However, the DC voltage for correcting the DC component is not a fixed value (single value) but needs to be adjusted, so the DC bias circuit becomes complicated and the number of additional components increases.

In order to suppress the direct current component of the alternating current output, in order to correct the duty ratio D of the PWM pulse by digital arithmetic processing in the digital processing device, for example, it was decided to output a sine wave alternating current of a predetermined level. The correction amount NC for DC component correction may be uniformly added to the PWM data NCPU, and the data may be shifted in one direction. That is, the data NPWM that determines the duty ratio D of the PWM pulse may be set as NPWM = NCPU + NC. In this case, the minimum change width ΔD of the duty ratio D is determined by the number of bits Nb of the input data (reference sine wave level data and feedback voltage data), and its value is ΔD = [1 / (2 Nb power)] × It will be 100%.

When the input data has a large number of bits (digits) such as 16 bits, the quantization range is 2 16 = 65.
Since the duty ratio can be specified with a fine width of 536 steps, it is possible to easily reduce the DC component to a range that does not affect even with the above correction method, but when the number of bits is small, such as 8 bits, There are cases in which the variation width ΔD of the duty ratio is coarse, as 2 8 = 256 steps, and the DC component cannot be suppressed more finely and accurately. Therefore, in order to cancel the DC component, it is necessary to use a digital processing device having a large number of bits, which increases the cost of parts.

Therefore, the present invention has been made in order to eliminate the above-mentioned drawbacks, and its first object is to provide an inverter for generating an AC output voltage having a high sine wave waveform accuracy, and to suppress an overcurrent. A second object is to provide an inverter having a high effect, a third object is to provide an inverter having a high constant voltage characteristic, and a fourth object is to suppress the DC component of the output AC. Further, the present invention provides a digital processing type inverter that obtains a high DC component suppressing effect by processing data with a relatively small number of bits.
The purpose of.

[0013]

An AC output control device according to the present invention is an AC output control device for controlling an AC output to be supplied to a load based on waveform data read from an AC waveform memory. An instantaneous value detecting means for detecting an instantaneous value of the voltage or current, an average value detecting means for accumulating the instantaneous value of the voltage or current supplied to the load for each specific phase section, and calculating an AC average value; Or, a first control means for forming first control data based on a difference between the instantaneous value of the current and the waveform data from the AC waveform memory is compared with the AC average value and a predetermined control target value, Second control means for forming second control data by multiplying the amplitude value of the waveform data from the waveform memory by a coefficient value increased or decreased according to the magnitude relation between the two, and the first and second control data. By Controlled, current or voltage, characterized in that it comprises an AC generator for generating an output which is controlled with respect to the control target value. Further, the alternating current generating means performs a switching operation by a PWM means for generating a PWM pulse whose duty changes with time according to an amplitude value of the input control data, and an output pulse of the PWM means to convert a direct current input into an alternating current output. And an inverter bridge switch that operates. An AC output control device according to the present invention is an AC output control device that controls an AC output supplied to a load based on waveform data read from an AC waveform memory, and an instantaneous value for detecting an instantaneous value of a voltage supplied to the load. Value detection means, average value detection means for calculating the AC voltage average value by integrating the instantaneous value of the voltage supplied to the load for each specific phase section, the instantaneous value of the voltage and the waveform data from the AC waveform memory First based on the difference between
Of the waveform data from the waveform memory, comparing the average value of the voltage with a predetermined voltage target value and increasing or decreasing the coefficient value according to the magnitude relationship between the two. Second control means for multiplying the amplitude value to form second control data, and an alternating current that is controlled by the first and second control data and that produces a controlled voltage output relative to the voltage target value. And a generating means. Further, the alternating current generating means performs a switching operation by a PWM means for generating a PWM pulse whose duty changes with time according to an amplitude value of the input control data, and an output pulse of the PWM means to convert a direct current input into an alternating current output. And an inverter bridge switch that operates. An AC output control device according to the present invention is an AC output control device that controls an AC output supplied to a load based on waveform data read from an AC waveform memory, and detects an instantaneous value of a voltage and a current supplied to the load. Instantaneous value detecting means, an average value detecting means for calculating the alternating current average value by integrating the instantaneous value of the current supplied to the load for each specific phase section, the average value of the current and a predetermined current target value And an amplitude adjusting means for multiplying the amplitude value of the waveform data from the waveform memory by the coefficient value increased / decreased according to the magnitude relationship between the two, and the instantaneous value of the voltage and the amplitude adjustment from the amplitude adjusting means. Control means for forming control data based on a difference from the waveform data, and alternating current generation means for generating an output controlled by the control data, the current being controlled with respect to the current target value, are provided. And it features. Further, the AC generation means is a PWM for generating a PWM pulse whose duty changes with time in accordance with the amplitude value of the input control data.
Means and an inverter bridge switch that is switched by the output pulse of the PWM means and converts a DC input into an AC output. An AC output control device according to the present invention is an AC output control device that controls an AC output supplied to a load based on waveform data read from an AC waveform memory, and an instantaneous value for detecting an instantaneous value of a voltage supplied to the load. A value detecting means, an average value detecting means for calculating an AC voltage average value by integrating the instantaneous value of the voltage supplied to the load for each specific phase section, and comparing the average value of the voltage with a predetermined voltage target value. Amplitude adjusting means for multiplying the amplitude value of the waveform data from the waveform memory by the coefficient value increased / decreased according to the magnitude relationship between the two, the instantaneous value of the voltage, and the amplitude adjusted waveform data from the amplitude adjusting means. And control means for forming control data based on the difference between the control data and the alternating current generation means for generating an output controlled by the control data with respect to the voltage target value. . Further, the AC generating means is a PW whose duty changes with time in accordance with the amplitude value of the input control data.
It is characterized by comprising PWM means for generating M pulses, and an inverter bridge switch which is switched by an output pulse of the PWM means and converts a DC input into an AC output. The AC output control device according to the present invention,
An AC output control device for controlling an AC output supplied to a load on the basis of waveform data read from an AC waveform memory, wherein an instantaneous value detecting means for detecting an instantaneous value of a voltage and a current supplied to the load and a load Average value detecting means for calculating the AC average value of the current and voltage by integrating the instantaneous values of the voltage and current to be supplied for each specific phase section, and comparing the average value of the voltage with a predetermined voltage target value, Amplitude adjusting means for multiplying the amplitude value of the waveform data from the waveform memory by the coefficient value increased / decreased according to the magnitude relationship between the two and the average value of the current and the predetermined current target value are compared, and the magnitude relationship between the two is determined. Target value adjusting means for increasing / decreasing the voltage target value in response to the control means, and control means for forming control data based on the difference between the instantaneous value of the voltage and the amplitude-adjusted waveform data from the amplitude adjusting means, data More controlled, the voltage, characterized in that it comprises an AC generator for generating an output which is controlled with respect to the voltage target value. Further, the alternating current generating means is switching-operated by a PWM means for generating a PWM pulse whose duty changes with time according to an amplitude value of the input control data, and an output pulse of the PWM means,
And an inverter bridge switch for converting a DC input into an AC output. An AC output control device according to the present invention is an AC output control device that controls an AC output supplied to a load based on waveform data read from an AC waveform memory, and detects an instantaneous value of a voltage and a current supplied to the load. An instantaneous value detecting means, an average value detecting means for accumulating instantaneous values of voltage and current supplied to the load for each specific phase section to calculate an AC average value of the voltage and current, and an average value of the current and a predetermined value. Compare the current target value of
First control data forming means for forming first control data by multiplying the amplitude value of the waveform data from the waveform memory by the coefficient value increased or decreased according to the magnitude relation between the two, and the average value of the voltage and the predetermined value. Second control data forming means for forming the second control data by comparing the amplitude value of the waveform data from the waveform memory with the coefficient value increased / decreased according to the magnitude relationship between the two. And a target value adjusting means for comparing the average value of the current with a predetermined current target value and increasing or decreasing the voltage target value according to the magnitude relation between the two, an instantaneous value of the voltage and the first or second The third control data is formed by adding the other of the control data to one of the control data of
Control data forming means, and alternating current generating means controlled by the third control data to generate outputs whose current and voltage are controlled with respect to the respective target values. Further, the alternating current generating means performs a switching operation by a PWM means for generating a PWM pulse whose duty changes with time according to an amplitude value of the input control data, and an output pulse of the PWM means to convert a direct current input into an alternating current output. And an inverter bridge switch that operates. Further, the third control data forming means is means for forming a difference between the sum of the first and second control data and the instantaneous value of the voltage. Also, the third control data forming means forms a third control data by multiplying the difference between the first control data and the instantaneous value of the voltage by a predetermined gain, and adding the second control data. It is a means to do. Further, the second control data forming means is provided with a limit means for limiting increase / decrease of the coefficient value of the first control data between a predetermined upper limit value and a predetermined lower limit value. Further, the target value adjusting means decreases the voltage target value by a minute value when the average value of the current is larger than the current target value, and the voltage target value when the average value of the current is smaller than the current target value. Is increased by a very small value, and limit means for limiting the output of the calculating means so as not to exceed a predetermined upper limit value and a lower limit value, the upper limit value being the output of the alternating current generating means. It is characterized in that it is set to a constant value such that the rated output voltage is supplied to the load when the voltage matches the voltage target value. In addition, integrating means for integrating the average value of the current or voltage in consideration of the polarity of each AC half cycle to detect the DC component of the AC output, and comparing the output of the integrating means with a predetermined range, the range When it is outside, the DC adjustment data is increased or decreased by a small amount corresponding to the upper and lower parts of the range, and when it is within the range, adjustment means for holding the previous value of the DC adjustment data, and the DC adjustment data for the second control data. Further comprising a DC shift means for adding to the DC correction loop operation so that the DC component of the output of the AC generating unit becomes a value within the range and becomes a substantially negligible amount with respect to the AC component. It is characterized by being performed. Further, by counting the comparison result indicating that the output of the arithmetic means is within the range over a predetermined number of loops, the counting means for detecting the convergence of the correction loop and the convergence detection output of the counting means are closed. Switch means for supplying the output of the alternating current generating means to the load.
The DC shift means for adding the DC adjustment data to the second control data includes a first adding means for adding an upper bit group of the DC adjustment data to the second control data, and the DC adjustment. Memory means for reading fine adjustment data having a number of "1" according to the value represented by the lower bit group, using the lower bit group of the data as an address, and the fine adjustment data for one bit for each DC correction loop. It is characterized by comprising serial shift means for serially shifting each by one, and second adding means for adding the output of "1" of the serial shift means to the output of the first adding means.

[0014]

According to the present invention, an inverter for controlling an AC output supplied to a load is presented based on waveform data read from an AC waveform memory. Instantaneous values of the voltage and current supplied to the load are detected by the instantaneous value detection means and the average value detection means provided at the AC output terminal, and the instantaneous values of the voltage and current supplied to the load are detected for each specific phase section. And the AC average value is calculated. The first control data forming means compares the average value of the current with a predetermined current target value, and multiplies the amplitude value of the waveform data from the waveform memory by a coefficient value amplified according to the magnitude relationship between the two. 1 to form control data. The second control data forming means compares the average value of the voltage with a predetermined voltage target value, and multiplies the amplitude value of the waveform data from the waveform memory by a coefficient value increased or decreased according to the magnitude relationship between the two. Form the second control data. The target value adjusting means compares the average value of the current with a predetermined current target value, and increases or decreases the voltage target value according to the magnitude relationship between the two. The third control data forming means forms the third control data by adding the other of the control data to the difference between the instantaneous value of the voltage and one of the first or second control data. The alternating current generating means is controlled by the third control data and generates an output in which the current and the voltage are controlled with respect to the respective target values. Thereby, in the dual control system using the first and second control data, the target value control independent of the instantaneous value control is performed. In addition, the adjustment of the coefficient applied to the waveform data is a delta method in which a small amount is increased or decreased at a time. Further, an overcurrent limit value is set as the current target value. Also, according to the present invention, the integrating means detects the DC component of the AC output by integrating the average value of the current or voltage in consideration of the polarity of each AC half cycle. The adjusting means compares the output of the integrating means with a predetermined range, minutely increases or decreases the DC adjustment data corresponding to the upper and lower parts of the range when it is out of the range, and outputs the DC adjustment data before it when it is within the range. Holds the value. The DC shift means adds the DC adjustment data to the second control data. As a result, the DC correction loop operation is performed so that the DC component of the output of the AC generating means becomes a value within the range and becomes a substantially negligible amount with respect to the AC component. Further, according to the present invention, the first adding means adds the higher-order bit group of the DC adjustment data to the second control data. Fine adjustment data having a number of "1" corresponding to the value represented by the lower bit group is read from the memory means by using the lower bit group of the DC adjustment data as an address.
The serial shift means serially shifts the fine adjustment data by one bit for each DC correction loop.
Then, the second adding means adds the output of "1" of the serial shifting means to the output of the first adding means.
As a result, data processing is performed with a relatively small number of bits.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

First, the first embodiment will be described.

The AC output control device according to the present invention is applied to, for example, an inverter circuit as shown in FIG.

In this inverter circuit, as shown in FIG. 1, a DC power supply 1 is connected to a capacitor 2 and an inverter bridge 3. Inverter bridge 3
Is a series circuit of switching elements Qx and Qy, and
A series circuit of switching elements Qu and Qv is provided. A terminal 4b between the switching elements Qx and Qy and a terminal 4a between the switching elements Qu and Qv are AC output terminals of the inverter bridge 3 formed by the switching elements Qx and Qy and Qu and Qv. When viewed from the inverter bridge 3, the DC power supply 1 and the capacitor 2 are connected in parallel to the DC voltage input terminals 2a and 2b.

Switching elements Qx, Qy and Qu
And Qv are driven on (conduction) / off (non-conduction) by switching drive circuits 3x and 3y and 3u and 3v, respectively. An ON / OFF instruction signal (low level L indicates ON / high level H indicates OFF) X and Y and U and V addressed to each switching element are output from the power control circuit 16.
It is applied to the switching drive circuits 3x and 3y and 3u and 3v. By setting the on / off instruction signals X and V to the on instruction level L and simultaneously setting the Y and U to the off instruction level H, the switching elements Qx and Qv are turned on (conduction).
Then Qy and Qu are turned off (non-conducting), and the switching output terminal 4b becomes the positive electrode potential (+) of the DC power supply 1.
Then, the switching output terminal 4a becomes the negative electrode potential (-). On the contrary, the on / off instruction signals X and V are turned off to the instruction level H.
At the same time, by setting Y and U to the on instruction level L, the switching elements Qx and Qv are turned off and Qy
And Qu are turned on, and the switching output terminal 4b
Becomes the negative electrode potential (−) of the DC power supply 1, and the switching output terminal 4a becomes the positive electrode potential (+).

An X / V conduction mode in which the on / off instruction signals X and V are set to the on instruction level L and Y and U are set to the off instruction level H, and the on / off instruction signals X and V are set to the off instruction level H and An alternating voltage (pulse) is generated between the switching output terminals 4a / 4b by alternately repeating the Y and U conduction modes in which Y and U are set to the ON instruction level L.

This AC voltage is stepped up by a step-up transformer 6 via a current detecting transformer 5, shaped into a sine wave by a capacitor connected in parallel to a secondary winding of the transformer 6,
It is applied to the capacitors 11 to 13 through the noise removing inductance element (reactor) 10. The capacitors 11 and 12 set a common potential (equipment ground) at the midpoint between the upper and lower peaks of the AC voltage. A load LD is connected in parallel with the noise removal (absorption) capacitor 13.

Reference numerals 14a and 14b are load connection terminals, that is, output terminals of the inverter (DC / AC converter) shown in FIG. A transformer 15 for output voltage detection is connected in parallel with the secondary coil of the step-up transformer 6.

A normally open contact piece of a relay 8r is interposed between the step-up transformer 6 and the reactor 10, and a relay drive circuit 8d energizes the relay 8r. The power control circuit 16 gives the energization instruction signal S1 to the relay drive circuit 8d. When the energization instruction signal S1 becomes low level L, the relay drive circuit 8d energizes the electric coil (not shown) of the relay 8r, and the relay contact is closed. That is, an AC voltage is applied to the load LD connected between the inverter output terminals (load connection terminals) 14a-14b (load energization). When the energization instruction signal S1 becomes high level H, the relay drive circuit 8d cuts off the energization of the electric coil (not shown) of the relay 8r, and the relay contact piece is opened. That is, no voltage is applied to the load LD connected between the inverter output terminals 14a and 14b (load cutoff: no load).

FIG. 2 shows the configuration of the power control circuit 16 shown in FIG. The main body of the power control circuit 16 is an 8-bit microcomputer 22. The current (load current instantaneous value) of the secondary winding of the transformer 5 for detecting the load current is rectified by the rectifying / amplifying circuit 17, noise (high frequency) removed and amplified, and the negative half-wave is inverted into the positive half-wave. Is converted into a voltage representing the pulsating current value and applied to the second A / D conversion input port A / D2 of the computer 22.

The computer 22 has a predetermined sampling period (Ts2 = 6 / 9.6 KHz≈625 μsec),
This voltage (absolute value of the instantaneous value of load current) is digitally converted and read. Hereinafter, this data is referred to as a load current detection value.
Note that this load current detection value is the instantaneous value (but absolute value) of the alternating current output (load current), that is, the output current instantaneous value (but absolute value).

The secondary winding voltage (instantaneous value of the load voltage) of the transformer 15 for detecting the load voltage is a sine wave (50 Hz) that swings in the positive and negative directions about the common potential (ground of the equipment). 18 biases this alternating current by +2.5 V to produce a pulsating current that swings substantially in the positive voltage range. This pulsating flow passes through a filter 19 that removes high frequency noise.
First A / D conversion input port A / D of computer 22
1 is applied. The computer 22 has a predetermined sampling period (Ts1 = 1 / 9.6 KHz≈104.17 μ).
sec), this voltage (instantaneous value of load voltage) is digitally converted and read. Hereinafter, this data is referred to as a load voltage instantaneous value. This instantaneous value of load voltage is the AC voltage output (load voltage)
Note that it is the instantaneous value of (but positively biased).

The oscillator 20 has a frequency f = 7.3728M.
It oscillates at Hz and gives a signal (clock pulse) of this frequency to the computer 22. Reference numeral 21 is a reset switch.

The computer 22 starts a predetermined pulse cycle (Tpwm = 25) from its PWM pulse output terminal "PWM".
The PWM pulse of 5 / f≈34.59 μsec) is output to the pulse inversion circuit 23. The pulse inversion circuit 23 uses this P
The pulse having the same phase as the WM pulse is output to the AND gate AN1, and the pulse having the opposite phase (inverted) is output to the AND gate AN2. AND gates AN1 and AN2 are respectively PW
A pulse having the same phase as the M pulse (hereinafter, a positive phase pulse) and a pulse having a negative phase (hereinafter, a negative phase pulse) are applied to the dead time generation circuit 24.

The dead time generation circuit 24 is synchronized with the positive phase pulse, and its rising from L (Low) to H (High) is delayed by a minute time determined by the values of the resistor R1 and the capacitor C1, and from H to L. The falling edge to generate a positive phase drive pulse with substantially no delay, level inversion is performed via the buffer amplifiers BAu and BAy (inverter), and output to the switching drive circuits 3u and 3y (signal U
And Y). The dead time generation circuit 24 is also synchronized with the negative phase pulse, and its rising edge from L to H is delayed by a minute time determined by the values of the resistor R2 and the capacitor C2, and the falling edge from H to L is substantially delayed. Generates a reverse-phase driving pulse that does not exist, inverts the level through the buffer amplifiers BAv and BAx, and outputs the inverted signals to the switching drive circuits 3v and 3x (signals V and X).

Therefore, within one cycle of the PWM pulse output (Tpwm = 255 / f≈34.59 μsec), the positive phase drive pulse and the negative phase drive pulse are generated during the above-described minute time after the PWM pulse rises to H at the start end. The drive pulses are both L, and all the switching elements (Qu, Qy) and (Qv, Qx) are off. After the lapse of the minute time, the positive phase drive pulse is H and the switching elements (Qu, Qy) are on (4) until the end of the H (High) section (Vpwm) of the PWM pulse.
a becomes + / 4-b, and (Qv, Qx) remains off. Then, the PWM pulse falls to L, the positive phase drive pulse falls to L in the same manner, and the switching elements (Qu, Qy) turn off, but the negative phase drive pulse continues to be L for the minute time. Therefore, all the switching elements (Qu, Qy) and (Qv, Qx) are off during the minute time. Then, after the minute time, the PWM pulse becomes L
Although in the interval, the anti-phase drive pulse rises to H and the switching elements (Qv, Qx) are turned on (4a is − / 4b is +).
To fall. Then, at the end of one cycle of the PWM pulse (beginning of the next cycle), it rises to H, and in synchronism with this, the reverse-phase drive pulse falls to L, and at the next minute time (beginning of the next cycle Of the switching element (Q
u, Qy) and (Qv, Qx) are turned off.

That is, the dead time generation circuit 24 causes the switching elements (Qu, Qy) and (Qv, Qx).
At the time of switching on, all switching element off sections of a minute time are placed. This is a switching element (Q
This is to eliminate the possibility of simultaneous turning on (u, Qy) and (Qv, Qx) (shorting the DC power supply 1).

As described above, one cycle of the PWM pulse (T
In pwm = 255 / f≈34.59 μsec), ignoring the minute time, the explanation will be made. In the H section (Vpwm) of the PWM pulse, the switching elements (Qu, Qy) are turned on and the terminals 4a are +, 4b are −. And the next L section (Tpwm
The switching element (Qv, Qx) becomes conductive at −Vpwm) and the terminal 4a becomes − and 4b becomes +.

That is, one cycle of the PWM pulse (Tpwm
), One cycle of alternating current (pulse) appears at the output terminals 4a / 4b of the switching circuit. When the duty ratio of the PWM pulse is 50% (Vpwm = Tpwm / 2),
As for the secondary winding voltage of the step-up transformer 6, a capacitor is connected in parallel to the secondary winding voltage, and this absorbs (smooths) a high frequency.
The low frequency component (50 Hz) is substantially zero. If the duty ratio of the PWM pulse (the H section) is 50
When the pulse width modulation (PWM) is performed repeatedly, for example, in a cycle corresponding to 50 Hz centering around%, the voltage of the secondary winding voltage of the step-up transformer 6 (capacitor connected in parallel thereto) becomes an AC voltage of 50 Hz. In the first embodiment, the computer 22 performs this pulse width modulation. That is, pulse width modulation (PWM) for outputting an AC voltage of 50 Hz is performed.

In the first embodiment, when the inverter circuit shown in FIG. 1 is turned on, the AC voltage is not output to the load LD immediately, but when the inverter circuit is turned on, the output current is first output. Is detected, and after overcurrent control and DC component correction, the relay 8r is turned on to supply power to the load. Computer 2
The ON command signal (H: relay ON / L: relay OFF) of the relay 8r from the port 1 of 2 is inverted in level via the buffer amplifier (inverter) BA1 (this is the output S1 of the power control circuit 16), and the relay drive circuit. Given to 8d.

Next, referring to FIG. 3, an outline of the constituent elements and operation of the PWM inverter in the first embodiment will be described.

As described above, the power of the DC power supply 1 is converted into the alternating PWM pulse power by the inverter bridge 3, converted into the sine wave AC waveform by the filter 40 including the transformer 6 and the capacitor 7 in FIG. 1, and the relay 8r.
Is supplied to the load LD via. The current and voltage of the AC power supplied to the load are the load current detection transformer 5 of FIG.
Is detected by the output current detector 41 corresponding to the load voltage detecting transformer 15 and the output voltage detector 42 corresponding to the load voltage detecting transformer 15. The detected instantaneous output current and instantaneous output voltage are converted into digital data Jout and Vout by A / D converters 22d and 22e, respectively.

The control function embodied by the program of the microcomputer 22 of FIG. 2 comprises a proportional control unit 22a, an integral control unit 22b and a DC component correction unit 22c, which are generally indicated by broken lines in FIG. The proportional control unit 22a and the integral control unit 22b operate during initialization of the inverter and during power supply to the load, but the DC component detection unit 22c operates only during initialization of the inverter. Each output of the proportional control unit 22a and the integration control unit 22b is amplitude data of a sine wave that determines an AC output, and the addition unit 22g
After being added by, the amplitude data is supplied to the PWM unit 22f that converts the amplitude data into the duty ratio of the PWM pulse. PWM
The part 22f generates a PWM pulse whose duty ratio corresponds to the instantaneous amplitude value of the sine wave and whose duty ratio changes continuously in accordance with the sine change of the amplitude value, and supplies the PWM pulse to the inverter bridge 3.

In the proportional control section 22a, the instantaneous output voltage Vout from the A / D conversion section 22e is subtracted from the first target value V1 in the subtraction section 227 to obtain an error signal V1-Vout for the target value. This error signal is multiplied by the gain G in the gain multiplication unit 228 and then derived to the addition unit 22g. Therefore, the output of the proportional control unit 22a is G * (V1-Vout). The gain G may be 1, for example.

The first target value V1 is stored in the sine wave data memory 225 composed of ROM in the microcomputer 22.
First reference sine wave data Vref1 (asin ωt) read from the (table TSIN1) at a predetermined time axis address
Is formed based on. In the multiplication unit 226, the first reference sine wave data is supplied with a first adjustment coefficient RA for overcurrent control.
AF / 256 (256 is an 8-bit full scale value) is multiplied and given to the subtraction unit 227 as the first target value V1, and the instantaneous output voltage Vout is subtracted as described above to calculate the error signals V1-Vout. .

The first adjustment coefficient RAAF / 256 is A / D
The instantaneous output current value Jout from the conversion unit 22d is given to the integrating and averaging unit 221 to calculate the AC current average value Jav, and the average value Jav and the overcurrent setting value Jref stored in the overcurrent storage unit 222 in the ROM are calculated. Are compared by the comparison unit 223, and the adjustment unit 224 increases or decreases the first adjustment value RAFF by the minute amount ΔAF or holds the previous value according to the comparison results (Jav> Jref, Jav <Jref, Jav = Jref). Therefore, the first target value V1 is instantaneous sine wave data (Vref1 * RAAF / 256) obtained by increasing / decreasing the amplitude of the first reference sine wave data Vref1 by the adjustment coefficient RAAF, and the output AC voltage waveform of the reference sine wave This is control data for making the amplitude follow and feeding back the instantaneous output voltage Vout so that the alternating current average value Jav does not exceed the overcurrent set value Jref. Note that the integration / averaging unit 221 typically integrates the sample amplitude values in each half-wave section of the instantaneous AC current Jout and divides by the number of samples n to calculate the AC average value Jav.

FIG. 4 shows details of the adjusting section 224. Based on the result of comparison between the average current value Jav and the set current value Jref, the calculation unit 224a increases or decreases ± ΔAF with respect to the voltage reference value RAAF. The data of the register 224b holding the adjustment result is given to the limiter unit 224c, and its value is limited so as not to exceed the upper limit value and the lower limit value.

The integration controller 22b forms the second target value V2 based on the average value of the AC voltage. That is, basically, the instantaneous output voltage Vout from the A / D conversion unit 22e is given to the integration and averaging unit 232, and the AC voltage average value S for every half cycle is given.
V is calculated, and the second adjustment coefficient RADR / 256 adjusted according to the average value is read from the sine wave data memory 235 (table TSIN2) configured by the ROM in the microcomputer 22 at a predetermined time axis address. By multiplying the amplitude value of the output second reference sine wave data Vref2 (bsin ωt), the second target value V2 (Vref2 * RAA
F / 256) is formed.

More specifically, in the integration control unit 22b, the AC voltage average value SV from the integration and averaging unit 232 is calculated by the comparison unit 2
At 33, the voltage reference value Sref is compared, and the comparison result (SV
<Sref, SV> Sref, SV = Sref), the adjustment unit 234 increases or decreases the second adjustment value RADR by a small amount ΔDR or holds the previous value to obtain a second adjustment coefficient RADR /
256 is formed. This adjustment coefficient RADR / 256 is multiplied by the second reference sine wave data Vref2 in the multiplication unit 236, and the second target value V2 is output via the DC shift unit 237 (described later).

The output V2 of the integration controller 22b is used as the adder 2
2g and output G * (V1−
Vout). Therefore, the control data given to the PWM unit 22f finally becomes G * (V1-Vout) + V2. If the gain G is 1, the above equation becomes (V1 + V
2) -Vout or (V2-Vout) + V1. From this, the second target value V2 is instantaneous sine wave data obtained by increasing or decreasing the amplitude of the second reference sine wave data Vref2 by the adjustment coefficient RADR, and makes the output AC voltage waveform follow the amplitude of the reference sine wave, The control data is for feeding back the instantaneous output voltage Vout so that the detected AC voltage average value SV matches the voltage reference value Sref.

The voltage reference value Sref is increased or decreased by a small amount ΔSref by the adjustment unit 231 by using the comparison result (output of the comparison unit 223) of the average current value Jav and the set current value Jref in the proportional control unit 22a. Adjusted by holding the value. As shown in detail in the adjusting unit 231, the calculating unit 231a increases or decreases ± ΔSref with respect to the voltage reference value Sref based on the result of comparison between the average current value Jav and the set current value Jref. The data of the register 231b holding the adjustment result is given to the limiter unit 231c,
The value is limited so as not to exceed the upper limit value Smax and the lower limit value Smin. The upper limit value Smax is set to a constant value such that the effective value of the AC output voltage becomes the rated value of 100V.

Therefore, when driving a load below the rated value at which overcurrent does not flow, since Jav <Jref, the voltage reference value Sref is increased toward the upper limit value Smax and stops increasing at the upper limit value. To do. In this state, the voltage reference value Sref and the AC output average value SV are compared as described above, and the adjustment coefficient RADR / 25 adjusted by the comparison result.
6 is multiplied by the second reference sine wave data Vref2, and the second target value V2 is output. Therefore, the output voltage of the inverter is maintained at the rated value of 100V (effective value).

When a load that causes an overcurrent to flow is connected to the output of the inverter, since Jav> Jref, the voltage reference value Sref is reduced, and the AC voltage average value becomes SV> Sref.
Becomes As a result, the second adjustment value RADR is reduced, so that the output voltage of the inverter is lowered by the loop control described above, and the average current value Jav is lowered. This decrease in the average current is caused by the first adjustment value RA in the proportional controller 22a.
It is also executed by reducing FF.

Here, the proportional controller 22a and the integral controller 2
The control of the overcurrent limitation is performed in both 2b because the integral control unit 22b controls the reference voltage Sre during the overcurrent.
If the control to reduce f is not performed, when the proportional control unit 22b performs the feedback control to reduce the voltage Vout in order to reduce the average current Jav at the time of overcurrent, the integral control unit 22b outputs the output voltage Vout rather than the reference voltage Sref. This is because the exact reverse feedback that works to prevent

As described above, the final control data given to the PWM unit 22f is equivalent to (V1 + V2) -Vout or (V2-Vout) + V1. Therefore, the change shown in FIG. 6 or 7 is possible. Is. In FIG. 6, the first target value V1 from the multiplication unit 226 of the proportional control unit 22a and the second target value V2 from the integration control unit 22b are added by the addition unit 22h, and the instantaneous output voltage Vout is subtracted from the addition result. 22
i is subtracted to obtain control data (Modification 1). FIG.
Then, the subtraction unit 22j subtracts the instantaneous output voltage Vout from the second target value V2 from the integration control unit 22b, and the subtraction result and the first target value V1 from the multiplication unit 226 of the proportional control unit 22a are added by the addition unit 22k. The final control data is obtained by adding (Modification 2). Each modification is merely a change in the order of the program steps of the microcomputer 22.

Returning to FIG. 3, the DC component correcting section 22c will be described.

The DC component correction unit 22c operates at the time of initialization of the inverter to form DC component correction data, and thereafter, only DC shift or DC cancellation based on the correction data is performed. This DC component correction data is stored in the DC shift unit 2 provided at the output end of the integration control unit 22b.
37 and is simply added to the second target value V2.

In the DC component correction unit 22c, the proportional control unit 22
The current average value Jav for each AC half cycle obtained by the integration and averaging unit 221 of a is integrated by, for example, five cycles (10 half cycles) in the integration unit 241 with a positive half cycle being positive and a negative half cycle being negative. To do. As a result, the direct current component SJav of the inverter output can be detected from the integrating unit 241.

The DC component SJav is compared with the set target ranges SJavmax and SJavmin in the range comparison unit 242, and the DC component adjustment value RACENTER is determined by the comparison result.
Increase or decrease ± 1 in 3. That is, if the DC component SJav exceeds the target upper limit SJavmax, 1 is subtracted from the DC component SJav.
If Jav is less than or equal to the target lower limit SJavmin, add 1
If it is within the target range, the previous value of the adjustment value is held.

The adjustment value RACENTER is sent to the DC shift unit 237, where the output of the multiplication unit 236 (RADR
/ 256) * Vref2 is added. As a result, the DC component is corrected by ± 1 in the cycle of the control loop, and if it is within the target range, that is, if SJavmax ≧ SJav ≧ SJavmin, the correction loop control is stopped, and the DC component adjustment value RAC at that time is adjusted.
ENTER is retained. After that, only the DC cancellation based on this adjustment value is executed by the DC shift unit 237.

In the range comparison unit 242, SJavmax ≧ SJav
When ≧ SJavmin is detected, the detection result is sent to the n count unit 250, and when it is measured that the correction loop has detected this state n times, for example, 12 times, the determination unit 251
Confirms the convergence of the DC correction loop and closes the output relay switch 8r of the inverter. As a result, the inverter output in which the DC component is canceled is supplied to the load LD.

This data is represented by 16 bits in order to ensure the accuracy of the DC component adjustment value RACENTER. However, since the microcomputer 22 can handle only 8-bit data at a time, it can only perform correction with a resolution equivalent to 8-bit. For this reason, as shown in FIG. 8, in the DC shift unit 237, the coarse adjustment and the fine adjustment are performed time serially by dividing the upper bit and the lower bit of the 16-bit adjustment value.

In FIG. 8, the DC component adjustment value RACENT
The high-order 8-bit data excluding the low-order 3 bits of the register 237a holding the ER is extracted to the register 237b as the rough adjustment data RACENT with an accuracy of ⅛ of the original adjustment value. This data is the second adjustment coefficient RA from the multiplication unit 236 of the integration control unit 22b in the addition unit 237f.
It is added to the second reference sine wave data Vref2 multiplied by DR / 256 every one rotation (one correction operation) of the DC component correction loop. Therefore, the second control data V2 becomes V2 = (RADR / 256) * Vref2 + RACENT.

On the other hand, the lower 3 bits of the DC component adjustment value RACENTER are given to the ROM 237c as an address, and 8 including the same number of "1" as the value 0 to 7 represented by 3 bits.
Bit fine adjustment data RACENTSUB is set in the register 23.
7d is read. For example, when the value of the lower 3 bits is 3, "10010010" is read as fine adjustment data. This fine adjustment data is added to the output of the adder 237f in the adder 237g for each rotation of the DC correction loop by the serial shifter 237e. Therefore, since the addition of +1 is performed three times in the correction loop operation of eight times, the DC component correction is performed with an accuracy of 3/8 on average on the minimum correction unit of the rough adjustment data.

In the above description, the proportional controller 22a is used.
The sine wave data memories 225 and 235 are used in the integration control unit 22b and the integration control unit 22b, but these may be a single memory. That is, a single memory that stores a sine wave with an amplitude of 1 is used, and the sine wave memory 22
5, 235 first and second reference sine wave data Vref1 and Vref
The amplitudes a and b of ref2 are included in the first adjustment value RAAF and the second adjustment value RADR, respectively.

Further, in the above description, the AC sine wave signals of the output current detector 41 and the output voltage detector 42 are processed as they are. As shown in the form of
A bias can be applied to the detected AC sine wave signal to treat it as a single polarity detection signal. In this case, V1-in the subtraction unit 227 in the proportional control unit 22a.
Before executing Vout, it is necessary to add a constant corresponding to the bias amount. For example, V1 + 128.

Further, in the above description, it is possible to store one cycle of the full wave as the sine wave waveform data Vref in the waveform memory, but as shown in the following embodiment, the half wave waveform is stored. Only the data can be stored to save the ROM area for the waveform data. In this case, with respect to the outputs V1 and V2 of the multiplication units 226 and 236,
A process of reversing the polarity between the positive half wave and the negative half wave is performed. When a bias is applied to the processed data, V1 + 128, 128-V1 is added to the output V1 of the multiplication unit 226.
The positive half-wave and the negative half-wave are alternately calculated. Further, also in the DC shift unit 237 of the integration control unit 22b, the shift process operation for correcting the DC component is positive as in V2 = (RADR / 256) * Vref2 + RACENT V2 = RACENT- (RADR / 256) * Vref2. Alternate half-wave and negative half-wave.

In the case of the configuration in which the voltage instantaneous value Vout is subtracted from the second target value V2 as shown in FIG. 7, the first target value V1
The waveform data memory 225, the multiplication unit 226, and the coefficient adjustment unit 224 in the addition path (addition unit 22k) and the proportional control unit 22a may be omitted. That is, in the control unit 22b, Vref2 * RADR / 256- is set so that the output voltage Vout matches the predetermined reference voltage Sref as described above.
Feedback control of Vout is performed. In addition, the reference voltage Sref
Is adjusted by the output of the comparison unit 223 so that the average current Jav does not exceed the overcurrent setting value Jref as described above.
Therefore, the voltage and current are controlled only by the control unit 22b.

FIG. 9 shows an outline of the power control operation of the computer 22 shown in FIG. Hereinafter, the power control operation of the computer 22 will be described with reference to FIG.

(1) Initialization of internal RAM: When the power is turned on, the computer 22 initializes the internal RAM for temporary storage of data (step 1).

(2) Setting initial values in registers: The computer 22 then sets initial values in the required registers of the internal RAM (writing: step 2).

FIG. 9 shows an example of the number of registers and initial values to be written therein.

That is, the register RAF1 is currently in the positive half-wave period [0 to 180 * of the AC output voltage (50 Hz).
(95/96)] or the negative half-wave period (180-180 + 18)
0 * (95/96)] is a flag register for storing data (0: positive half-wave period / 1: negative half-wave period), and the initial value stored in this is 0. In addition, one unit (180 degrees / 9) obtained by dividing one cycle into 192 (= 96 × 2)
6), output voltage control (H section data V of PWM pulse
Iterative calculation cycle (update of pwm) (timer 1 described later)
The execution cycle of the interrupt process IRT1: the update cycle of Vpwm), and the zero-cross points (0, 180 degrees) are included in the start points of the positive half-wave period and the negative half-wave period of the AC output voltage (50 Hz), respectively. .

The register RAF2 has an AC output current (50
Is a flag register for storing data (0: no overcurrent control / 1: overcurrent control) indicating whether or not overcurrent control for suppressing an overcurrent of (Hz) is being performed. The initial value stored in this is 0.

The register RASV is an AC output voltage (50
(Hz) is a voltage integration register for calculating an output voltage integrated value in each half-wave period. The initial value stored in this is 0.

The register RASJ is an AC output current (50
Hz) is an integrating register for calculating an average output current value. The initial value stored in this is 0. The AC output current (5
It is a half of one cycle of 0 Hz), an average value is calculated at the end of this period, and sampling and integration of current values are newly started.

The register RAAF is a register for storing an adjustment value for overcurrent control. 0 to 255 is stored, and a first reference voltage (sine wave) V for generating a reference AC voltage
The output voltage is adjusted by multiplying ref1 (N) by RAAF / 256. RAAF / 256 “RA
"AF" means the data in the register RAAF. The initial value of the register RAAF is 255.

The register RADR has an AC output voltage (50
(Hz) is a register that stores adjustment values for setting values. The output voltage is adjusted by multiplying the second reference voltage (sine wave) Vref2 (N) for generating the reference AC voltage by RADR / 256. “RADR” of RADR / 256 means the data of the register RADR. The initial value of the register RADR is 0.

The register RAN is a phase count register and is a unit (180 degrees /
96) as one unit of the phase count, and when it counts up to 95 (at the end of the half-wave cycle), the value is initialized. The initial value is 0.

The register RAI has an AC output current (50H).
It is a cumulative number register for calculating the output current average value of z). The initial value stored in this is 9. Output current average value sampling and integration interval (register RAI
The AC output current (50
(Hz) 1/2 period of one cycle, and at the end of this period, the average value of AC output current Jav = RASJ / 16 (RAS
J is the data of the integration register RASJ and 16 is the data of the integration number register RAI), and sampling and integration of the current value are newly started.

Here, the initial value of RAI is set to 9 because
In the no-load state, since the load is not connected to the secondary side between the output terminals 4a and 4b, only the step-up transformer and the current detecting transformer 5, that is, only the inductor component is connected, the output AC voltage and the output AC This is because a phase difference of about 90 degrees occurs between the currents, and this phase difference is eliminated and the positive half wave and the negative half wave of the output AC current are distinguished and integrated. The significance of this initial value will be described later in “DC component correction” (step 12).
It will be described in more detail in the section of the content description of.

The register RPWM is a PWM output register that stores data Vpwm that defines the H (high level) width of the PWM pulse to be output. The initial value of the data Vpwm of the register RPWM is 128 (the duty ratio of the PWM pulse is 50%).

The register RASJAV is an integrated value of the direct current component of the output current average value Jav during the 5 cycles of the alternating current output current (50 Hz) (the integrated value of the direct current component included in the sampling value of the output current average value Jav of 10 times). ) Is a direct current component integration register for storing). In order to remove the AC component, the value of Jav in the range of 90 to 270 degrees of the AC output current (50 Hz) is integrated as a positive value, and the value of Jav in the range of 270 to 0 to 90 degrees is integrated as a negative value. AC output current (50Hz) of 5
Accumulated data RASJ of register RASJAV during the cycle
AV represents the average value of the DC component during 5 cycles. The initial value of this register RASJAV is 1000H (H is hexadecimal notation).

The register RAJ is a number-of-integration register for integrating the DC component, and its initial value is 0.

The register RAOK is a count register for storing the number of times the DC component is in the proper value range in the repeated DC component detection, and its initial value is 0.

The register RACENTER is a register for storing the adjustment value for adjusting the DC component, and the initial value is 0.
It is 400H.

The register RACENT is the register RAC
The register stores an integer value of 1/8 of the ENTER data, and the initial value is 80H.

The register RACENTSUB is a register for storing data corresponding to a decimal value of 1/8 of the data in the register RACENTER, and its initial value is 00H.

Various other registers (assigned to internal RAM) and data tables (assigned to internal ROM)
However, they will be clarified in the description of the operation of the computer 22 based on the following flow chart.

(3) Setting of PWM pulse cycle Tpwm: The computer 22 outputs the PWM pulse cycle Tpwm from the output port "PWM" to the pulse inverting circuit 23 = Tpwm =
Write 255 / f≈34.59 μsec into the register Tpwm (step 3). f is the frequency of the clock pulse generated by the oscillator 20. In addition, in this embodiment, the frequency of the AC voltage applied to the load LD is 50 Hz.

(4) Setting of interrupt cycle Ts1 of timer interrupt 1: time limit value Ts1 of timer 1 = 1 / 9.6 KHz≈104.
Write 17 μsec to the register Ts1 (step 4).

(5) Setting of interrupt cycle Ts2 of timer interrupt 2: time limit value Ts2 of timer 2 = 6 / 9.6 KHz≈625
.mu.sec is written in the register Ts2 (step 5).

(6) Permitting timer interrupts: Permit timer 1 interrupt processing and timer 2 interrupt processing in response to timer 1 and timer 2 timeout (step 6). As a result, thereafter, every time the timer 1 times out, the "timer 1 interrupt process" (IRT1) shown in FIGS.
Every time the timer 2 times out, the "timer 2 interrupt process" (IRT2) shown in FIG. 10 is executed. Since the timers 1 and 2 are set with the time limit values Ts1 and Ts2, respectively, the "timer 1 interrupt process" (IR
T1) is executed in Ts1 cycle, and "timer 2 interrupt processing"
(IRT2) is executed in Ts2 cycle.

Since Ts2 = Ts1 × 6, the “timer 2 interrupt process” (IRT2) is executed once for every 6 times of the “timer 1 interrupt process” (IRT1).
The contents of the "timer 1 interrupt process" (IRT1) will be described later with reference to FIGS.
The contents of 2) will be described later with reference to FIG.

(7) Timer start: Set the time limit value Ts1 (data of the register Ts1) to the timer 1 and the time limit value Ts2 (data of the register Ts2) to the timer 2, and start (start time counting) respectively (step 7). ).

(8) PWM pulse output start: The computer 22 sets a high level H to its output port "PWM" and starts an interrupt timer Vpwm for Vpwm (data of register Vpwm) time, PWM interrupt processing "
Is allowed (step 8).

Thereafter, the PWM pulse output is output from the computer 22 by the "PWM interrupt processing" (PW
Interrupt processing for M output). PWM cycle T
pwm is the value set in the register Tpwm in step 3, 2
55 / f≈34.59 μsec. Measurement of Vpwm and Tpwm (time counting) is performed by counting output pulses (frequency f) of the oscillator 20 (clock pulse counting). In this interrupt processing, a timer Vpwm that measures Vpwm is started, a high level H is set to the output port (PWM), and when the timer Vpwm times out, a low level L is set to the output port (PWM), Tpw
A timer (Tpwm-Vpwm) for measuring m-Vpwm is started, and when this timer (Tpwm-Vpwm) times out, a timer Vpwm for measuring Vpwm is started,
High level H is set to the output port (PWM). The same applies hereinafter. In this interrupt process, Vpwm is updated every Ts1 cycle by the data of the register RPWM described later. At this time, Vpwm is Vpwm = RPWM / 255 * T
It is represented by pwm (however, RPWM is the data of register RPWM). For example, when RPWM = 128, the output port "PW
The duty ratio of the pulse output from "M" is almost 50%.
Becomes By this "PWM interrupt process", a PWM pulse is output from the output port "PWM" to the pulse inverting circuit 23.

FIG. 19 shows the PWM pulse. Ts1 ≒
Since 104.17 μsec and Tpwm ≈ 34.59 μsec, and Vpwm is updated in one cycle of Ts, P having the same on (H) width during 3 pulses (3 cycles) or 4 pulses of the PWM pulse.
The WM pulse is output. That is, when the pulse-on (H) width Vpwm is calculated within the time Ts1 and the contents of the register RPWM are rewritten, pulses having a constant PWM cycle and the same on-width are output. As will be described later, in the "timer 1 interrupt process" (IRT1: FIG. 14 to FIG. 18) executed in the Ts1 cycle, various calculations for overcurrent suppression, DC component suppression and output voltage control are performed, and these calculations are performed. Takes a relatively long time. Therefore, Ts1 is the PWM pulse period T
It is set longer than pwm.

(9) Output cutoff to load LD: Simultaneously with the start of PWM pulse output, the computer 22 sets L (low) to its output port 1 (step 9). This L is inverted to H (high) by the buffer amplifier BA1 and given to the relay drive circuit 8d. Relay drive circuit 8d
Responds to this H and deactivates relay 8r (stops energization). The relay contact is open (note that the relay contact is open when the power is off, and the relay contact is substantially open during the process from power on to here).

(10) "Detection of output current A" (step 10): Here, the instantaneous value (absolute value) of the output current (50 Hz) detected by the current detection transformer 5 is read, and the average value Jav is calculated. (Step 10). The contents will be described later with reference to FIG.

(11) "Overcurrent control A" (step 1
1): Here, it is detected whether or not the 0 output current (50 Hz) is within the set range, and when it is out of the set range, the adjustment value is changed so as to be within the range (step 11). The contents will be described later with reference to FIG.

(12) "DC component correction" (step 1
2): Here, the direct current component of the output current (50 Hz) is detected, it is determined whether or not it is within an appropriate value range, and when it is out of the range, the adjustment value is changed so as to be within the range. (Step 12). Step 1 until it is within the appropriate range
Repeat 0 to 12. When the appropriate value range is reached, the next step 1
Proceed to 3. The contents of this "DC component correction" will be described later with reference to FIG.

(13) Start power supply to the load LD: The computer 22 sets H (high) to its output port 1 (step 13). This H is L by the buffer amplifier BA1
It is inverted to (low) and applied to the relay drive circuit 8d. The relay drive circuit 8d responds to this L by the relay 8
Energize r. The relay contact is closed. As a result, the AC output voltage (50 Hz) of the inverter shown in FIG. 1 is applied to the load LD.

(14) "Detection B of output current" (step 14): Here, the processing executed by the computer 22 is
This is the same as the "output current detection A" (step 10).
Therefore, detailed description of the contents is omitted.

(15) "Overcurrent control B" (step 1
5): Here, the processing executed by the computer 22 is the same as the “overcurrent control A” (step 11). Therefore, detailed description of the contents is omitted.

After energizing the relay 8r (while the load is energized)
The computer 22 repeats only "output current detection B" (step 14) and "overcurrent control B" (step 15) in this order until the power is turned off or the reset switch 21 is turned on. Run. When the reset switch 21 is turned on, the computer 22 stops operating, and when the reset switch 21 is turned off again, the operation is restarted from the series of steps 1 described above.

The processing from step 1 to step 12 is the load LD.
Is a preparatory process (pre-processing) for supplying electric power to the device, and steps 10 to 12 are repeated until the output direct current component under no load is suppressed within an appropriate range. When the direct current component is suppressed within the proper range, power supply to the load LD starts (relay 8r on)
However, the subsequent power supply control to the load is performed only by "output current detection B" (step 14) and "overcurrent control B" (step 15).

Referring to FIG. 10, "timer 2 interrupt processing"
The contents of (IRT2) will be described.

In response to the time-out of the timer 2, the computer 22 resets Ts2 (data of the register Ts2) in the timer 2 and restarts the timer 2 (step 21), and the "output current detection" The value 1 indicating the execution requirement is written in the register IRF2 (step 22). Then, the "timer 2 interrupt process" (IRT2) is terminated, and the process returns to the original routine (process immediately before proceeding to this interrupt process).

Referring to FIG. 11, "output current detection A"
The contents of (step 10) will be described.

Here, the computer 22 first checks whether the register IRF2 has 1 (necessary to detect the output current) (step 31). If not 1, register I
Wait for the RF2 data to become 1. That is, it waits for the output current detection (sampling) timing.
When the data in the register IRF2 is 1 or becomes 1, the computer 22 clears the data in the register IRF2 (same as writing 0) (step 32), and the second
Wait for the end of digital conversion of the input voltage (instantaneous value of output current 50 Hz; absolute value) of the A / D conversion input port A / D2 of (33). This digital conversion is started at step 106 (FIG. 16) of “timer 1 interrupt processing” (IRT1: FIG. 14 to FIG. 18) described later (current detection value A /
(D conversion is performed in Ts1 cycle).

Referring again to FIG. 11, after completion of the digital conversion (step 33), the current detection value (data) Jout is written in the register RAJOUT (step 34). That is, the latest current detection value is written in the register RAJOUT.

Next, the sum obtained by adding Jout to the contents is updated and written in the integration register RASJ (step 3).
5). That is, the current detection value Jout read this time is integrated in the register RASJ. Since the integrated value becomes large, 2 bytes are assigned to the register RASJ to represent it.

Next, the data RA of the integration count register RAI
It is checked whether I represents 16 (accumulation of 16 times has been performed) (step 36). If it is not 16, the data RA of the integration count register RAI
Increment I by 1 (step 37) and wait until the data in the register IRF2 becomes 1 (step 3).
1). That is, it waits for the next current value sampling timing. As described above, since the data in the register IRF2 becomes 1 when the "timer 2 interrupt process" (IRT2) is completed, the sampling cycle of the output current is T.
s2, and here, the time lapse of Ts2 is awaited. In this way, when the current value is read and integrated 16 times (total time is 16 × Ts2), the computer 22 calculates the current average value Jav = RASJ / 16 and writes it in the register Jav. (Step 38). And
The data RAI of the integration count register RAI is initialized to 1 (step 39), and the data of the integration register RASJ is set to 0.
(Step 40).

That is, by "detection A of output current" (step 10), 16 times in Ts2 cycle during Ts2 × 16.
The output current detection value Jout is read, and the average value Jav is read.
Is calculated, the current average value Jav (data Jav of the register Jav) is updated in Ts2 × 16 cycles. Every time the current average value is updated, the process proceeds to "overcurrent control A" (11). Therefore, "overcurrent control A" (step 11)
It is executed in 2 × 16 cycles.

The above is the contents of the "output current detection A" (step 10), and this "output current detection A" (step 10) is executed in Ts2 × 16 cycles. It should be noted that "output current detection B" after power supply to the load LD is started
The contents of (step 14) are also the same as the contents of "Detection A of output current" (step 10). That is, the above-mentioned "detection of output current" is executed in Ts2 × 16 cycles both before and after the start of power supply to the load LD.

The contents of the "overcurrent control A" (step 11) will be described with reference to FIG.

Here, the computer 22 has an internal R
The overcurrent set value Jref is read from the OM, the current average value Jav is compared with this overcurrent set value Jref, and Jref = J
It is checked whether av, Jref <Jav, or Jref> Jav (step 41).

If Jref <Jav, the computer 22
Is the value of a register RAAF (this initial value is 255) that stores a first adjustment value RAAF for adjusting the output current value,
The adjustment value is updated to a value smaller by one unit ΔAF (step 45). This update is performed by register RAAF data RAA.
This is synonymous with updating F to data representing the difference obtained by subtracting 1 from the numerical value represented by it (1 decrement of data). Next, it is checked whether the updated value is equal to or lower than the lower limit value (0), and if it is equal to or lower than the lower limit value (0), the value is changed to the lower limit value (0) (step 44, step 4).
5). That is, the lower limit value (0) of the data of the register RAAF is set as the lower limit. Adjustment (reduction) of current value
Is required, the value 1 which means this is set in the register RA
Write to F2 (step 46). The register RAF
The data of 2 is the "timer 1 interrupt process" (IRT
Referenced in 1).

Next, the computer 22 causes the register RAS for storing the second adjustment value RASREF for adjusting the output current value.
The value of REF is updated to a value smaller by one unit ΔSref than the second adjustment value (step 47). This update is done by register R
It is synonymous with updating the data RASREF of ASREF to data representing the difference obtained by subtracting 32 from the numerical value represented by it. Next, it is checked whether the updated value is below the lower limit value (12288), and if it is below the lower limit value (12288), it is changed to the lower limit value (12288) (step 4).
8, step 49). That is, the register RASREF
The lower limit of the lower limit value (12288) for the data is.
This lower limit value corresponds to the area of the hatched area shown in FIG. That is, the lower limit value (12288) is the area enclosed by the central axis value (128) of the sine wave and the phase axis (128 × 96) within the half cycle range.
It is.

The current average value Jav is compared with the overcurrent set value Jref (step 41). When Jref> Jav, the computer 22 stores the first adjustment value RAAF for adjusting the output current value in the register RAAF. Is updated to a value that is larger than the first adjustment value by one unit ΔAF (step 5).
0). This update is performed by the data RAAF in the register RAAF.
Is updated to data representing a sum obtained by adding 1 to the numerical value represented by the value (1 increment of data). Next, it is checked whether the updated value exceeds the upper limit value (255). If the updated value exceeds the upper limit value (255), the value is changed to the upper limit value (255) (step 51, step 5).
2). That is, the upper limit of the data of the register RAAF (255) is set as the upper limit. When the upper limit is exceeded, the current value cannot be adjusted (increased), so 0 is written in the register RAF2, which means that the current value does not need to be adjusted (unadjustable) (step 53). When the upper limit value is not exceeded, 1 indicating the necessity of current value adjustment is set in the register R.
Write to AF2 (step 54). Computer 2
2 updates the value of the register RASREF that stores the second adjustment value RASREF for adjusting the output current value to a value larger by one unit ΔSref than the second adjustment value (step 55). Next, it is checked whether the updated value exceeds the upper limit value (18888). If it exceeds the upper limit value (18888), the value is changed to the upper limit value (18888) (step 56, step 5).
7). That is, the upper limit value (18888) of the data of the register RASREF is the upper limit. This upper limit is
This corresponds to the area of the hatched area shown in FIG. The upper limit (18888) is 108sin (180 ° * N / 96 +) within the half cycle.
128), N = 0 to 95 and the area surrounded by the phase axis is shown (hatched portion). As for this upper limit value, the output voltage of the inverter is the execution value 1
It is a set value for controlling the voltage to be 00V.

The current average value Jav is compared with the overcurrent set value Jref (step 41), and when Jref = Jav, the computer 22 does not change the first adjustment value RAAF and the second adjustment value RASREF. (Maintain the previous value) and write 1 indicating that the current value needs to be adjusted in the register RAF2 (step 42).

The above is the "overcurrent control A" (step 1).
This is the content of 1), and this "overcurrent control A" (step 1
1) is executed in Ts2 × 16 cycles. In addition, load LD
The contents of the "overcurrent control B" (step 15) after the start of the power supply is also the same as the contents of the "overcurrent control A" (step 11). That is, the above-described overcurrent control is performed for Ts2 both before and after the power supply to the load LD is started.
It is executed in × 16 cycles.

The contents of the "DC component correction" (step 12) will be described with reference to FIG.

This "DC component correction" (step 12)
Only before the start of the power supply to the load LD, the cycle Ts2 × 16
= 625 × 16 = 10000 μsec (1/2 of the cycle of 20000 μsec of the output AC voltage of 50 Hz).
5000 μse because the initial value of RAI is 9 only when the generation of the output AC voltage of 0 Hz is started (step 8 in FIG. 9).
When “c” has elapsed (at the time when the phase of the first wave of the AC voltage is 90 degrees), the first “DC component correction” (step 12) is executed, and then Ts2 × 16 = 10000 μsec. Please be careful.

It has been described above that the first "DC component correction" (step 12) is executed when Ts2 × 8 = 5000 μsec, which is a half of the normal cycle, elapses only when the generation of the output AC voltage of 50 Hz starts. This is the output terminal 4a, 4 in the unloaded state
Between b, only the step-up transformer and the current detection transformer 5, which are not connected to the load on the secondary side, are connected, that is, only the inductor component. Therefore, between the output AC voltage and the output AC current, about 90 Therefore, in order to perform the DC component correction processing by distinguishing between the positive half-wave and the negative half-wave of the output AC current as described later, the “DC component correction” (step 12) is started. 9 points from the 50Hz output voltage waveform
Since it must be delayed by 0 degrees, the initial value of RAI is 9
This is because the execution of the first “DC component correction” (step 12) is shifted by 90 degrees (5000 μsec).

In the "DC component correction" (step 12), the computer 22 first increments the data RAJ (initial value is 0) of the integration number register RAJ by 1 (step 61), and whether the value is an even number. Is checked (step 62), and if it is even, the data Jav of the register Jav
Is added to the data RASJAV of the integration register RASJAV to update and write it in the integration register RASJAV (step 63). 2 bytes are allocated to the data RASJAV. Data RA of integrated count register RAJ
When J is an odd number, the data Jav of the register Jav
The difference obtained by subtracting from the data RASJAV of the integration register RASJAV is updated and written in the integration register RASJAV (step 64). And the accumulated number register RAJ
It is checked whether the data RAJ of 10 has become 10 (integration of 10 times is completed) (step 65), 10
If it has not reached, then "DC correction" (Step 1
2) is ended, and "output current detection A" (step 10)
Proceed to.

When the data of the integration count register RAJ indicates 10, the phase of the first wave 270 degrees to the phase 90 of the second wave of the 50 Hz AC voltage output (no load).
Average value (Jav) of the rectified value (absolute value) of the output current
1) is added to the register RASJAV with a- (minus) value, and the average value (Jav2) of the output current from the phase 90 degrees to 270 degrees of the second wave is added to the register RASJAV with a + value to obtain the value of the second wave. The average value (Jav3) of the output current from the phase 270 degrees to the phase 90 degree of the second wave is-(minus)
The value is added to the register RASJAV, and the same is done for the following items: Jav4, Jav5, Jav6, Jav7, Jav8, Jav9
And, the average value (Jav10) of the output current from the 90th phase to the 270th phase of the fifth wave is a positive value, and the register RASJAV
Will be added to.

However, the first "DC component correction" immediately after start-up
In (Step 12), since the initial value of the register RAI is set to 9 in order to match the phase of the current, the integrated data (Jav1) when the data of RAJ is 1 is the 50 Hz AC voltage output (no load), It is the average value of the rectified value (absolute value) of the output current between the phases of two waves of 0 to 90 degrees.

When the DC component is present, the value represented by the data in the register RASJAV indicating that the DC component has a positive level (the polarity that raises the positive half-wave peak of the first wave) is large. The value represented by the data in the register RASJAV has a small positive value (because the initial value of the register RASJAV is 1000H).

The computer 22 uses the integration count register R
When the data RAJ of AJ becomes 10, it is detected in step 65 and the integrated number register RAJ is cleared (step 66). And DC component (register R
The data RASJAV of ASJAV is set range (appropriate value range), that is, SJAVMAX (register SJAVM).
It is checked whether the data is AX data, which is a fixed value representing 100 AH) or less, and SJAVMIN (data of register SJAVMIN, which is a fixed value representing 0FFH) or more. That is, SJAVMAX ≧ RASJAV
It is checked whether ≧ SJAVMIN (step 6)
7, step 69). When RASJAV (DC component) is outside of this setting range (DC component is 50Hz
When the positive half-wave peak of the AC no-load output current is high), the DC component adjustment value RACENTER (data of the register RACENTER) is decremented by 1 (step 68), and when it is off to the lower side. (DC component is 5
When the positive half-wave peak of the 0 Hz AC unloaded output current is low), the DC component adjustment value RACENTER is incremented by 1 (step 70).

Thus, the DC component adjustment value RACENTER
When is changed, 0 indicating that the adjustment is being performed is written in the register RAOK (step 71), and the integration register RASJAV is initialized. That is, the accumulation register R
Write an initial value of 1000H to ASJAV (step 7
4). The computer 22 then proceeds to the register RACENT.
The lower 3 bits representing the numerical value i (i = 0 to 7) of the 2-byte data RACENTER of the ER (data structure is shown in FIG. 22) are extracted (step 75), and the numerical value i (i = i) 8-bit data (shown in FIG. 23) corresponding to 0 to 7) is read from the internal ROM and written in the register RACENTSUB (step 76). That is,
RA with the lower 3 bits of RACENTER as relative value i
The ROM data at the address CENTSUB0 + i is read and this data is stored in RACENTSUB. From ROMENTSUB0 to ROM, 0/8, 1/8, ..., 7/8
The data containing 1 at the ratio of is stored in advance. Therefore, when the extracted 3 bits represent i = 0, "00000000" (in relation to the processing described later,
(Meaning fraction 0/8) is set to "1" when i = 1.
0000000 "(meaning a fraction ⅛), i = 2
Is 10001000 (meaning fractional 2/8), and i = 3 is 1001001.
0 "(meaning fractional 3/8), and when i = 4," 10101010 "(meaning fractional 4/8),
When i = 5, "11011010" (fraction 5 /
(Meaning 8) is added to “11101 when i = 6.
110 "(meaning a fraction of 6/8) is" 11111110 "(meaning a fraction of 7/8) when i = 7.
To the register RACENTSUB (step 7
6).

Next, the computer 22 sends the register RA
2-byte data RACENTER of CENTER
8-bit data from the lower 4 bits to 11 bits (an integer value of data representing 1/8 of data RACENTER) is extracted (that is, divided by 1/8) and written in the register RACENT (step 78). ). Roughly speaking, the processing of steps 75 to 78 described above is performed by the register R
Divide to obtain 1/8 of the data RACENTER of ACENTER, write the obtained integer in the register RACENT, and write the data corresponding to the fraction to the register RACENTS.
It means to write in UB.

Step 65 and steps 66 to 78 described above
When the process of (1) is executed, "output current detection A" (step 10) is executed again, "overcurrent control A" (step 11) is executed, and "DC component correction" (step 1) is executed again.
Perform 2). As already explained, each of these three sets of processing has a cycle of Ts2 × 16≈10000 μsec,
This process is repeated in this order, but will be described later in "Timer 1 interrupt process" (IR
T1) is repeated in a short cycle of Ts1≈104.17 μsec, and the adjustment value (RAA) set in “Overcurrent control A” (step 11) is set in this “timer 1 interrupt process” (IRT1).
F, RASREF) and "DC component correction" (step 1
Adjustment value (RACENT, RACENTS) set in 2)
UB), the H width Vpwm of the PWM pulse is determined,
The PWM of this set Vpwm by the above-mentioned PWM interrupt processing
Since the pulse is generated and output to the pulse inversion circuit 23,
As described above, by changing the adjustment value (RACENT, RACENTSUB) in the “DC component correction” (step 12), the value of the 50 Hz no-load AC output current changes,
By repeating the “DC component correction” (step 12), the DC component RASJAV can be adjusted to an appropriate value range (SJAVMAX or less, S
Change to JAVMIN or above).

When the value is within the appropriate range, that is, SJAVMA
When X ≧ RASJAV ≧ SJAVMIN, the computer 22 goes through the steps 67 and 69 of FIG. 13 and stores the data in the register RAOK (this initial value is 0 and is 0 when it is out of the appropriate value range). RA
The OK is incremented by 1 (step 72). Then check if RAOK has reached 12. That is, in 12 consecutive “DC component corrections” (step 12),
Appropriate value range SJAVMAX ≧ RASJAV ≧ SJAVMI
Check if it was N. If that is the case (YES), then the computer 22 sets the load LD to 50 Hz.
An AC output voltage is applied (step 13 in FIG. 9). This completes the "DC component correction" (step 12), and thereafter, the "DC component correction" (step 12) is executed unless reset by the reset switch 21 and the power is continuously turned on. Instead, only the “output current detection B” (step 14) and the “overcurrent control B” (step 15) are repeatedly executed in this order at Ts2 × 16 cycles. During this period, the above-mentioned "timer 2 interrupt process" (IRT2) and "timer 1 interrupt process" (IRT
1) is repeatedly executed in the Ts2 cycle and the Ts1 cycle, respectively. The contents of the “output current detection B” (step 14) and the “overcurrent control B” (step 15) are the same as the above-mentioned “output current detection A” (step 10) and “overcurrent control A” (step 11), respectively. Since it is the same as the content of, the description will be omitted.

Next, the "timer 1" shown in FIGS.
The contents of "interrupt processing" (IRT1) will be described.

First, as shown in FIG. 14, when proceeding to this "timer 1 interrupt process" (IRT1), the computer 22 first restarts the timer 1 (step 81). That is, the data Ts1 of the register Ts1 is set in the timer 1 and the time counting is started. This is the next "Timer 1"
This is to determine the execution start timing of the "interrupt processing" (IRT1). When the timer 1 times out, this "timer 1 interrupt process" (IRT1) is executed and the timer 1 is restarted (step 81). Therefore, "timer 1 interrupt process"
(IRT1) is repeatedly executed in the Ts1 cycle.

The process of calculating the second sine wave level data V2 will be described. First, when the timer 1 is restarted, the computer 22 causes the first A / D conversion input port A /
Voltage of D1 (Instantaneous value of 50Hz AC output voltage:
Digital conversion of the positive bias by the bias circuit 18, that is, A / D1 conversion is started (step 8).
2). Then, the data N (0 to 95;
In the following, it may be represented by RAN) (step 83) and the address N of the table TSIN2 is read.
The data Vref2 of is read (step 84). The table TSIN2 is assigned to one area of the internal ROM of the computer 22, and the level data Vref2 () of each point (phase) obtained by dividing the half cycle of the second reference sine wave into 96 is assigned to each of the addresses N = 0 to 95. N) = 123sin (180 ° * N / 96), N = 0 to 95 are stored. This data is shown schematically in FIG. For example, the address 0 of the table is the data (0) of the phase 0 °, the address 48 is the upper peak data of the phase 90 ° (123), and the address 95 is the phase 1 data.
Data of 80 ° * 95/96 is stored. In the data reading of step 84, this data Vref2 (N) =
123sin (180 ° * N / 96), N is the data of register RAN,
Is read.

The computer 22 then proceeds to register RAD.
Corrected second sine wave data VA that has been corrected for voltage adjustment based on R data RADR (output voltage adjustment value)
2. VA2 = Vref2 (N) * (RADR / 256), where N is the data of the register RAN is calculated (step 85). That is, the level data of the table TSN2 is RA
DR / 256 is multiplied to change the amplitude of the sine wave VA2. The relationship between VA2 and Vref2 (N) is shown in FIG. The data RADR of the register RADR is processed later (see FIG. 1).
8 is set in steps 112 to 115), and roughly speaking, the adjustment value RASR for suppressing the overcurrent is set.
It is an adjustment value for suppressing overcurrent and for setting the 50 Hz AC output voltage within the set range based on EF (data of the register RASREF) and the voltage integral value of the half-wave section of the 50 Hz AC output voltage. Details of this will be described later with reference to FIGS. 18 and 19.

The computer 22 next has a current time of 50H.
It is checked whether the AC output voltage is in the positive half-wave section or the negative half-wave section (step 86). Step 11 of FIG. 17 described later
0 and steps 117 to 119 of FIG. 18 described later.
Then, switching between the positive half-wave section / negative half-wave section is detected, and data representing the switched section (0: positive half-wave section / 1: negative half-wave section) is written to the register RAF1. In the check at step 86, the data RAF1 of this register RAF1 is
Is checked to determine whether it is a positive half-wave section or a negative half-wave section. If it is a positive half-wave section, V2 = VA2 + RACENT is calculated, and if it is a negative half-wave section, V2 = RACENT-VA2 is calculated (steps 87 and 88). That is, as shown in FIG. 26, the level data of the table TSIN2 is RA
The central axis of the sine wave VA2 obtained by multiplying DR / 256 is R
The level data of the second sine wave V2 converted into ACENT is calculated. RACENT is data of the register RACENT and is an integer value of the adjustment value for setting the DC component as the setting range (steps 66 to 78 in FIG. 13 described above).

The computer 22 then outputs data RACENT corresponding to the fraction of the adjustment value for setting the DC component as the setting range.
SUB (8 bits: one of the 8 groups in FIG. 23. However, the data at each digit position is circularly shifted to the left by the circular shift described later) is stored in the register RACENTSU.
It is read from B (step 89), and when the least significant digit bit is 1, V2 is updated to a value larger by 1 (step 9).
0, 91). When it is 0, this change of V2 is not performed. Then, the data in the register RACENTSUB is cyclically shifted by one bit from the lower digit to the upper digit (step 92). This shift process is schematically shown in FIG.
FIG. That is, the contents of each bit are the upper bits (left)
Shift to The most significant bit content (b7) is moved to the least significant bit (b0).

The computer 22 then writes the calculated data V2 in the register RAV2 (step 93). For example, R extracted in step 75 of FIG. 13 described above
The lower 3 bits of ACENTER are the numerical value 3 (RACENT
For the integer value represented by means a fraction of 3/8)
Then, after storing "10010010" in RACENTSUB in step 76 of FIG. 13, in the first "timer 1 interrupt process" (IRT1), RACENT
Since the least significant bit of SUB is 0, V2 correction (step 91) is not executed in steps 90 to 92 in FIG. 14, but 1 in RACENTSUB in step 92.
Since the bit cyclic shift is performed, RACENTSUB
Becomes "00100101", and since the least significant bit of RACENTSUB is 1 in the second "timer 1 interrupt process" (IRT1), steps 90 to 90 in FIG.
At 92, V2 correction (step 91) is executed,
At step 92, RACENTSUB is subjected to a 1-bit cyclic shift. In this way, when the lower 3 bits of RACENTER extracted in step 75 of FIG. 13 represent the numerical value 3, "timer 1 interrupt process" (I
During execution of RT1) repeated 8 times, steps 87, 88
Change to increase V2 calculated by 1 by 1 (step 91)
Is only executed 3 times. That is, it is executed with a probability of 3/8. That is, R extracted in step 75 of FIG.
If the lower 3 bits of ACENTER is a numerical value i (= 0 to 7), the probability of executing the change of V2 in step 91 is
It becomes i / 8, and when viewed in time series (statistically viewed), RACENTE extracted in step 75 of FIG.
This means that V2 is changed by a value (fractional value) obtained by dividing the numerical value i represented by the lower 3 bits of R by 8. The data V2 obtained by the above calculation is schematically shown in FIG.

The calculation process of the level data V1 of the first sine wave will be described with reference to FIG.

V2 is calculated as described above and the register RAV is calculated.
2 (93 in FIG. 14), the computer 22
The data N of the register RAN is read (step 9
4), data Vre of address N in table TSIN1
f1 is read (step 95). Here table TSI
N1 is assigned to one area of the internal ROM of the computer 22, and the first address is assigned to each of the addresses N = 0 to 95.
Level data Vref1 (N) = 120sin (180 ° * N / 96), N = 0 to 95 at each point (phase) obtained by dividing the half cycle of the reference sine wave into 96 are stored. This data is shown schematically in FIG. In the data read of step 95, this data Vre
f1 (N) = 120sin (180 ° * N / 96), N is register RAN
The data of is read. For example, at address 0 of the table, data of phase 0 ° (0), at address 48, upper peak value data of phase 90 ° (123), and at address 95 of phase 180 ° * 95/96. The data is stored.

Computer 22 then proceeds to register RAF
The necessity of overcurrent control is checked with reference to the data of No. 2 (step 96). As described above, when the first adjustment value RAAF for overcurrent control (data of the register RAAF) is not the upper limit value (255), 1 indicating that overcurrent control is necessary is written in the register RAF2 (FIG. 1).
2). When the data of the register RAF2 is 1, the value VA1 obtained by correcting the level data Vref1 (N) of the first sine wave using this first adjustment value RAAF, VA1 = Vref1 (N) * (RAAF / 256) calculate. That is, during overcurrent control operation (RAF2 = 1)
To the level data of table TSIN1 in RAAF /
It is multiplied by 256 to change the amplitude of the sine wave VA1. When the data in the register RAF2 is 0 (when RAAF = 255), VA1 = Vref1 (N) is set (steps 97, 98). In FIG. 29, Vref1
The relationship between (N) and VA1 is schematically shown.

Next, according to the data in the register RAF1, the present time is the positive half-wave section (RAF1 = 0) or the negative half-wave section (RA
Whether F1 = 1) is checked (99), and V1 = VA1 + 128 (80H) is calculated in the positive half-wave section, and V1 = 128 (80H) −VA1 is calculated in the negative half-wave section ((1)) ( Steps 100, 101). 128 (8
0H) is the central axis value. That is, the level data of the first sine wave V1 in which the central axis of the sine wave VA2 obtained by multiplying the level data of the table TSIN1 by RAAF / 256 is converted to 128 (80H) is calculated. The sine wave represented by V1 is schematically shown in FIG.

Referring to FIG. 16, H width V of PWM pulse
The calculation process of pwm will be described.

Computer 22 then proceeds to register RAV
The data Vout of OUT is read and the AC output voltage Vout
H width G * (V1-
Vout) is calculated (step 101). In this first embodiment, G = 1. Note that the above-mentioned step 82 (see FIG.
In 4), read the AC output voltage Vout (instantaneous value) (A /
D1 conversion) is started, and steps 104 and 1 to be described later are started.
05 (FIG. 16), the digital data Vout obtained by this A / D1 conversion is stored in the register RAVOUT, and this processing is performed inside the "timer 1 interrupt processing" (IRT1) (reading at the Ts1 cycle). AC output voltage (instantaneous value) data Vout used in step 101
Is currently being read (A / D1 conversion) (step 8
It is a read value before Ts1 from (starting at 2).

The computer 22 then calculates the calculated G *
V2 is added to (V1-Vout) to obtain the H width V of the PWM pulse
pwm and Vpwm = G * (V1-Vout) + V2 are calculated (step 102). Since G = 1, the above equation is Vpwm = (V1 + V2) -Vout. This calculated data Vpwm is stored in the register RPWM (step 103). Ie register RPWM
The data of is updated to the latest calculated value. By the PWM interrupt processing described above, the following Tpwm-Vpw is maintained at the H level during the time indicated by the data Vpwm of the register RPWM.
While m, the PWM pulse of L level is
Is output to the pulse inverting circuit 23 from the output port “PWM” of the.

Here, the high level H width Vpw of the PWM pulse
The relationship between m and the 50 Hz AC output voltage will be described. In the present embodiment, the calculation formula of Vpwm is G = 1 in order to simplify the calculation in this embodiment, so Vpwm = (V1 + V2)
-Vout. V1 is shown in FIG. 30, V2 is shown in FIG. 26, and the central axis value of V1 is 128 (8
0H), the central axis value of V2 is RACENT, and the position (time) of crossing the central axis of both is the same. That is, V1 and V2 are synchronized. Therefore, (V1 + V
2) is a sine wave (composite wave) synchronized with V1 and V2, and its central axis value is RACENT + 128 (80H). Here, for ease of explanation, RACENT
Assuming that the value of has a value of 128 (80H) which is the initial value as a result of the DC correction, the value of the central axis of (V1 + V2) is 1
It becomes 28 × 2. On the other hand, when the output voltage is 0V, the value obtained by the A / D1 conversion of the computer 22 is Vout = 1 because the output voltage is positively biased by the bias circuit 18.
28. Therefore, Vpwm = (V1 +
V2) -Vout is 128, which is the central axis value. The voltage level at the start point (0 degree) of the positive half-wave section and the start point (180 degree) of the positive half-wave section is referred to as the positive half-wave section and the low half-wave section as the high-level section and the low-level section, respectively. The H width of the PWM pulse that gives 0 is Tpwm / 2 (duty ratio 50%). This is H of PWM pulse
In the width section, the switching elements Qy and Qu are turned on, the switching circuit output terminal 4a becomes + potential, and 4b becomes −potential, and the switching element Qx, in the L width section of the PWM pulse.
When Qv is on, the switching circuit output terminal 4a has a − potential, 4b has a + potential, and the duty ratio of the PWM pulse is 50%, both terminals 4a and 4b have a 0 potential (output voltage 0) on a time series average. Because it will be. This PW
When the H width of the M pulse is expanded from the duty ratio of 50% (when the duty ratio is increased), the output terminal 4a becomes + potential and 4b becomes −potential in time series average.
The voltage between a / 4b (positive voltage) increases. When the H width of the PWM pulse is narrowed from the duty ratio of 50% (when the duty ratio is decreased), the output terminal 4a becomes −potential and 4b becomes + potential, and the terminals 4a / 4b are in a time series average. The absolute value of the voltage (negative voltage) increases.

The above description is a simplified one. In practice, in the dead time generation circuit 24 (FIG. 2), the switching elements (Qy, Qu) and (Qx, Qv) are turned on simultaneously (DC power supply 1 In order to eliminate the possibility of (short circuit of), dead time (delay time) is given at the time of on-rising, and in addition, correction for adjustment of output DC component (adjustment of RACENT etc.) is added. There is a slight deviation from the simplified description above.

Referring again to FIG. Computer 22
Calculates the H width section Vpwm of the PWM pulse as described above and updates and writes it in the register RPWM (103), and then waits for the end of A / D1 conversion started in step 82 (FIG. 14) (104). ), And the converted data Vout is updated and written in the register RAVOUT (105). here,
The data of the register RAVOUT has been updated to the latest output AC voltage (instantaneous value).

Next, the computer 22 starts the A / D conversion of the input voltage (the instantaneous value of the 50 Hz AC output current) of the second A / D conversion input port A / D2 (step 10).
6). The data Jout obtained by this A / D2 conversion is the "output current detection A" shown in FIG.
It is written in the register RAJOUT in steps 33 and 34 of 0). While the load is energized, the register RAJOU is similarly set in the corresponding step of "Detection B of output current" (step 14).
Written in T. These "output current detection A" (step 10) and "output current detection B" (step 1)
The above-mentioned reading of the data Jout by 4) is the Ts2 cycle, but the A / D conversion of the A / D2 is started (step 10).
6) is the Ts1 cycle. Since Ts2 = 6 × Ts1, only one A / D2 conversion data out of six A / D2 conversions is sampled.

Feedback of the AC output voltage will be described with reference to FIG.

The computer 22 checks from the data of the register RAF1 whether the AC output voltage is the positive half-wave section or the negative half-wave section at the present time (step 107), and if it is the positive half-wave section, the voltage integration register RASV. Then, the latest data Vout (register RAVOUT in step 105)
Accumulated (plus accumulated). That is, Vout is added to the data RASV of the register RASV, and the obtained sum is updated and written in the register RASV (step 108). That is, the voltage integration is performed as in the area S1 indicated by the diagonal line to the right in FIG. In the negative half-wave section, the detected voltage Vout is lower than the central axis value 128, so the detected voltage Vout is inverted with respect to the central axis value 128, and the inverted value is integrated in the voltage integration register RASV. That is, 128+ (128-Vout) = 2 * 12
8-Vout is added to the data RASV of the register RASV, and the obtained sum is updated and written in the register RASV (step 109). This is the area S2 indicated by the vertical line in FIG.
It means that the voltage is integrated.

Next, the computer 22 checks whether it is the end of the half-wave section (step 110). If it is not the end of the half-wave section, the data RAN of the phase count register RAN is incremented by 1 (N is updated to a value larger by 1) (111), and this "timer 1 interrupt process" (IR
T1) ends (returns to the process immediately before proceeding to the timer 1 interrupt process).

When it is at the end of the half-wave section, the computer 22 refers to FIG.
The data SV of the ASV is compared with the data Sref of the register RASREF. In step 116 described later, the register R
Since ASV is cleared, the voltage integration register R is used here.
The data SV of the ASV shows the voltage integrated value (S1 or S2 in FIG. 31) in the half-wave section which is finished this time. Further, the data Sref of the register RASREF is the load LD
Before starting the power supply to the device, "Overcurrent control A" (step 11) in Fig. 9 is performed, and after starting the power supply, "Overcurrent control B".
In (step 15), the register RA is used to adjust the overcurrent.
It is set to SREF (step 4 in FIG. 12).
7-49 / steps 55-57 and FIG. 14).

The upper limit value 18888 of the data Sref of the register RASREF is 1 when the effective value of the 50 Hz AC output voltage is 1.
Set value (fixed value) that determines Vpwm so that it becomes 00V
It is. When overcurrent flows, register RASRE
The data Sref of F is reduced (step 41--
Steps 43 to 48) are increased toward the upper limit value when no overcurrent flows (step 41 to steps 50 to 56 in FIG. 12), and Sref is maintained while a current of the same level as the overcurrent set value Jref is flowing. Change is stopped (Fig. 12
Step 41-Step 42-Return).

In step 112 of FIG. 18, the voltage integrated value SV in the half-wave section is compared with the above-mentioned overcurrent suppressing data Sref. When SV = Sref, SV and Sref are compared.
Adjustment value RADR (register R
Data stored in ADR) is not changed (step 11)
3). When SV> Sref, the output voltage is too high, so the adjustment value RADR is changed to be smaller by the minimum adjustment unit ΔDR. That is, the data in the register RADR is decremented by 1 (step 114). When SV <Sref, the output voltage is low, and therefore the adjustment value RADR is greatly changed by the minimum adjustment unit ΔDR. That is, the register RAD
The R data is incremented by 1 (step 11
5). The adjustment value RADR (data stored in the register RADR) is stored in the correction level VA2 (V2 based on the correction level VA2) in step 85 of FIG. 14 as described above.
Is calculated).

Next, the computer 22 clears the phase count register RAN and the voltage integration register RASV (step 116) since the end of the half-wave section at this time, and the previous half-wave section ( It is checked whether it is RAF1 = 0) or a negative half-wave section (RAF = 1) (step 117). If it is a positive half-wave section (RAF1 = 0), this time it is a negative half-wave section. Register R
When the data is written in AF1, and the negative half-wave section (RAF = 1) is the positive half-wave section this time, 0 representing this is registered in the register R.
Write to AF1 (steps 118 and 119). And
The current "timer 1 interrupt process" (IRT1) is terminated (returns to the process immediately before proceeding to the current timer 1 interrupt process).

The above is the "timer 1 interrupt processing" (IRT).
This is the content of 1), and this is Ts1 = 1/1 / as described above.
Repeated at 9.6 KHz ≈ 104.17 μsec.

Next, the characteristic points in the above-described first embodiment will be described.

(1) No load processing: As described above, Tpwm = 255 from the start of PWM pulse output (step 8 in FIG. 9) to the start of power supply to the load LD (step 13 in FIG. 9). A PWM pulse having a period of /f≈34.59 μsec is continuously output from the computer 22 to the pulse inverting circuit 23. The frequency of the AC output voltage of the inverter is 50 Hz, and the cycle T50 is T50 = 1 sec / 50 = 20,000 μsec. The "timer 1 interrupt process" (IRT1: Fig. 14 to Fig. 18) is repeated at a cycle of Ts1 = 1 / 9.6 KHz ≈ 104.17 µsec. In this "timer 1 interrupt process", the AC output voltage ( Instantaneous value) First A for reading Vout
A / D conversion A / D1 is performed and the data Vout is stored in the register RAVOUT (step 8 in FIG. 14).
2, step 105 in FIG. 16. That is, the sampling of the AC output voltage (instantaneous value) Vout is performed in the Ts1 cycle.

In the "timer 1 interrupt process", the second A / D conversion A for reading the AC output current (instantaneous value) Jout
/ D2 is performed. However, this conversion data Jout is written to the register RAJOUT in step 34 (FIG. 5) of "output current detection A" (step 10), and "output current detection A" (step 10) is Ts2 cycle. The sampling of the AC output current (instantaneous value) Jout is substantially Ts2 cycles.

"Timer 2 interrupt processing" (IRT2: FIG. 1
0) is repeated at a cycle of Ts2 = 6 / 9.6 KHz≈625 μsec, and the timer 2 interrupt process ends (IRF2 = 0 → I) at “output current detection A” (step 10).
Wait for RF2 = 1), then AC output current (instantaneous value) Jout
Is performed (the A / D2 converted data is stored) and the current average value Jav is calculated. Therefore, the internal calculation process of “output current detection A” (step 10) is repeated in the Ts2 cycle. 16 (times) sampling data J
Until the output is ready, "Output current detection A" (Step 1
0) and 16 (times) sampling data Jou
When t is adjusted and their average value Jav is calculated, one "output current detection A" ends, and in the end, "output current detection A" (step 10) is performed in a cycle of Ts2 × 16. Repeated.

In the "overcurrent control A" (step 11),
Since the process immediately after the execution of the "output current detection A" (step 10), the process is repeated in the cycle of Ts2 × 16.

Similarly, the "DC component correction" (step 12) is repeated in the cycle of Ts2 × 16. By repeating this "DC component correction" (step 12), the adjustment value is adjusted so that the DC component is within the setting range, and when the DC component is within the setting range, the preparation for load energization ( After repeating steps 10 to 12 in FIG. 9), the relay 8r is turned on to energize the load.

(2) Processing during load energization: A PWM pulse having a cycle of Tpwm = 255 / f≈34.59 μsec is continuously output from the computer 22 to the pulse inverting circuit 23. The "timer 1 interrupt process" (IRT1: FIG. 14 to FIG. 18) is repeated at a cycle of Ts1 = 1 / 9.6 KHz≈104.17 μsec. AC output voltage (instantaneous value) Vout
Is sampled in the Ts1 cycle, and the AC output current (instantaneous value) Jout is sampled in the Ts2 cycle.

"Timer 2 interrupt processing" (IRT2: FIG. 1
0) is repeated at a cycle of Ts2 = 6 / 9.6 KHz≈625 μsec, and the same process as the “output current detection A” (step 10) is performed “output current detection B” (step 14), the timer 2 interrupt process ends (I
Waiting for (RF2 = 0 → IRF2 = 1), the process of reading the AC output current (instantaneous value) Jout (storing the A / D2 conversion data) and calculating the current average value Jav is performed. The internal calculation process of (step 14) is repeated in the cycle of Ts2. However, until 16 (times) sampling data Jout are prepared, the output current detection B remains (step 14) and 16 ( Once the sampling data Jout has been prepared and the average value Jav thereof has been calculated, one "output current detection B" ends, and in the end, "output current detection B" (step 14).
Is repeated in a cycle of Ts2 × 16.

"Overcurrent control B" (step 1) which performs the same processing as "overcurrent control A" (step 11)
Since 5) is entered immediately after the execution of the "output current detection B" (step 14), this is also repeated in the cycle of Ts2 × 16.

That is, the load is energized (relay 8r is on).
Performs PWM interrupt processing for PWM pulse output, "timer 1 interrupt processing" (IRT1) and "timer 2 interrupt processing" (IRT2), and "output current detection B"
(Step 14) and "Overcurrent control B" (Step 15)
Are each repeatedly executed with a cycle of Ts2 × 16. Since the "DC component correction" (step 12) is not executed, the adjustment value for DC component correction is the adjustment value immediately before the relay 8r was switched from OFF to ON (adjustment value for DC component adjustment at no load). Staying at "Timer 1 interrupt processing"
In (IRT1), the PWM pulse H width Vpwm is determined based on this adjustment value and the adjustment value determined in the "overcurrent control B" (step 15).

(3) AC output voltage (50 Hz) generation processing 1: In the above-described embodiment, the "timer 1 interrupt processing" (IRT1) is repeated in Ts1 cycle in order to perform the sine wave AC output of a predetermined level. , The register RAN counts the AC output phase (N), samples the AC output voltage (instantaneous value) Vout, and outputs half-cycle sine wave level data Vref1 (N), N = 0 to 95 of the table TSIN1. Vref1 (N) of phase (N) is read, and the read Vref1
The duty ratio (Vpwm / Tpwm) of the output PWM pulse corresponding to the difference between (N) and the detected AC output voltage Vout is determined (FIGS. 15 and 16).

This processing is relatively simple, and a sine wave AC voltage having a predetermined level and high waveform accuracy is generated. Feedback of the AC output voltage Vout has the significance of causing the instantaneous voltage value to follow the target instantaneous value (generating an accurate sine wave).

(4) In the above embodiment, Ts2 ×
"Overcurrent control A" repeated in 16 cycles (step 11)
In "and overcurrent control B" (step 15), the average value Jav of the AC output current is calculated and compared with the overcurrent set value Jref. When the average value Jav is larger than the overcurrent set value Jref, the adjustment value RAAF is set. Adjust to make it smaller, and average value J
When av is smaller than the overcurrent setting value Jref, the adjustment value RA
Adjust the AF to be larger and repeat the cycle of Ts1 in the "timer 1 interrupt process" (IRT1) to read the above V
multiply ref1 (N) by (RAAF / 256) and VA1 =
Vref1 (N) * (RAAF / 256) is obtained and this VA
Output P corresponding to the difference between the detected AC output voltage Vout and 1
The duty ratio (Vpwm / Tpwm) of the WM pulse is determined (FIGS. 15 and 16).

As a result, the average value Jav of the AC output current converges below the overcurrent set value Jref. That is, overcurrent is suppressed.

(5) AC output voltage (50 Hz) generation processing 2: In the above-described embodiment, "timer 1 interrupt processing" (IRT1) is repeated in Ts1 cycle in order to perform sine wave AC output at a predetermined level. Then, the AC output phase (N) is counted by the register RAN, and the AC output voltage (instantaneous value) Vou
Sampling t, reading out Vref2 (N) of the phase (N) of the sine wave level data Vref2 (N), N = 0 to 95 for half cycle of the table TSIN2, and reading Vref2
The duty ratio (Vpwm / Tpwm) of the output PWM pulse corresponding to the difference between the detected AC output voltage Vout and (N) is determined (steps 102 and 103 in FIGS. 14 and 16).

This processing is relatively simple and a sine wave AC voltage having a predetermined level and high waveform accuracy is generated.

(6) In the above embodiment, the integrated value SV of the AC output voltage (data of the register RASV at the half cycle end) is detected by the "timer 1 interrupt processing" (IRT1) repeated in the cycle Ts1. Integral value S for each half cycle of AC output voltage
If V is higher than the reference value Sref (data of the register RASREF), the adjustment value RADR is made smaller, and if the integration value SV is smaller than the reference value Sref, the adjustment value RADR is made larger, and VA2
= Vref2 (N) * (RADR / 256) is calculated, and the duty ratio (Vpwm / Tpwm) of the output PWM pulse corresponding to the difference between this VA2 and the detected AC output voltage Vout is determined (FIG. 14, Steps 102 and 103 in FIG. 16).

As a result, the AC output voltage converges on the reference value. That is, overvoltage or voltage drop is suppressed.
Feedback of the AC output voltage Vout has the significance of causing the instantaneous voltage value to follow the target instantaneous value (generating an accurate sine wave).

(7) AC output voltage (50 Hz) generation processing (1 + 2): In the above embodiment, the AC output voltage (50 Hz) generation processing 1 of (3) and the AC output voltage (5) of 50 Hz) generation processing 2 is combined. That is, in the above embodiment, G = 1 and Vpwm = G * (V1-V
out) + V2 (step 102 in FIG. 16).
That is, Vpwm = (V1 + V2) -Vout V1 = 128 (80H) -VA1 (negative half-wave section), or VA1 + 128 (80H) (positive half-wave section), VA1 = Vref1 (N) * (RAAF / 256) V2 = RACENT-VA2 (negative half-wave section), or VA2 + RACENT (positive half-wave section), VA2 = Vref2 (N) * (RADR / 256), and the effects of (3) to (6) are simultaneously brought about.

(8) Suppression of DC component: In the above embodiment,
In the "DC component correction" (step 12), the DC component integrated value RASJAV (5 cycles of the output AC) of the AC output is detected, and this is set to a setting range (SJAVMAX or less, SJAVM
The adjustment value RACENTER is adjusted so that the value is equal to or less than IN (FIG. 7). The value of the adjustment value RACENTER becomes large, so that it cannot be represented by the reference 1-byte data and is 2-byte data.

To simplify the arithmetic processing, 1/8 of the 2-byte data RACENTER is calculated and stored in the register RACENT. This register RACE
The data RACENT of NT is made to correspond to the central axis level (potential zero level) of the AC output.

In order to simplify the processing, the division to obtain the 1/8 data described above is performed by the 2-byte data RACENTER.
Discard the lower 3 bits of data, and start from the lower 4 bits
This is done by extracting 8-bit data up to 1 bit as RACENT. Therefore, RACE
In NT, fractions generated by dividing 1/8 are discarded.

In order to extract this fraction and reflect it in the DC component suppression, the lower 3 bits of data (0
1 to 7 and 0/8 to 7 after division, respectively
/ 8) into 8-bit data (ROM data contents in FIG. 23) that includes "1" for the number i (0 to 7) represented by "1" and that "1" is distributed at an equal pitch as much as possible. It is converted and stored in the register RACENTSUB. And this fraction adjustment data RACENTSUB
Based on (data of register RACENTSUB),
V2 is calculated eight times ("Timer 1 interrupt processing" (IR
In 8 times of execution of T1), the minimum unit is changed by the number of times of “1” of RACENTSUB.

Thus, the "timer 1 interrupt process" (IR
V8 is changed by i / 8 minutes if the time is averaged over eight execution times of T1) (in time series average). In order to realize this, the data of RACENTSUB is
Each time "Timer 1 interrupt processing" (IRT1) is executed,
It is cyclically shifted by one bit (steps 89 to 89 in FIG. 14).
93, FIG. 18).

When the division is 1 / (2 to the nth power) (n = 3 in the above embodiment), the data extracted as a fraction is the lower n bits of RACENTER,
The numerical value i represented by the n bits is 0 to (2 to the nth power −1).
Therefore, the required number of data bits of RACENTSUB is 2
To the nth power. The larger n is, the finer the amount of correction to V2 for the purpose of DC correction can be changed.
A large number of RACENTSUB data bits is required.
As the data RACENTSUB, the data for the numerical value i represented by the lower n bits of the RACENTER is read from the ROM (step 76 in FIG. 13), and the next timer 1
An arithmetic operation such as cyclically shifting the RACENTSUB data for correction by an interrupt (step 92 in FIG. 14) is performed. In order to simplify such an arithmetic operation and shorten the processing time, it is desirable to match the RACENTSUB data with the standard data length unit of the computer 22 (1 byte = 8 bits in the above embodiment).

(9) In the above-described first embodiment, T
When it is detected that the direct current component is within the set range by continuously executing the "direct current component correction" (step 12) performed 12 times in a cycle of s2x16, the "direct current component correction" ( Step 12) is not executed,
Adjustment value RACENT determined immediately before the execution of the 12 consecutive times
And RACENTSUB are held as they are, and Vpwm is calculated based on them.

(10) "DC correction" (step 12)
Performs in a no-load state, and as described in (9) above, when it is detected that the DC component is within the set range by continuously executing the "DC component correction" (step 12) 12 times in succession, When the load is energized and the load is energized, the continuous 1
Adjustment values RACENT and R defined immediately before the second execution
Hold ACENTSUB as it is and perform "DC component correction"
(Step 12) is not executed, but “Detection B of output current”
(Step 14) and "Overcurrent control B" (Step 1
Only 5) is repeatedly executed in this order in a cycle of Ts2 × 16. During this time, the adjustment values RACENT and RACENT
Adjustment value R for suppressing overcurrent based on SUB
Adjustment value RASR for AAF and overcurrent suppression
EF (Sref) and actual output voltage value RASV (SV)
Vpwm is adjusted based on the adjustment value RADR based on

Therefore, the DC component under no load is suppressed, the overcurrent is suppressed, the output voltage is maintained at a predetermined level (effective value 100V), and the DC component is suppressed and the overcurrent is maintained even while the load is energized. Is suppressed and the output voltage is maintained at a predetermined level (effective value 100V).

Here, “DC component correction” (step 12)
The reason why the operation is performed under no load will be described. In the present embodiment, when there is a DC component, the phenomenon that the balance between the positive half-wave and the negative half-wave of the output AC current flowing between the output terminals 4a / 4b is lost is used to check the balance of the output AC current and The minute is corrected. The imbalance of the output AC current due to the DC component is particularly significant when only the inductor component is connected between the output terminals 4a / 4b. Therefore, when correcting the direct current component, the relay 8r is turned off to put it in a no-load state to create a situation in which only the inductor components (5, 6) are connected between 4a / 4b,
Correction has been performed.

Next, the second embodiment will be described.

The AC output control device according to the present invention is applied to, for example, an inverter circuit as shown in FIG.

In this inverter circuit, the DC power supply 1 is
160V is applied between the DC input terminals 2a / 2b. Switching circuit (Qu, Qy, 3u, 3y / qv, qy, 3
u, 3x) AC output terminals 4a, 4b are connected to a reactor 6
L is connected, and the condenser 7 is connected to the reactor 6L.

In the first embodiment described above, the step-up transformer 6 and the capacitor 7 are an LC low-pass filter circuit for generating a 50 Hz AC, and the step-up transformer 6 converts the DC 48 V into a 50 Hz AC having an effective value of 100 V. Although boosting is performed, in the second embodiment, the reactor 6L and the capacitor 7 are LC low-pass filter circuits for generating 50 Hz AC, but boosting is not performed. Therefore, 160V is used for the DC power supply 1. To obtain 100V AC voltage, the DC voltage may be 141V,
In order to compensate for the voltage drop caused by switching and to cope with load fluctuation, a DC voltage of 160 V is applied between the DC input terminals 2a / 2b.

The inverter circuit according to the second embodiment has the same hardware configuration as that of the above-described inverter circuit according to the first embodiment except for the above-described configurations. Further, the hardware configuration and control operation of the power control circuit 16 in the second embodiment are exactly the same as those of the power control circuit 16 in the first embodiment described above.

Next, a third embodiment will be described.

The AC output control device according to the present invention is applied to, for example, an inverter circuit as shown in FIG.

In this inverter circuit, as shown in FIG. 33, the switching circuit of the inverter circuit in the above-described first and second embodiments is a full bridge, whereas it is a half bridge. Further, in place of the step-up transformer 6 (first embodiment), the reactor 6L is used as in the second embodiment. In the third embodiment, the DC power supply 1P is connected to the DC input terminal 2a by +
160V is applied, and another DC power supply 1N applies -160V to the DC input terminal 2b. DC input terminal 2a / 2
The voltage between the terminals b is 320V, and one of the AC voltage output terminals 4b may be connected to the middle potential terminal (terminal of the DC power supply at the reference potential 0) 2c, and the reactor 6L may be connected thereto. The reactor 6L may be replaced with the step-up transformer 6 and the voltage of each DC power source may be set to 48V. Also in this third embodiment, the reactor 6L and the capacitor 7 are 50
It is an LC low pass filter circuit for Hz alternating current generation. The hardware configuration and control operation of the power control circuit 16 in the third embodiment are exactly the same as those of the power control circuit 16 in the first embodiment.

[0193]

As described above, according to the present invention, an inverter for controlling the AC output supplied to the load based on the waveform data read from the AC waveform memory is presented.
An instantaneous value detecting means for detecting an instantaneous value of a voltage and a current supplied to the load, and an average value detecting means for calculating an AC average value by accumulating the instantaneous values of the voltage and the current supplied to the load for each specific phase section. It is provided at the AC output end. A first control data is formed by comparing an average current value with a predetermined current target value, and multiplying an amplitude value of the waveform data from the waveform memory by a coefficient value increased / decreased according to the magnitude relationship between the two. Of the control data forming means, the average value of the voltage and a predetermined voltage target value are compared, and a coefficient value increased or decreased in accordance with the magnitude relationship between the two is multiplied by the amplitude value of the waveform data from the waveform memory to obtain a first value. The second control data forming means for forming the second control data is compared with the average value of the current and a predetermined current target value,
Target value adjusting means for increasing / decreasing the voltage target value according to the magnitude relation between the two is provided. There is provided third control data forming means for forming third control data by adding the other of the control data to the difference between the instantaneous value of the voltage and one of the first or second control data. The alternating current generating means is controlled by the third control data, and the current and the voltage generate controlled outputs for the respective target values. Therefore, by the dual control system using the first and second control data, high waveform precision and high precision target value control performance can be obtained. The target value control is performed independently of the instantaneous value control. By using the delta method for adjusting the coefficient applied to the waveform data by a small amount at a time, the control system has high control accuracy and good stability. Also, by setting the overcurrent limit value as the current target value, the function of overcurrent protection can be obtained. Further, according to the present invention, there is provided integrating means for integrating the average value of the current or voltage in consideration of the polarity of each AC half cycle to detect the DC component of the AC output. The output of the integrating means is compared with a predetermined range, and when it is out of the range, the DC adjustment data is increased or decreased by a small amount corresponding to the upper and lower parts of the range, and when it is in the range, the previous value of the DC adjustment data is held. By further providing the adjusting means and the DC shift means for adding the DC adjusting data to the second control data, the DC component of the output of the AC generating means becomes a value within the range and substantially the AC component is obtained. The DC correction loop operation is performed so that the amount becomes negligible. Therefore, the direct current component of the output alternating current can be sufficiently suppressed. Further, according to the present invention, the first addition means for adding the upper bit group of the DC adjustment data to the second control data, and the value represented by the lower bit group with the lower bit group of the DC adjustment data as an address. Memory means for reading out the fine adjustment data having a number of "1" according to the above, serial shift means for serially shifting the fine adjustment data one bit at a time for each DC correction loop, and "" for the serial shift means. Second addition means for adding the output of 1 "to the output of the first addition means is provided. Therefore, a high DC component suppressing effect can be obtained by data processing with a relatively small number of bits.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a PWM inverter to which an AC output control device according to the present invention is applied in the first embodiment.

FIG. 2 is a circuit diagram showing a configuration of a power control circuit of the PWM inverter circuit.

FIG. 3 is a block diagram showing a function of a PWM inverter implemented by a microcomputer of the power control circuit and an execution program thereof.

FIG. 4 is a block diagram showing in detail a configuration of an adjusting unit of a proportional control unit in the PWM inverter.

FIG. 5 is a block diagram showing in detail the configuration of an adjusting unit of the integral control unit in the PWM inverter.

FIG. 6 is a principal block diagram showing a first modification of a part of the PWM inverter.

FIG. 7 is a principal block diagram showing a second modification of a part of the PWM inverter.

FIG. 8 is a block diagram showing in detail the configuration of a DC correction shift unit of the PWM inverter.

FIG. 9 is a flowchart showing an outline of control operation of the microcomputer.

FIG. 10 is a flowchart showing the contents of a “timer 2 interrupt process” of the microcomputer.

FIG. 11 is a flowchart showing the content of “output current detection A” processing of the microcomputer.

FIG. 12 is a flowchart showing the contents of “overcurrent control A” processing of the microcomputer.

FIG. 13 “DC component correction” of the above microcomputer
It is a flow chart which shows the contents of processing.

FIG. 14 is a flowchart showing steps 81 to 93 of the content of “timer 1 interrupt processing” of the microcomputer.

FIG. 15 is a flowchart showing steps 94 to 101 of the contents of “timer 1 interrupt processing” of the microcomputer.

FIG. 16 is a flowchart showing steps 101 to 106 of the content of “timer 1 interrupt processing” of the microcomputer.

FIG. 17 is a flowchart showing steps 107 to 111 of the contents of “timer 1 interrupt processing” of the microcomputer.

FIG. 18 is a flowchart showing steps 112 to 119 of the content of “timer 1 interrupt processing” of the microcomputer.

FIG. 19 is a PWM generated by the microcomputer.
It is a time chart which shows a pulse.

FIG. 20 is a waveform diagram showing a relationship between a lower limit value of RASREF (area of a right-downward diagonally shaded region) set by the microcomputer and an AC output voltage level (voltage waveform) in the “overcurrent control A” process.

FIG. 21 is a waveform diagram showing a relationship between an upper limit value of RASREF (area of a right-downward diagonally shaded region) set by the microcomputer and an AC output voltage level (voltage waveform) in the “overcurrent control A” process.

FIG. 22 is a data configuration diagram showing a bit configuration of data RACENTER set by the microcomputer in the “DC component correction” process.

FIG. 23 is data RACENTSUB (8 sets) set by the microcomputer in the “DC component correction” process.
It is a data configuration diagram showing the data of.

FIG. 24 is a waveform diagram showing a voltage waveform represented by sine wave level data Vref2 (N) read from the internal ROM by the microcomputer in the “timer 1 interrupt process”.

FIG. 25: Adjustment value R for overcurrent control and voltage control
Data VA2 in which Vref2 (N) is corrected based on ADR
It is a wave form diagram which shows the voltage waveform represented by.

FIG. 26 is a waveform diagram showing a voltage waveform represented by an adjustment value RACENT for DC component correction and data V2 generated based on the data VA2.

FIG. 27 is a data configuration diagram showing a cyclic shift of the adjustment data RACENTSUB in the “timer 1 interrupt process”.

FIG. 28 is a waveform diagram showing a voltage waveform represented by sine wave level data Vref1 (N) read from the internal ROM by the microcomputer in the “timer 1 interrupt process”.

FIG. 29 is a waveform diagram showing a voltage waveform represented by data VA1 in which Vref1 (N) is corrected based on an adjustment value RAAF for overcurrent control.

FIG. 30 is a waveform diagram showing a voltage waveform represented by an adjustment value RACENT for DC component correction and data V1 generated based on the data VA1.

FIG. 31 shows the integrated value of the detection value of the output AC voltage calculated by the microcomputer in the “timer 1 interrupt process” in the shaded area (positive half-wave section) and the vertical line area (negative half-wave section). It is a waveform diagram.

FIG. 32 is a circuit diagram showing a configuration of a PWM inverter to which the AC output control device according to the present invention is applied in the second embodiment.

FIG. 33 is a circuit diagram showing a configuration of a PWM inverter to which the AC output control device according to the present invention is applied in the third embodiment.

[Description of symbols] 1 DC power supply 3 Inverter bridge 8r Relay switch 22a Proportional control unit 22b Integral control unit 22c DC component correction unit 22d, 22e A / D converter 22f PWM unit 22g Adder unit 40 Filter 41 Output current detector 42 Output Voltage detector 225, 235 Sine wave data memory 232 Integrated averaging unit LD load

Front page continuation (72) Inventor Sadaharu Tamoto 228 Kayajuku, Nakahara-ku, Kawasaki City Yutaka Electric Co., Ltd.

Claims (14)

[Claims] 1. An AC output control device for controlling an AC output supplied to a load based on waveform data read from an AC waveform memory, wherein an instantaneous value detecting means for detecting an instantaneous value of a voltage or a current supplied to the load. An average value detecting means for calculating an AC average value by integrating the instantaneous value of the voltage or current supplied to the load for each specific phase section; the instantaneous value of the voltage or current and the waveform data from the AC waveform memory. The first control means that forms the first control data based on the difference between the above-mentioned AC average value and the predetermined control target value are compared, and the coefficient value increased or decreased according to the magnitude relation between the two is calculated as above. Second control means for forming second control data by multiplying the amplitude value of the waveform data from the waveform memory, and the current or voltage controlled by the first and second control data, and the control target value. AC output control device, characterized in that it comprises a AC generation means for generating an output which is controlled for. 2. An AC output control device for controlling an AC output supplied to a load based on waveform data read from an AC waveform memory, wherein the instantaneous value detecting means detects an instantaneous value of a voltage supplied to the load. Average value detection means for calculating the AC voltage average value by integrating the instantaneous value of the voltage supplied to the load for each specific phase section, and based on the difference between the instantaneous value of the voltage and the waveform data from the AC waveform memory. Comparing the average value of the above voltage with a predetermined voltage target value, and increasing or decreasing the coefficient value according to the magnitude relationship between the two values from the waveform memory. Second control means for forming second control data by multiplying the amplitude value of the waveform data, and an output controlled by the first and second control data and having a voltage controlled with respect to the voltage target value. Generated alternating current AC output control device, characterized in that it comprises a stage. 3. An AC output control device for controlling an AC output supplied to a load based on waveform data read from an AC waveform memory, wherein an instantaneous value detecting means detects an instantaneous value of a voltage and a current supplied to the load. And an average value detecting means for calculating the AC current average value by integrating the instantaneous value of the current supplied to the load for each specific phase section, and comparing the average value of the current with a predetermined current target value. Of the amplitude value of the waveform data from the waveform memory and the difference between the instantaneous value of the voltage and the amplitude-adjusted waveform data from the amplitude adjusting means. AC means for generating control data based on the control data, and AC generation means for generating an output that is controlled by the control data and the current is controlled with respect to the current target value. Force control apparatus. 4. An AC output control device for controlling an AC output supplied to a load on the basis of waveform data read from an AC waveform memory, and an instantaneous value detecting means for detecting an instantaneous value of a voltage supplied to the load. Average value detection means for calculating the AC voltage average value by integrating the instantaneous value of the voltage supplied to the load for each specific phase section and the average value of the above voltage and a predetermined voltage target value are compared, Based on the difference between the amplitude adjustment means for multiplying the amplitude value of the waveform data from the waveform memory by the coefficient value increased or decreased according to the relationship and the instantaneous value of the voltage and the amplitude adjusted waveform data from the amplitude adjustment means. AC output control device comprising: control means for generating control data by means of the control data; and AC generation means for generating an output controlled by the control data, the voltage being controlled with respect to the voltage target value. . 5. An AC output control device for controlling an AC output supplied to a load based on waveform data read from an AC waveform memory, the instantaneous value detection detecting an instantaneous value of a voltage and a current supplied to the load. Means, an average value detection means for calculating the AC average value of the current and the voltage by integrating the instantaneous values of the voltage and the current supplied to the load for each specific phase section, the average value of the voltage and the predetermined voltage target value. And a coefficient value increased or decreased according to the magnitude relationship between the two, an amplitude adjusting means for multiplying the amplitude value of the waveform data from the waveform memory, and an average value of the current and a predetermined current target value are compared, Target value adjusting means for increasing / decreasing the voltage target value according to the magnitude relationship between the two, and control for forming control data based on the difference between the instantaneous value of the voltage and the amplitude-adjusted waveform data from the amplitude adjusting means. Means and Is controlled by the control data, AC output control unit in which the voltage; and a AC generation means for generating an output which is controlled with respect to the voltage target value. 6. An AC output control device for controlling an AC output supplied to a load based on waveform data read from an AC waveform memory, wherein an instantaneous value detecting means detects an instantaneous value of a voltage and a current supplied to the load. An average value detecting means for calculating an AC average value of voltage and current by integrating instantaneous values of voltage and current supplied to the load for each specific phase section; and an average value of the current and a predetermined current target value. And a first control data forming means for forming first control data by multiplying the amplitude value of the waveform data from the waveform memory by a coefficient value increased / decreased according to the magnitude relationship between the two, and A second control data is formed by comparing the average value with a predetermined voltage target value and multiplying the amplitude value of the waveform data from the waveform memory by a coefficient value increased or decreased according to the magnitude relationship between the two. Control data type Means, a target value adjusting means for comparing the average value of the current with a predetermined current target value, and increasing or decreasing the voltage target value according to the magnitude relation between the two, an instantaneous value of the voltage, and the first or first value. The third control data forming means for forming the third control data by adding the other of the control data to the difference of the one of the two control data, and the current and the voltage controlled by the third control data. AC output control means comprising: an AC generating means for generating an output controlled with respect to a target value. 7. The third control data forming means is a means for forming a difference between a sum of the first and second control data and an instantaneous value of the voltage. AC output control device. 8. The third control data forming means multiplies a difference between the first control data and the instantaneous value of the voltage by a predetermined gain and adds the second control data to obtain a third control. 7. The AC output control device according to claim 6, which is means for forming data. 9. The second control data forming means comprises limit means for limiting increase or decrease of the coefficient value of the first control data between a predetermined upper limit value and a predetermined lower limit value. Item 7. The AC output control device according to item 6. 10. The target value adjusting means decreases the voltage target value by a small value when the average value of the current is larger than the current target value, and when the average value of the current is smaller than the current target value, The calculating means for increasing the voltage target value by a small value, and the limiting means for limiting the output of the calculating means so as not to exceed the predetermined upper limit value and the lower limit value, the upper limit value being the AC generation 7. The AC output control device according to claim 6, wherein when the output voltage of the means matches the voltage target value, a constant value is set so that the rated output voltage is supplied to the load. 11. An integrating means for integrating the average value of the current or voltage in consideration of the polarity of each AC half cycle to detect the DC component of the AC output, and comparing the output of the integrating means with a predetermined range. Then, when it is out of the range, the DC adjustment data is slightly increased or decreased corresponding to the upper and lower parts of the range, and when it is within the range, an adjusting means for holding the previous value of the DC adjustment data; And a DC shift means for adding the control data to the DC control means so that the DC component of the output of the AC generating unit becomes a value within the range and is a substantially negligible amount with respect to the AC component. The AC output control device according to claim 10, wherein a loop operation is performed. 12. A counting means for detecting the convergence of a correction loop by counting a comparison result indicating that the output of the arithmetic means is within the range by a predetermined number of loops or more, and a convergence detection output of the counting means. 12. The AC output control device according to claim 11, further comprising switch means which is closed and supplies the output of the AC generating means to the load. 13. The first DC conversion means for adding the DC adjustment data to the second control data, the first addition means for adding an upper bit group of the DC adjustment data to the second control data, Using the lower bit group of the DC adjustment data as an address,
Memory means for reading out fine adjustment data having a number of "1" corresponding to the value represented by the lower bit group; serial shift means for serially shifting the fine adjustment data by one bit for each DC correction loop; 12. The AC output control device according to claim 11, further comprising a second addition unit that adds the output of "1" of the serial shift unit to the output of the first addition unit. 14. The alternating current generating means performs a switching operation by a PWM means for generating a PWM pulse whose duty changes with time according to the amplitude value of the input control data, and an output pulse of the PWM means to perform a switching operation to convert a direct current input to an alternating current. The AC output control device according to any one of claims 1 to 6, further comprising an inverter bridge switch for converting the output.