JPH086920A - Information processor - Google Patents

Abstract

PURPOSE:To provide an information processor capable of debugging also a bus access to an on-chip resource such as a built-in ROM, a built-in RAM and a built-in peripheral circuit only by the addition of a little hardware by connecting the processor to an external debugging device such as an in-circuit emulator. CONSTITUTION:A processor consisting of a decoder part 1, a PC calculation part 2 and a data pass part 3 executes an instruction. An external bus interface part 7 connects internal buses for connecting the processor to on-chip resources consisting of a built-in ROM 4, a built-in RAM 5 and a built-in peripheral circuit 6 to an external memory 11. An external debugging device interface part 10 connects the internal buses to an in-circuit emulator 12. A debugging mode control operates the part 9 manages the existence of a debugging state and interface part 10 in the debugging state to allow the emulator 12 to execute bus access instead of the on-chip resources.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device such as a microcontroller having a processor and a built-in peripheral circuit such as a built-in memory and a DMA in a chip, and more particularly to an external debug device such as an in-circuit emulator. It is characterized by a bus structure for connection and a structure relating to a bus control system.

[0002]

2. Description of the Related Art A conventional information processing apparatus, as shown in FIG. 4, for example, includes a decoder section 41, a PC (program counter) calculation section 42, a data path section 43, in a chip.
Built-in ROM 44, built-in RAM 45, built-in peripheral circuit 4
6, an external bus interface unit 47, and a bus control unit 48. External bus interface section 47
An external memory 49 and an in-circuit emulator 50 as an external debug device are connected to the. The decoder unit 41 decodes the machine language instruction and controls each unit of the chip. The PC calculator 42 calculates the address of the instruction to be decoded. The data path unit 43 performs calculation by ALU or the like. The built-in ROM 44 stores instructions. Built-in R
The AM 45 stores data. The internal peripheral circuit 46 is
It consists of a DMA and a timer. The external bus interface unit 47 controls data transfer with an external memory 49 outside the chip. The bus control unit 48 is provided between the processor core including the decoder unit 41, the PC calculation unit 42, and the data path unit 43, and on-chip resources such as the built-in ROM 44, built-in RAM 45, and built-in peripheral circuit 46 and the external bus interface unit 47. Control the passing of data. That is, the bus controller 48 stores the RO in the built-in ROM 44.
The M control signal is output, the RAM control signal is output to the internal RAM 45, the peripheral control signal is output to the internal peripheral circuit 46,
External memory 49 and in-circuit emulator 50
The external bus control signal is output to.

In this conventional information processing apparatus, when data is loaded from the external memory 49 during debugging, the data path unit 43 first calculates the address of the data to be loaded and outputs it to the internal address bus. Next, the bus control unit 48 controls the external bus interface unit 47 to output the address on the internal address bus to the external address bus. Next, the external memory 49 outputs the data corresponding to the address on the external address bus to the external data bus. Next, the external bus interface unit 47
Data is input from the external data bus and output to the internal data bus. Next, the data path unit 43 inputs the data on the internal data bus. This completes the data access. At the time of this bus access, the in-circuit emulator 50, which is an external debug device, monitors the operation of the processor by monitoring the contents of the external address bus and the external data bus. Further, when performing an instruction break or an operand break for debugging, the in-circuit emulator 50 generates an interrupt when the contents of the monitored external address bus or external data bus match the address or data to be broken. generate.

[0004]

However, in the above-mentioned conventional information processing apparatus, the in-circuit emulator 50 is used.
Has a problem that the instruction break and the operand break can be generated only when the external memory 49 is accessed.

In the above conventional information processing apparatus, the built-in R
In order to generate an instruction break or an operand break with respect to on-chip resources such as the OM 44, the built-in RAM 45, and the built-in peripheral circuit 46, a circuit that stores an address and data that cause a break in the chip and the address and data A circuit for detecting a match with an address or data for bus access and generating a break must be added, and a chip for connecting to the in-circuit emulator 50 is separately created or debugged on a mass-produced chip. Therefore, there is a problem in that the hardware is increased, because the hardware for this has to be added.

Further, in the above conventional information processing apparatus, when the external memory 49 is not connected because the system for mounting the chip is not constructed, the external memory 49 cannot be accessed and debugging cannot be performed. There was a problem that there is. The present invention has been made in view of such circumstances, and by connecting to an external debug device such as an in-circuit emulator, it is possible to turn on the built-in ROM, built-in RAM, built-in peripheral circuit, etc. by adding a small amount of hardware. An object of the present invention is to provide an information processing device capable of debugging bus access to chip resources.

A further object of the present invention is to provide an information processing apparatus which can be debugged by connecting it to an external debugging device such as an in-circuit emulator even when the external memory is not connected.

[0008]

According to a first aspect of the present invention, a processor for executing an instruction, an on-chip resource such as a memory for storing an instruction and data, a built-in peripheral circuit, and the like are connected to the processor and the on-chip resource. An external bus interface unit that connects the internal bus to the external memory, an external debug device interface unit that connects the internal bus to an external debug device, and manages the debug state, and in the debug state, the external debug device interface unit Is included in the chip, and a debug mode control unit for performing bus access to an external debug device instead of on-chip resources by operating the device.

According to a second aspect of the present invention, a processor for executing instructions, on-chip resources such as a memory for storing instructions and data and a built-in peripheral circuit, and an internal bus connecting the processor and the on-chip resources to an external memory. The external bus interface part to connect, the external debug device interface part that connects the internal bus to the external debug device, and manages the debug state, and when in the debug state,
By operating the external debug device interface, the debug mode controller that makes bus access to the external debug device instead of on-chip resources, and the external bus trace mode that monitors access to external memory are detected, and the external bus trace is detected. An external bus trace mode control unit that outputs an address and data for accessing an external memory from the external debug device interface unit in the mode is provided in the chip.

According to a third aspect of the present invention, a processor for executing instructions, on-chip resources such as a memory for storing instructions and data and a built-in peripheral circuit, and an internal bus connecting the processor and the on-chip resources to an external memory. An external bus interface unit for connection, an external debug device interface unit for connecting the internal bus to an external debug device, managing the debug state, and operating the external debug device interface unit in the debug state Detects the debug mode control unit that makes bus access to the external debug device instead of the on-chip resources and the external memory emulation mode in which no external memory exists, and suppresses the operation of the external bus interface unit in the external memory emulation mode. Then
Instead, an external memory emulation mode control unit that operates the memory incorporated in the external debug device as an external memory by operating the external debug device interface unit is provided in the chip.

[0011]

In the invention of claim 1, the processor executes an instruction. On-chip resources include a memory for storing instructions and data, a built-in peripheral circuit, and the like. The external bus interface unit connects the internal bus connecting the processor and the on-chip resources to the external memory. The external debug device interface unit connects the internal bus to the external debug device. The debug mode control unit manages the debug state, and operates the external debug device interface unit in the debug state to cause the external debug device to access the bus instead of the on-chip resource.

In the invention of claim 2, the processor is
Execute an instruction. On-chip resources include a memory for storing instructions and data, a built-in peripheral circuit, and the like. The external bus interface unit connects the internal bus connecting the processor and the on-chip resources to the external memory. The external debug device interface unit connects the internal bus to the external debug device. The debug mode control unit manages the debug state, and operates the external debug device interface unit in the debug state to cause the external debug device to access the bus instead of the on-chip resource. The external bus trace mode control unit detects the external bus trace mode for monitoring access to the external memory, and in the external bus trace mode,
The address and data for accessing the external memory are output from the external debug device interface section.

In the invention of claim 3, the processor is
Execute an instruction. On-chip resources include a memory for storing instructions and data, a built-in peripheral circuit, and the like. The external bus interface unit is for connecting an internal bus connecting the processor and the on-chip resources to an external memory. The external debug device interface unit connects the internal bus to the external debug device. The debug mode control unit manages the debug state, and operates the external debug device interface unit in the debug state to cause the external debug device to access the bus instead of the on-chip resource. The external memory emulation mode control unit detects the external memory emulation mode in which the external memory does not exist, suppresses the operation of the external bus interface unit in the external memory emulation mode, and operates the external debug device interface unit instead. , The memory built in the external debug device is operated as the external memory.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of an information processing device according to a first embodiment of the present invention. This information processing device includes a decoder unit 1, a PC (program counter) calculation unit 2 and a data path in a chip. Part 3, built-in ROM 4, built-in RA
M5, a built-in peripheral circuit 6, an external bus interface unit 7, a bus control unit 8, a debug mode control unit 9,
An external debug device interface section 10 is provided. The external bus interface unit 7 includes an external memory 1
1 is connected to the external debug device interface unit 1
An in-circuit emulator 12 as an external debug device is connected to 0. The in-circuit emulator 12 includes an ICE (in-circuit emulator) memory 13. The decoder unit 1 decodes the instruction,
It outputs a control signal to each unit of the processor core including the decoder unit 1, the PC calculation unit 2, and the data path unit 3. PC
The calculator 2 calculates the address of the instruction decoded by the decoder 1. The data path unit 3 performs an operation based on the control signal output from the decoder unit 1. Built-in R
The OM 4 stores instructions. The built-in RAM 5 stores data. The built-in peripheral circuit 6 includes a DMA and a timer. The external bus interface unit 7 controls the exchange of addresses and data between the internal address bus or internal data bus and the external address bus or external data bus to which the external memory 11 or the like is connected. Bus control unit 8
Is an internal address bus between the processor core including the decoder unit 1, the PC calculating unit 2, and the data path unit 3 and the on-chip resources including the internal ROM 4, the internal RAM 5, and the internal peripheral circuit 6 and the external memory 11. Controls the passing of data through the data bus. That is, the bus control unit 8 outputs a ROM control signal to the built-in ROM 4 and the in-circuit emulator 12, and the built-in RAM 5
And a RAM control signal to the in-circuit emulator 12 and a peripheral control signal to the built-in peripheral circuit 6 and the in-circuit emulator 12.
Also, the external bus control signal is output to the in-circuit emulator 12. The debug mode control unit 9 holds that the in-circuit emulator 12, which is an external debug device, is connected and is in the debug state, and controls the bus access in the debug state. That is, the debug mode control unit 9 outputs an access prohibition signal to an on-chip resource including the built-in ROM 4, the built-in RAM 5, and the built-in peripheral circuit 6, and outputs the debug mode instruction signal to the external debug device interface unit 10.

Next, the operation will be described. When fetching an instruction from the built-in ROM 4 during debugging, first, the PC
The calculator 2 calculates the next instruction or the instruction address of the branch destination, and outputs the instruction address to the internal address bus. When the in-circuit emulator 12 is connected, the debug mode control unit 9 holds the state in a flag or the like, and outputs an access prohibition signal which is a signal for suppressing the operation to the built-in ROM 4. Output. At the same time, the debug mode control unit 9 controls the external debug device interface unit 10 to output the contents of the internal address bus to the external debug address bus. As a result, the built-in ROM 4 does not output the instruction data corresponding to the address, but instead the ICE memory 13 mounted in the in-circuit emulator 12 outputs the instruction data corresponding to the address to the external debug data bus. This instruction data is output to the internal data bus via the external debug device interface section 10, and the decoder section 1 inputs the instruction data from the internal data bus to decode the instruction. This operation is the same for accessing the built-in RAM 5 and built-in peripheral circuit 6.

In this way, the built-in ROM 4 and built-in RAM 5
In bus access to on-chip resources such as the internal peripheral circuit 6 and
Instruction breaks and operand breaks can be generated by monitoring the contents of the external debug address bus and the external debug data bus. Further, by rewriting the data on the ICE memory 13 in the in-circuit emulator 12, it is possible to easily rewrite the instruction and the data and execute the instruction.

When the bus connected to the built-in ROM 4 and the bus connected to the built-in RAM 5 are separated and there are a plurality of internal address buses and internal data buses, the plurality of internal buses are connected to the external debug device interface section 10.
It may be connected to the in-circuit emulator 12 via. In addition, the external debug device interface unit 10
Can be realized with a terminal bonding option, etc.
One chip can be used both as a mass production chip and a chip connected to the in-circuit emulator 12. (Embodiment 2) FIG. 2 is a block diagram of an information processing apparatus according to Embodiment 2 of the present invention. Information of Embodiment 1 shown in FIG. 1 except that an external bus trace mode control unit 21 is provided in the chip. It has the same configuration as the processing device. Therefore, FIG.
The same components as the components shown in are given the same part numbers, and the description thereof will be omitted. The external bus trace mode control unit 21, when accessing the external memory 11,
The external bus trace mode for monitoring the address and data is stored, and bus access in the external bus trace mode is controlled. That is, the external bus trace mode control unit 21 outputs the external bus trace mode instruction signal to the bus control unit 8 and the external debug device interface unit 10.

Next, the operation will be described. When performing bus access to the external memory 11 during debugging, the external bus trace mode control unit 21 uses a flag or the like to indicate that the external bus trace mode for monitoring the address and data to access the external memory 11 is in use. Keep it. When bus access is performed to the external memory 11 in this state, the external bus interface unit 7 addresses the external address bus or external data bus connected to the external memory 11 and the internal address bus or internal data bus. Since the external bus trace mode control unit 21 holds the mode for monitoring the address and data of the external bus at the same time as the transfer of the data and the data,
By controlling the external debug device interface unit 10,
The contents of the internal address bus and internal data bus are output to the external debug address bus and external debug data bus. As a result, regarding bus access to the external memory 11, it is possible to monitor the address and data via the external debug address bus and the external debug data bus.

As described above, with respect to the bus access to the external memory 11, the instruction break and the operand break are performed by using the external debug device interface section 10 similar to the access to the on-chip resources such as the built-in ROM 4, the built-in RAM 5 and the built-in peripheral circuit 6. Can correspond to. (Third Embodiment) FIG. 3 is a block diagram of an information processing apparatus according to the third embodiment of the present invention. Information of the first embodiment shown in FIG. 1 except that an external memory emulation mode control unit 31 is provided in the chip. It has the same configuration as the processing device. Therefore, the same components as those shown in FIG. 1 are designated by the same component numbers, and the description thereof will be omitted. When the external memory is not connected, the external memory emulation mode control unit 31 stores the state and controls to access the ICE memory 13 in the in-circuit emulator 12, which is an external debug device, instead of the external memory. To do. That is, the external memory emulation mode control unit 31 outputs an external access prohibition signal to the external bus interface unit 7, and outputs an external memory emulation mode instruction signal to the bus control unit 8 and the external debug device interface unit 10.

Next, the operation will be described. When the external memory is not connected, the external memory emulation mode control unit 31 uses a flag or the like to hold that the ICE memory 13 in the in-circuit emulator 12 is used instead of the external memory. deep. When a bus access is made to the external memory in this state, the external memory emulation mode control unit 31 outputs an external access prohibition signal to the external bus interface unit 7 to inhibit access to the external address bus and external data bus. To do. Then, the external memory emulation mode control unit 31 outputs an external memory emulation instruction signal to the external debug device interface unit 10, and the external memory emulation mode control unit 31 outputs between the internal address bus or the internal data bus and the external debug address bus or the external debug data bus. Control to transfer data. As a result, the access to the external memory is changed to the access to the in-circuit emulator 12, and the ICE memory 13 in the in-circuit emulator 12 can be accessed.

As described above, it is possible to debug even when there is no external memory at the stage where the system for mounting the chip is not constructed.

[0022]

As described above, according to the present invention, a processor for executing an instruction, an on-chip resource such as a memory for storing an instruction and data, a built-in peripheral circuit, and the like are connected to the processor and the on-chip resource. An external bus interface unit that connects the internal bus to the external memory, an external debug device interface unit that connects the internal bus to an external debug device, and manages the debug state, and in the debug state, the external debug device interface unit Since a debug mode control unit that makes bus access to an external debug device instead of on-chip resources by operating the on-chip resource is provided in the chip, an external circuit such as an in-circuit emulator can be connected via the external debug device interface unit. The debug device has a built-in ROM, built-in RAM, or built-in peripheral Can monitor the bus access to the on-chip resources such as a circuit, it is possible to easily generate an instruction break or operand break. That is, by connecting an external debug device such as an in-circuit emulator to the information processing device, bus access to on-chip resources such as built-in ROM, built-in RAM and built-in peripheral circuits can be performed with a small amount of additional hardware. Can also be debugged.

An external bus interface for connecting a processor for executing instructions, on-chip resources such as a memory for storing instructions and data and a built-in peripheral circuit, and an internal bus connecting the processor and on-chip resources to an external memory. Part, the external debug device interface part that connects the internal bus to the external debug device, and managing the debug state, and operating the external debug device interface part in the debug state to replace the on-chip resource. The debug mode control unit that makes the bus access to the external debug device and the external bus trace mode that monitors the access to the external memory are detected, and the address to access the external memory from the external debug device interface unit in the external bus trace mode is detected. Or data If an external bus trace mode control unit is provided in the chip, it can be monitored by an external debug device such as an in-circuit emulator through the external debug device interface unit even when accessing an external memory, and the on-chip Instruction breaks and operand breaks can be handled using the same external debug device interface as the resources.

Further, a processor for executing instructions, on-chip resources such as a memory and a built-in peripheral circuit for storing instructions and data, and an external bus for connecting an internal bus connecting the processor and the on-chip resources to an external memory. By managing the bus interface section, the external debug apparatus interface section that connects the internal bus to the external debug apparatus, and the debug state, and operating the external debug apparatus interface section in the debug state, on-chip resources Instead, the debug mode control unit that makes bus access to the external debug device and the external memory emulation mode in which the external memory does not exist are detected, and the operation of the external bus interface unit is suppressed in the external memory emulation mode. External debug device If the chip includes an external memory emulation mode control unit that operates the memory incorporated in the external debug device as an external memory by operating the interface unit, the external memory can operate via the external debug device interface unit. Instead of, the memory mounted on the external debugging device can be used, and debugging can be performed even when the system for mounting the chip is not built and the external memory is not connected.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an information processing device according to a second embodiment of the present invention.

FIG. 3 is a block diagram of an information processing device according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a conventional information processing device.

[Explanation of symbols]

 1 Decoder 2 PC Calculation 3 Data Path 4 Built-in ROM 5 Built-in RAM 6 Built-in Peripheral Circuit 7 External Bus Interface 8 Bus Control 9 Debug Mode Control 10 External Debug Device Interface 11 External Memory 12 In-Circuit Emulator 13 ICE Memory 21 External bus trace mode controller 31 External memory emulation mode controller

Claims (3)

[Claims] 1. A processor that executes instructions, an on-chip resource such as a memory or a built-in peripheral circuit that stores instructions or data, and an external bus that connects an internal bus that connects the processor and the on-chip resources to an external memory. A bus interface unit, an external debug device interface unit for connecting the internal bus to an external debug device, managing a debug state, and operating the external debug device interface unit when in the debug state, An information processing device, comprising: a debug mode control unit for bus access to the external debug device instead of on-chip resources; 2. A processor that executes instructions, an on-chip resource such as a memory or a built-in peripheral circuit that stores instructions or data, and an external bus that connects an internal bus that connects the processor and the on-chip resources to an external memory. A bus interface unit, an external debug device interface unit for connecting the internal bus to an external debug device, managing a debug state, and operating the external debug device interface unit when in the debug state, A debug mode control unit that makes a bus access to the external debug device instead of on-chip resources, and an external bus trace mode that monitors access to the external memory is detected, and in the external bus trace mode,
An information processing device comprising: an external bus trace mode control unit for outputting an address and data for accessing the external memory from the external debug device interface unit; 3. A processor for executing an instruction, an on-chip resource such as a memory or a built-in peripheral circuit for storing the instruction or data, and an internal bus connecting the processor and the on-chip resource to an external memory. An external bus interface unit for connecting the internal bus to an external debug device, and managing the debug state, and operating the external debug device interface unit in the debug state. A debug mode control unit that makes a bus access to the external debug device instead of the on-chip resources; and an external memory emulation mode in which the external memory does not exist is detected, and in the external memory emulation mode, Suppress the operation, An external memory emulation mode control unit that operates the external debug device interface unit instead of the external debug device to operate the memory built in the external debug device as the external memory. Information processing equipment.