JPH08340250A - Variable frequency divider - Google Patents

Abstract

PURPOSE: To output a highly accurate frequency-divided clock from a reference clock by accumulating a set value outputted from a register in each reference clock and counting and outputting an overflow signal outputted at intervals of a prescribed time. CONSTITUTION: An accumulator 16 accumulates a set value outputted from a register 14 in each reference clock, i.e., executes cumulative addition or cumulative subtraction, and outputs an overflow signal, i.e., a carry signal in the case of cumulative addition or an inverse signal of a carry signal in the case of cumulative subtraction. A counter 18 counts, i.e., counts up or counts down the overflow signal outputted from the accumulator 16 and outputs a count signal of at least one bit. A selector 20 selects one bit in the count signal by a selection signal and outputs the selected bit as a frequency divided clock. Thereby the frequency of a reference clock can be divided by a frequency dividing ratio less than a decimal point by properly determining the number of bits in the accumulator 16 and the set value set up in the register 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable frequency divider, and more particularly to a variable frequency divider used for a baud rate generator for generating a communication clock in serial communication.

[0002]

2. Description of the Related Art FIG. 14 is a block diagram of an example of a conventional variable frequency divider. This variable frequency divider 100 is used for a baud rate generator, and has a reference clock generator 12 that generates a reference clock of a predetermined frequency and a count signal C that is counted up by this reference clock.
, A register 14 for outputting the set value N set by the CPU (central processing unit) 22, a coincidence detector 52 for comparing the count signal C with the set value N, and the coincidence detector. A toggle flip-flop 102 that divides the signal output from 52 by two and outputs a divided clock is formed.

In the variable frequency divider 100, first, a set value N is set in the register 14 by the CPU 22, and the set value N is directly input to the coincidence detector 52. On the other hand, the reference clock generated by the reference clock generator 12 is input to the up counter 50. As shown in FIG. 16, in the up-counter 50, the count signals C are counted up one by one in synchronization with the rising edge of the reference clock, depending on the set value N, from “0” to “N”. Is also input to the coincidence detector 52.

Then, in the coincidence detector 52, the set value N and the count signal C are compared, and if a coincidence is detected, the coincidence detector 52 outputs a coincidence detection signal, and the coincidence detection signal is output from the up counter 50. And the toggle flip-flop 102. As shown in FIG. 16, when the coincidence detection signal is input to the up counter 50, the count signal C is cleared and returned to "0".
Further, the divided clock is inverted in the toggle flip-flop 102, and thereafter, the above-described operation is repeated to obtain the divided clock from the reference clock.

FIG. 15 is a block diagram of another example of the conventional variable frequency divider. Compared with the variable frequency divider 100, the variable frequency divider 104 uses a down counter 58 that outputs a count signal C counted down by a reference clock, instead of the up counter 50, and that of the coincidence detector 52. Instead, the only difference is that the zero detector 60 that outputs a zero detection signal when the count signal C becomes "0" is used, and therefore, the same components are given the same reference numerals and their description is omitted. Omit it.

That is, in the variable frequency divider 104,
When the set value N set in the register 14 is set (loaded) in the down counter 58 by the zero detection signal, the down counter 58 counts down the count signal C from “N” to “0”. Then, when the zero detector 60 detects that the count signal C has become “0” and outputs the zero detection signal, the toggle flip-flop 102 inverts the divided clock and the down counter 58 The set value N is reset.

In these variable frequency dividers 100 and 104, the counters 50 and 58 function as (N + 1) -ary counters, and according to the set value N set in the register 14,
A divided clock obtained by dividing the frequency of the reference clock by 2 × (N + 1) can be obtained. In this way, even if the frequency of the reference clock is fixed, the frequency of the obtained divided clock can be changed as appropriate by changing the set value N set in the register 14.

By the way, in serial communication, in general,
The divided clocks of the variable frequency dividers 100 and 104 described above are further divided into 1/16 or 1/64 to obtain the baud rate. For example, conventionally, variable frequency dividers 100, 1
04 is provided with 8- to 12-bit counters 50 and 58, and by giving 1 to 10 MHz as the frequency of the reference clock, the frequency of the divided clock is 4.8 to 19.2.
When using KHz, that is, a baud rate obtained by dividing a divided clock into 1/16, the baud rate is 300 to 12
00 bps was often used.

In this case, the division ratio (= frequency of the reference clock
Number f_sys/ Frequency of divided clock f _baud) Is over 2 digits and large
Because of the threshold, that is, if the division ratio is large, the baud rate is necessary.
The frequency of the divided clock obtained and the variable frequency divider 100,
The error from the frequency of the divided clock output from 104
Since it can be made smaller, the variable frequency dividers 100, 10
The frequency of the divided clock output from 4 is accurate enough.
It was being done.

However, in recent years, the speed of the reference clock and the speed of communication have been increased.
30MHz, baud rate 2400-38400b
When the speed is increased to ps, the variable frequency dividers 100 and 104 divide the reference clock by 2 × (N + 1), that is, the frequency division can be performed only by an integer value. When the division ratio becomes small, there is a problem that the frequency error of the divided clock output from the variable frequency dividers 100 and 104 may increase with respect to the frequency of the divided clock required by the baud rate. It was

For example, when 38400 bps is used as the baud rate obtained by dividing the divided clock into 1/16,
The required frequency of the divided clock is 614.4 KHz, so the frequency of the reference clock is 10 MHz, 8
Given MHz and 5 MHz, the required division ratio is 16.28 (= 10 MHz / 614.4K).
Hz), 13.02 (= 8 MHz / 614.4 KHz)
And 8.14 (= 5 MHz / 614.4 KHz).

On the other hand, since the frequency division ratio of the variable frequency dividers 100 and 104 shown in FIGS. 14 and 15 is represented by 2 × (N + 1), the frequency of the reference clock is 10 MHz, 8
For MHz and 5 MHz, the division ratio is 1 for each.
6, 14 and 8 and as a result
The divided clocks output from the variable frequency dividers 100 and 104 are 625 KHz, 571.43 KHz and 6 respectively.
It becomes 25 KHz. Therefore, the error of the frequency of the divided clock generated with respect to the required frequency of the divided clock, that is, the error of the generated baud rate is 1.7%, 7.0%, and 1.7%, respectively. Becomes

Generally, it is considered that the baud rate error is limited to about 2% in serial communication. That is, if the error of the baud rate is large, a communication error is likely to occur. Therefore, in the above-described example, the variable frequency dividers 100 and 104 cannot be used with the frequency of the reference clock set to 8 MHz. Therefore, when the system clock is used as the reference clock, the system clock must be changed in order to decrease the frequency of the system clock or increase the frequency division ratio according to the baud rate used for serial communication. The reference clock generator 12 dedicated to the baud rate is provided without using it, and the frequency of this reference clock is increased.

However, for example, when the maximum frequency of the reference clock allowed in the system is 8 MHz,
If the frequency of the system clock is reduced to 5 MHz in order to eliminate the error in the baud rate used for serial communication, there is a problem in that the performance of the entire system is degraded. Further, when the reference clock generator 12 is provided, it is necessary to prepare a dedicated oscillator for serial communication, which causes a problem of high cost.

[0015]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a variable frequency divider capable of obtaining a frequency-divided clock with high accuracy from a reference clock in view of various problems based on the above-mentioned prior art. It is in.

[0016]

As described above, according to the conventional variable frequency divider used in the baud rate generator, the obtained frequency division ratio is an integer value. For this reason, when the frequency division ratio required with the recent increase in the speed of communication systems becomes small, it becomes difficult to obtain sufficient frequency accuracy, and various restrictions have been imposed for that purpose. Further, conventionally, the accuracy is kept within 1 to 2%, and the duty of the divided clock (the ratio between the high level width and the low level width of the pulse) is 50%.
Was supposed to get. However, in reality, the accuracy is strictly required in the serial communication, but the bias of the duty is not strictly required. The present inventors paid attention to this point and found that the frequency-divided clock required from the reference clock can be generated with high accuracy by slightly shifting the duty.

In other words, in order to achieve the above object, the first aspect of the present invention is to accumulate a set value output from the register for each register and a register for outputting the set value set. An at least 1-bit accumulator for performing an arithmetic operation and outputting an overflow signal; and a counter for counting the overflow signal output from the accumulator and outputting at least a 1-bit count signal. To provide a variable frequency divider.

A second aspect of the present invention is the variable frequency divider, which further outputs a second count signal of at least 1 bit reset by a detection signal and counted for each of the reference clocks. A second counter, a detector that outputs the detection signal when the second counter counts a count value corresponding to the set value output from the register, and a digit output from the accumulator. A variable frequency divider comprising: a switch that selectively outputs an overflow signal and a detection signal output from the detector to the counter according to a switch signal.

Further, according to a third aspect of the present invention, a register for outputting the set set value, and a set value and a predetermined value output from the register are selectively output according to the switching signal and the detection signal. 1 switch, an accumulator of at least 1 bit for accumulating output signals of the first switch for each reference clock of a predetermined frequency, and outputting an accumulation signal and an overflow signal, and this accumulator When a count value corresponding to the set value output from the register is accumulated, a detector that outputs the detection signal, and a overflow signal output from the accumulator according to the switching signal and the overflow signal A second switching device for selectively outputting a detection signal output from the detector;
And a counter that counts the output signal of the switching device and outputs a count signal of at least 1 bit.

The predetermined value output from the first switch is preferably 1 or -1.

Further, the second switching device selectively outputs the overflow signal output from the accumulator and the detection signal output from the detector in response to the switching signal, instead of the overflow signal. It is preferable that the polarity of the overflow signal output from the accumulator is inverted according to the switching signal.

The switching signal is preferably one of the upper bits of the set value output from the register.

Further, when the count signal of at least 1 bit is a count signal of 2 bits or more, it is preferable to include a selector which selectively outputs 1 bit of the count signal as a divided clock by a selection signal.

[0024]

In the variable frequency divider according to the first aspect of the present invention, the set value output from the register by the accumulator is accumulated for each reference clock, that is, cumulative addition or subtraction is performed, and a digit overflow occurs at every predetermined time. A signal, that is, a carry signal (carry signal) in the case of cumulative addition, and a carry borrow signal (borrow signal) in the case of cumulative subtraction, is output to the counter, and the counter counts this carry-over signal, that is, By counting up or down, the reference clock is divided and the divided clock is output.

The variable frequency divider according to the second aspect of the present invention is
It has both the function of the conventional variable frequency divider and the function of the variable frequency divider of the first aspect of the present invention. Here, the conventional variable frequency divider is the variable frequency divider 1 described in the related art.
00, 104, etc.

The variable frequency divider according to the third aspect of the present invention is
Like the variable frequency divider of the second aspect of the present invention, it has the function of the conventional variable frequency divider and the function of the variable frequency divider of the first aspect of the present invention. The circuit scale of the variable frequency divider according to the first aspect of the present invention is shared by the structural elements of the variable frequency divider of the first aspect of the present invention.

Therefore, in the variable frequency divider of the present invention,
By appropriately determining the number of bits of the accumulator and the set value set in the register, it is possible to divide the reference clock as if the division ratio had a value below the decimal point. Further, like the variable frequency divider of the second aspect of the present invention,
By having both the function of the conventional variable frequency divider and the function of the variable frequency divider of the first aspect of the present invention, it is possible to obtain a highly accurate frequency division clock at both high frequency and low frequency. Further, like the variable frequency divider of the third aspect of the present invention, by sharing the constituent elements, the circuit scale can be reduced. Therefore, according to the variable frequency divider of the present invention, even if the reference clock or the communication speed is increased and the required frequency division ratio is reduced, a highly accurate frequency division clock can be generated from the reference clock with a small circuit scale. Therefore, it can be easily obtained in a programmable manner.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The variable frequency divider of the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram of an embodiment of a variable frequency divider according to the first aspect of the present invention. This variable frequency divider 10
A reference clock generator 12 for outputting a reference clock, and C
Register 1 that outputs the set value set by PU22
4, an accumulator 16 that outputs an overflow signal, a counter 18 that outputs a count signal, and a selector 20 that outputs a divided clock. This variable frequency divider 10
In, the reference clock and the set value are input to the accumulator 16, the overflow signal is input to the counter 18,
A count signal and a selection signal are input to the selector 20.

Here, the reference clock generator 12 is for generating a reference clock having a predetermined frequency, and may be, for example, a crystal oscillation circuit. According to the variable frequency divider 10 of the first aspect of the present invention, it is possible to obtain the optimum frequency-divided clock from the system clock.
The variable frequency divider 10 need not be provided with a dedicated reference clock generator 12. Therefore, the reference clock generator 1
2 may be provided, but it is preferable to use the system clock as the reference clock in terms of cost and mounting area reduction.

The register 14 supplies the set value to be set to the accumulator 16, and may be a general register composed of a plurality of flip-flops, for example. In the figure, the CPU 2
2 shows an example in which the setting value is set by software, but the setting value is not limited to this, and the setting value may be set by hardware by using a switch or the like. good.

Subsequently, the accumulator 16 accumulates the set value output from the register 14 for each reference clock and outputs an overflow signal. Examples of the accumulator 16 include a cumulative adder that outputs a carry signal as an overflow signal and a cumulative subtractor that outputs a borrow signal as an overflow signal. The register 14 and the accumulator 16 need to have at least 1 bit, but it is preferable that the numbers of these bits are the same.

The counter 18 counts the overflow signal output from the accumulator 16 and outputs a count signal of at least 1 bit. The counter 18 may be, for example, an up counter or a down counter, and may be an asynchronous counter that counts an overflow signal as a clock signal or a synchronous counter that counts an overflow signal as a permission signal by a reference clock. Either may be used.

Finally, the selector 20 selects 1 bit in the count signal output from the counter 18 by the selection signal and outputs it as the divided clock. It goes without saying that the selector 20 is not always necessary when the count signal output from the counter 18 is only one bit.

Next, FIG. 2 shows a structural circuit diagram of an embodiment of an accumulator and a counter which constitute the variable frequency divider according to the first aspect of the present invention described above. In the figure, the accumulator is a cumulative adder 16 including an m-bit cumulative addition unit 24 (24a, 24b), and the counter is an up counter 18 including an n-bit counter unit 40 (40a, 40b).

In the cumulative adder 16, each cumulative addition unit 24a has a full adder 32 composed of EXOR gates 26 and 28 and an AND-OR composite gate 30, and an output of the full adder 32 as a reference clock signal. And a flip-flop 34 which holds the signal in synchronization with the rising edge of. The portion corresponding to the full adder 32 of the cumulative addition unit 24b of the least significant bit is configured by the half adder 38 including the EXOR gate 26 and the AND gate 36 because the carry signal from the lower bit is not input. . In addition, each cumulative addition unit 24
A set value is input from a register 14 (not shown), and a carry signal is output from the cumulative addition unit 24a of the most significant bit.

In addition, in the counter 18, each counter unit 40a E which inverts the count signal.
It is composed of an XOR gate 42, an AND gate 44 for generating a carry signal to the upper bit, and a flip-flop 46 for holding the count signal in synchronization with the rising edge of the reference clock signal. Since the most significant bit counter unit 40b does not need to output the carry signal to the upper bits, the AND gate 44 that generates the carry signal.
Does not have. The carry signal output from the most significant bit cumulative addition unit 24 a of the cumulative adder 16 is input to the least significant bit counter unit 40 a of the counter 18, and the respective counter units 40 a
Outputs a count signal. The accumulator 16 and the counter 18 constituting the variable frequency divider of the first aspect of the present invention
Is configured in this way, for example.

Next, the first aspect of the present invention configured as described above
In the variable frequency divider 10 of the aspect, as shown in FIG. 2, the accumulator 16 is an m-bit cumulative adder, and the counter 18
Is an n-bit up counter,
The operation will be described.

In the variable frequency divider 10, first, the CPU 22 sets a set value R in the register 14, and the set value R is directly input to the accumulator 16. Accumulator 1
6, the set value R is set to the reference clock generator 12
The cumulative addition is performed in synchronization with the rising edge of the reference clock. Then, according to the number of bits of the accumulator 16 and the set value R, the cumulative addition value is the number of bits m of the accumulator 16.
When it exceeds, a carry signal is output from the accumulator 16 and this carry signal is input to the counter 18.

Then, a carry signal is input to the counter 18.
Then, in the counter 18, the count signal is the reference
One by one in synchronization with the rising edge of the clock, starting from "0"
‘2 ⁿThis counts up to -1 '.
The number is input to the selector 20. Output from counter 18
The count signal to be generated is the selection signal in the selector 20.
Selects one bit in the count signal,
Is output as the divided clock. After that, the operation described above
By repeatedly performing,
I'm getting a hook.

In the variable frequency divider 10, the frequency f _{c of the} overflow signal is represented by f _c = f _sys × R / 2 ^m . Here, f _sys is the frequency of the reference clock, R is a set value, and m is the number of bits of the accumulator 16.

Further, the frequency f _baud of the _divided clock is represented by f _baud = f _c / 2 ^{j + 1} = f _sys × R / 2 ^{j + m + 1} . Here, j (= 0, 1, 2, ..., N-
1) corresponds to the bit of the count signal selected by the selector 20.

Accordingly, the frequency division ratio is represented by the frequency division ratio = f _sys / f _baud = 2 ^{j + m + 1} / R.

Therefore, the variable frequency divider 1 according to the first aspect of the present invention
According to 0, it is possible to obtain a divided clock obtained by dividing the frequency of the reference clock by (2 ^{j + m + 1} / R) according to the set value R set in the register 14. That is, the first aspect of the present invention
In the variable frequency divider 10 of the aspect, since the reference clock can be frequency-divided not only by an integer value but also by a numerical value having a value after the decimal point, the set value R set in the register 14 and the accumulator 16 are set. By appropriately changing the number of bits m of, the reference clock is divided by a more optimal dividing ratio,
It is possible to obtain a divided clock with the desired frequency.

In the conventional variable frequency dividers 100 and 104, the change amount of the frequency of the divided clock when the set value N is changed by 1 is f _sys / (2 × (N + 1)) − f _sys / ( 2 x ((N +
1) +1)) = f _sys / (2 × (N + 2) × (N + 1)). That is, by changing the set value N by 1,
Since the frequency of the divided clock changes depending on the set value N, it is difficult to adjust the frequency of the divided clock.

On the other hand, in the variable frequency divider 10 according to the first aspect of the present invention, when the set value R is changed by one, the change amount of the frequency of the divided clock is f _sys × (R + 1) / 2 ^{j + m + 1-} _fsys * R / ^{2j + m + 1} = _fsys / ^{2j + m + 1} . That is, by changing the set value R by 1,
Since the frequency of the divided clock is changed by a predetermined value (fixed value) that is not related to the cumulative value R, the conventional variable frequency divider 10
It is obvious that the frequency of the divided clock can be adjusted more easily than 0 and 104, and the frequency of the divided clock can be adjusted more finely as the number of bits m of the accumulator 16 is increased. Is.

For example, as described in the description of the prior art, when 38400 bps is used as the baud rate obtained by dividing the divided clock into 1/16, when the reference clock frequency is 8 MHz, the required divided frequency is obtained. The ratio is 13.02. According to the variable frequency divider 10 of the first aspect of the present invention, for example, the bit number m of the accumulator 16 is 7 bits, the set value R is 20 (decimal number), and the bit 0 of the count signal of the counter 18 is divided. If it is selected as the frequency clock, the frequency division ratio is frequency division ratio = 2 ^{j + m + 1} /R=20+7+1/20=12.8. Therefore, the error in the frequency of the divided clock generated with respect to the required frequency of the divided clock, that is, the error in the frequency of the generated baud rate can be 1.7%.

Next, a 3-bit up-counter and a 5-bit cumulative adder are used as the counter 18 and the accumulator 16, respectively, and the selector 20 is used as a divided clock.
Assuming that bit 0 of the count signal is selected by and the register 14 is set to "01011 (binary number)" as the set value R, the operation of the variable frequency divider 10 according to the first aspect of the present invention will be described with reference to FIG. A description will be given with reference to (a) and (b).

3 (a) and 3 (b) show the continuous display of the variable frequency divider 10 in a divided manner: (reference clock number): (count signal of counter) _ (cumulative adder) The state of the count signal from the reference clock 0 to the reference clock 68 and the cumulative addition value are shown in the form of (cumulative addition value). The count signal and the cumulative added value are displayed in binary numbers, and the right side is the lower bit and the left side is the higher bit.

As described above, the cumulative adder 16 cumulatively adds the set value R for each reference clock. As shown in the figure, for example, the cumulative addition value at the reference clock 0 is set to '00.
000 ”, the cumulative addition value in the reference clock 1 becomes“ 01011 ”, and similarly, in the same manner,“ 10110 ”for the reference clock 2 and“ 00001 ”for the reference clock 3.
Becomes The same applies to the reference clock 4 and thereafter.

When the cumulative addition value becomes '00001' at the reference clock 3, the carry signal is output from the cumulative adder 16 to the counter 18, and the count signal of the counter 18 is incremented by one. That is, the count signal output from the counter 18 becomes "001", and the divided clock is inverted. After that, the above operation is repeated,
As shown in FIGS. 3A and 3B, reference clocks 3, 6, 9, 12, 15, 18, 21, 21, 24, 27, 3
At 0, that is, every 3 reference clocks, the count signal of the counter 18 similarly increases by 1 and the divided clock is inverted.

In the reference clock 32, the cumulative addition value becomes "00000", and the divided clock, that is, bit 0 of the count signal is inverted by 2 reference clocks. This is because the bit number m of the set value is 5 bits, that is, the accumulator 16
Is 32 reference clocks and the set value R is' 010
11 ', that is, 11 (decimal number), so 32/1
This is because 1 = 2 and the remainder is 10, and the carry signal is output from the accumulator 16 every 2 or 3 reference clocks. This also applies to the reference clock 64, and thereafter, is repeated every 32 reference clocks.

Here, the frequency division ratio in this embodiment is the frequency division ratio = 2 ^{j + m + 1} / R = 64/11. As shown in FIGS. 3A and 3B, according to the variable frequency divider 10 of the first aspect of the present invention, the divided clock may not have the duty of 50%, but the value after the decimal point is a value. It becomes possible to divide the reference clock by a numerical value having.

As described above, the overflow signal output from the accumulator 16 is equal to one reference clock cycle (no matter how many bits m and the set value R of the accumulator 16 are). = 1 / f _sys ). Further, as already described in the description of the prior art, the reference clock tends to be a high-speed clock, and therefore its cycle tends to be short. In serial communication, the baud rate, that is, the frequency of the divided clock, Accuracy is strictly required, but bias in duty is not strictly required. Therefore, it goes without saying that the deviation of the duty of the divided clock does not pose any problem in practical use.

Next, FIGS. 4 and 5 are block diagrams of an embodiment of the variable frequency divider of the second aspect of the present invention. The variable frequency divider 48 is the variable frequency divider 10 according to the first aspect of the present invention, and further includes an up-counter 50, a coincidence detector 52, and a switch 54 shown in the conventional variable frequency divider 100 of FIG. The variable frequency divider 56 corresponds to the first embodiment of the present invention.
Since the variable frequency divider 10 of the aspect further includes the down counter 58 and the zero detector 60 shown in the conventional variable frequency divider 104 of FIG. 15 and the switch 54,
The same components are designated by the same reference numerals, and detailed description thereof will be omitted.

That is, the variable frequency divider 48 has the function of the variable frequency divider 10 of the first aspect of the present invention and the function of the conventional variable frequency divider 100 shown in FIG. Divider 56
1 is a function of the variable frequency divider 10 according to the first embodiment of the present invention, and FIG.
5 has the function of the conventional variable frequency divider 104, and both functions can be switched and used by the switching signal input to the switch 54.

As described above, in the variable frequency divider 10 according to the first aspect of the present invention, the obtained frequency division ratio is 2 ^{j + m + 1} / R.
And the frequency of the obtained _divided clock is f _sys × R /
2 ^{j + m + 1} , and the amount of change in the frequency of the divided clock when the set value R is changed by 1 is f _sys / 2 ^{j + m + 1} .
For example, when the bit j of the count signal is 0 and the number of bits of the accumulator 16 is m = 8, 0 ≦ setting value R ≦ 255 (= 2 ⁸ −1)
Then, the obtained division ratio is 2,512 / 255, ...,
256 and 512, and the obtained frequency of the divided clock is f _sys / 2,255 × f _sys / 512, ..., F _sys /
256, f _sys / 512.

On the other hand, in the conventional variable frequency dividers 100 and 104, the frequency division ratio obtained is 2 × (N + 1) and the frequency of the frequency division clock obtained is f _sys × (N + 1) / 2, which is set. When the value N is changed by one, the change in frequency of the divided clock is f _sys / (2 × (N + 2) × (N +
1)). Similarly, when 0 ≦ setting value N ≦ 255, the obtained division ratios are 2, 4, ..., 510, 512, and the obtained divided clock frequencies are f _sys / 2, f
_sys / 4, ..., F _sys / 510, f _sys / 512.

That is, the variable frequency divider 10 according to the first aspect of the present invention.
, The change in frequency of the divided clock is the set value R
It is always constant regardless of the conventional variable frequency divider 10
Compared with 0 and 104, it has an advantage that the frequency of the divided clock can be easily adjusted even at high frequencies. On the other hand, in the conventional variable frequency dividers 100 and 104, the smaller the set value N is, that is, the higher the frequency of the divided clock is, the larger the amount of change is, which is difficult to adjust. On the other hand, the larger the set value N, that is, the lower the frequency of the divided clock,
There is an advantage that the amount of change in the frequency of the divided clock is also small and fine adjustment is possible.

In other words, although the variable frequency divider 10 according to the first aspect of the present invention and the conventional variable frequency dividers 100 and 104 have a common frequency division ratio (frequency of the frequency division clock), Since there are frequency division ratios obtained only by the respective variable frequency dividers, by combining these variable frequency dividers, it is possible to obtain a highly accurate frequency division clock in a wider frequency range. That is, the variable frequency dividers 48 and 56 of the second aspect of the present invention are the variable frequency divider 10 of the first aspect of the present invention and the conventional variable frequency dividers 100 and 104.
Since it has both the functions of and, the frequency of the divided clock can be adjusted more easily at both the high frequency and the low frequency.

Next, FIG. 6 is a block diagram of an embodiment of the variable frequency divider of the third aspect of the present invention. This variable frequency divider 6
2 is the function of the variable frequency divider 10 according to the first aspect of the present invention (hereinafter referred to as the first mode) and the function of the conventional variable frequency divider 104 shown in FIG. 15 without increasing the circuit scale. In the variable frequency divider 10 according to the first aspect of the present invention, which has both functions (hereinafter, referred to as a second mode),
Further, since it has the first switching device 64, the second switching device 54, and the detector 66, the same components are designated by the same reference numerals, and detailed description thereof will be omitted.

In the illustrated example, the variable frequency divider 6 having both the function of the variable frequency divider 10 according to the first aspect of the present invention and the function of the conventional variable frequency divider 104 shown in FIG.
2 is shown, the variable frequency divider of the third aspect of the present invention is not limited to this, and the function of the variable frequency divider 10 of the first aspect of the present invention and the conventional frequency divider shown in FIG. It goes without saying that a variable frequency divider having both functions of the variable frequency divider 100 can be similarly configured.

That is, the detector 66 receives the accumulated signal (cumulative value) output from the accumulator 16, and the detector 6
A detection signal is output from 6. In addition, the first switching device 6
4, a set value output from the register 14, a detection signal output from the detector 66, and a switching signal for switching between the first mode and the second mode are input, and the output signal is the accumulator 16 Entered in. The overflow signal output from the accumulator 16, the detection signal output from the detector 66, and the switching signal are input to the second switch 54, and the output signal is input to the counter 18. To be done.

Here, the detector 66 is used only in the second mode, and the zero detector 60 of the conventional variable frequency divider 104 shown in FIG. 15 or the conventional variable frequency divider shown in FIG. 14 is used. It corresponds to 100 coincidence detectors 52. That is, when the accumulator 16 is used as a down counter, the accumulation signal output from the accumulator 16 is input to the detector 66, and the accumulation signal output from the accumulator 16 that is cumulatively subtracted is input. Becomes '0', a detection signal corresponding to the zero detection signal output from the zero detector 60 is output.
When the accumulator 16 is used as an up counter, the accumulator signal output from the accumulator 16 and the set value output from the register 14 are input to the detector 66.
When the accumulated signal output from the accumulator 16 that is cumulatively added reaches the set value output from the register 14, the detection signal corresponding to the coincidence detection signal output from the coincidence detector 52 is output.

The first switch 64 selects and outputs the set value and the predetermined value output from the register 14 according to the detection signal and the switch signal output from the detector 66. That is, when the first mode is selected by the switching signal, the set value output from the register 14 is output from the first switch 64 as the value accumulated by the accumulator 16. On the other hand, when the second mode is selected by the switching signal and the accumulator 16 is used as the down counter, when the detection signal is in the active state, the first switching is performed as the initial value set in the accumulator 16. The set value output from the register 14 is output from the device 64, and conversely, when the detection signal is inactive, a predetermined value is output as the value counted down by the accumulator 16.

When the second mode is selected by the switching signal and the accumulator 16 is used as an up counter, the value counted up by the accumulator 16 is:
A predetermined value is output from the first switch 64. The predetermined value output from the first switch 64 is not particularly limited, but in order to realize the functions of the up counter 50 and the down counter 58 of the conventional variable frequency dividers 100 and 104, It is preferably +1 'or'-1'.

Further, the second switching device 54 selectively outputs the overflow signal output from the accumulator 16 and the detection signal output from the detector 66 according to the switching signal. That is, when the first mode is selected by the switching signal, the overflow signal output from the accumulator 16 is output from the second switching unit 54. On the other hand, when the second mode is selected by the switching signal, the detection signal output from the detector 66 is output from the second switching unit 54.

As will be described later, the first switching device 64
When the predetermined value output by the above is represented by a negative expression such as 2's complement, the inverted signal of the overflow signal output by the accumulator 16 is used instead of the detection signal output by the detector 66. Sometimes possible. In this case, the circuit scale of the second switch 54 can be further reduced, which is more preferable. Next, a more preferable configuration of the variable frequency divider 62 of the third aspect of the present invention will be described by taking as an example the case where the variable frequency divider 10 of the first aspect of the present invention and the conventional variable frequency divider 104 are combined. explain.

First, FIG. 7 is a block diagram of another embodiment of the variable frequency divider according to the first aspect of the present invention. This block diagram shows the accumulator 16 in more detail in the block diagram of the variable frequency divider 10 according to the first embodiment of the present invention shown in FIG. That is, the accumulator 16 includes a register 68 and an adder 70 that adds the set value output from the register 14 and the accumulation signal output from the register 68 and outputs the added value to the register 68.

FIG. 17 is a block diagram of another example of the conventional variable frequency divider. This block diagram illustrates the down counter 58 in more detail in the block diagram of the conventional variable frequency divider 104 shown in FIG. That is, the down counter 58 registers the register 68, the decrementer (subtractor) 72 that subtracts “1” from the accumulated signal output from the register 68, and the zero detection signal output from the zero detector 60. 14 and a selector 73 that selectively outputs the output value of the decrementer 72 to the register 68.

FIG. 8 shows the first embodiment of the present invention shown in FIG.
FIG. 18 is a block diagram of a variable frequency divider configured by combining the variable frequency divider 10 of the aspect and the conventional variable frequency divider 104 shown in FIG. 17. The variable frequency divider 74 outputs a reference clock generator 12 which outputs a reference clock, a register 14 which outputs a set value set by the CPU 22, a set value output from the register 14 and a register 68. An adder 70 for adding the accumulated signal and a register 6
Decrementer 72 for subtracting the accumulated signal output from 8
A selector 76 for selectively outputting any one of the set value output from the register 14, the output signal of the adder 70 and the output signal of the decrementer 72, the register 68 for holding the output signal of the selector 76, and the register 68. A zero detector 60 that detects that the output accumulated signal has become "0", or a carry signal that is output from the register 68 or a zero detection signal that is output from the zero detector 60 is selected and output. And a counter 18 that divides the output signal of the selector 80.

In the variable frequency divider 74, the register 14 of the conventional variable frequency divider 104 and the register 14 of the variable frequency divider 10 of the first aspect of the present invention are shared, and the conventional variable frequency divider 104 is used. The toggle flip-flop 102 and the counter 18 of the variable frequency divider 10 according to the first aspect of the present invention are shared, and the register 68 configuring the down counter 58 of the conventional variable frequency divider 104, and the first aspect of the present invention. It is shared with the register 68 which constitutes the accumulator 16 of the variable frequency divider 10 of the aspect. Thus, the variable frequency divider 10 according to the first aspect of the present invention
The circuit scale of the variable frequency divider 74 can be reduced by sharing the above-mentioned structural elements with those of the conventional variable frequency divider 104.

Further, FIG. 9 shows a variable frequency divider 74 shown in FIG.
4 is a partial block diagram in which a part of FIG. In the variable frequency divider 74 shown in FIG. 8, the set value output from the register 14 and directly input to the selector 76 is the set value output from the register 14 in the second mode.
It is a route for setting (loading) to 8. The setting value is set in the register 68 through this route.
Only when the accumulated signal output from the register 68 becomes "0".

In this case, since "0" is input to one input terminal of the adder 70, the output signal of the adder 70 becomes equal to the set value output from the register 14. Therefore, as shown in the variable frequency divider 82 of FIG.
It is possible to omit a path for setting a more output set value in the register 68, and further reduce the number of input terminals of the selector 76 to two. The variable frequency divider 8
It is preferable to initialize the accumulated signal output from the register 68 to "0" before starting the operation of 2.

Further, FIG. 10 shows the variable frequency divider 8 shown in FIG.
2 is a partial block diagram in which a part of 2 is changed. FIG. The decrementer 72 subtracts "1" from the accumulated signal output from the register 68, and can be realized by adding "-1" to the output signal of the register 68. Further, in the variable frequency divider 82 shown in FIG. 9, only one of the output signal of the adder 70 and the output signal of the decrementer 72 is used by the selector 76, so that the variable frequency divider 84 of FIG. As shown, the decrementer 72 can be eliminated.

Further, FIG. 11 is a partial block diagram in which a part of the variable frequency divider 84 shown in FIG. 10 is modified. Figure 10
In the variable frequency divider 84 of FIG. 11, since “−1” input to the selector 76 is a constant, and “−1” becomes “111 ... 111” (all 1) in the two's complement representation, As shown in the variable frequency divider 88 of FIG.
Instead of using 6, the OR gate 90 can be used, and the circuit scale can be further reduced. In addition,
The NOR gate 92 that controls the OR gate 90 receives the detection signal and the switching signal.

Next, FIG. 12 shows an accumulator 16, a counter 18, and a detector 6 which constitute the variable frequency divider of the third aspect of the present invention.
6 shows a configuration circuit diagram of one embodiment of the first, second and second switching devices 64, 54. The accumulator 16 and the counter 18
2 is the same as the accumulator 16 and the counter 18 constituting the variable frequency divider 10 of the first aspect of the present invention shown in FIG. 2 except that the number of bits is different, and therefore, the same constituent elements are the same. Reference numerals are given and detailed description thereof is omitted.

In the figure, the detector 66 corresponds to the zero detector 60 which constitutes the conventional variable frequency divider 104 shown in FIG. 15, and is constituted by a NOR gate 94. The NOR gate 94 inputs the accumulation signal output from the flip-flop 34 constituting each cumulative addition unit 24, and the NOR gate 94 outputs the detection signal (zero detection signal).

Further, the first switching device 64 has the OR gate 9
0 and a NOR gate 92. The set value output from the register 14 is input to one input terminal of the OR gate 90, and N is commonly input to the other input terminal.
The output signal of the OR gate 92 is input to the OR gate 90.
The output terminals of are connected to the input terminals of the cumulative addition unit 24, respectively. Further, at the input end of the NOR gate 92,
The detection signal and the switching signal are input.

Further, the second switch 54 is an XNOR
(Exclusive NOR) gate 96.
The carry signal output from the cumulative addition unit 24a for the most significant bit is input to one input end of the XNOR gate 96, and the switching signal is input to the other input end of the XNOR gate 96.
The output end of the OR gate 96 is input to the least significant bit counter unit 40a. The accumulator 16, the counter 18, the detector 66, and the first and second switchers 64 and 54, which constitute the variable frequency divider of the third aspect of the present invention, are configured as described above, for example.

Next, the operation of this variable frequency divider will be described. First, when the first mode is selected by the switching signal, that is, when a high level is input as the switching signal in the illustrated example, the NOR gate 92 that configures the first switching device 64 regardless of the state of the detection signal. Output signal becomes low level, and the set value output from the register 14 is directly output from each OR gate 90.

Further, the XNO which constitutes the second switch 54.
The carry signal output from the cumulative addition unit 24a for the most significant bit is output from the R gate 96 as it is. That is, when the first mode is selected by the switching signal, this variable frequency divider has the same configuration as the variable frequency divider 10 of the first aspect of the present invention, and the variable frequency divider of the first aspect of the present invention. Since the operation is the same as that of 10, the description of the operation is omitted.

Next, when the second mode is selected by the switching signal, that is, when a low level is input as the switching signal in the illustrated example, the output signal of the NOR gate 92 constituting the first switching device 64. Is determined according to the state of the detection signal. When the detection signal is in the active state, that is, when it is at the high level in the illustrated example, the output signal of the NOR gate 92 becomes the low level, and the set value output from the register 14 is output from each OR gate 90, and the accumulated value is accumulated. The set value output from the register 14 is set (loaded) in the calculator 16.

When the detection signal is low level, the first
The output signal of the NOR gate 92 that constitutes the switching device 64 becomes high level, and the high level is output from each OR gate 90. That is, when the detection signal is at a low level, "-1" in 2's complement representation is input to the accumulator 16, and "-1" is cumulatively added by the cumulative adder 16 to perform subtraction. And the accumulator 16 is used as a down counter.

Further, the XNO which constitutes the second switch 54
The R gate 96 outputs an inverted signal of the carry signal output from the cumulative addition unit 24a for the most significant bit. When the second mode is selected, the circuit may be configured so that the detection signal output from the detector 66 is selectively output from the second switch 54, but in the case of the circuit configuration of this embodiment, Two-complement expression "-1", that is, "111 ...
Since 111 '(all 1s) are cumulatively added, the carry signal is always in the active state except when the accumulated signal (cumulative added value) output from the flip-flop 34 is' 000 ... 000' (all 0). The signal is output. That is, since the inverted signal of the carry signal becomes active at the same timing as the detection signal output from the detector 66, the inverted signal of the carry signal is used instead of the detection signal output from the detector 66. It can be used and the circuit scale can be further reduced.

That is, in the second mode, the register 14
A set value is set by the CPU 22, and the accumulation signal output from the flip-flop 34 forming the accumulator 16 is initialized to "0" before the operation is started, for example, by a reset signal. At this time, when the detection signal output from the detector 66 becomes a high level which is an active state, the set value output from the register 14 is input to the accumulator 16 through the first switch 64, and the accumulator 16 accumulates. The carry signal output from the calculator 16 is low level, that is,
The output signal of the second switch 54 becomes the high level which is the active state.

Then, in synchronization with the next rising edge of the reference clock, the flip-flop 34 which constitutes the accumulator 16
When the set value output from the register 14 is set in
The detection signal output from the detector 66 becomes a low level, which is an inactive state, and all the input terminals of the accumulator 16 are at a high level through the first switch 64, that is, in the 2's complement representation. 1'is input, the carry signal output from the accumulator 16 is at a high level, that is, the output signal of the second switch 54 is at a low level which is an inactive state, and is output from the counter 18. The count signal is not counted up (when the set value is other than zero).

Then, from the next reference clock, the accumulator 1
The output signals of the flip-flops 34 constituting 6 are counted down one by one in synchronization with the rising edge of the reference clock from the set value to “0”. Flip flop 3
When all the output signals of 4 become "0", the above-described operation is repeated, and the count signal output from the counter 18 counts up every time the output signal of the second switch 54 becomes the active state of high level. To be done.

As described above, according to this variable frequency divider, when the first mode is selected by the switching signal, the first mode of the present invention can be obtained.
Can be operated in the same manner as the variable frequency divider 10 of the aspect,
When the second mode is selected by the switching signal, it can be operated in the same manner as the conventional variable frequency divider 104. Also,
This variable frequency divider uses the accumulator 16 to realize the down counter 58, which is a component of the conventional variable frequency divider 104, without using the decrementer 72.
There is an advantage that an increase in circuit scale can be suppressed to an extremely small level.

For example, as in this embodiment, the accumulator 16
When the number of bits is 8 bits, the variable frequency divider 62 according to the third aspect of the present invention is different from the variable frequency divider 56 according to the second aspect of the present invention in that it has a decrementer 72, eight selectors 76, and a selector. 80 is reduced and, conversely, 8 OR gates 90, X
A NOR gate 96 and a NOR gate 92 are added. The reduced number of gates is approximately 80 gates,
The circuit scale of the variable frequency divider 56 of the second aspect of the present invention is about 25.
Since it is considered to have about 0 gates, the variable frequency divider 62 of the third aspect of the present invention was able to reduce the circuit scale by about 30% as compared with the variable frequency divider 56 of the second aspect of the present invention.

In the variable frequency divider of the present invention, the switching signal may be input from the outside, may be held by using a flip-flop, or may be set by a switch. May be.
Further, as described above, the frequency of the divided clock gradually becomes higher and the divided ratio tends to become smaller, that is, the switching signal is set to the high level to select the first mode, and the register 14 is selected. Since the set value set to 1 is also a large value, for example, one of the upper bits of the set value output from the register 14 can be used as the switching signal.

Here, FIG. 13 is a configuration circuit diagram of another embodiment of the variable frequency divider of the third aspect of the present invention. This variable frequency divider uses the most significant bit of the set value output from the register 14, that is, bit 7 as a switching signal, as compared with the variable frequency divider according to the third aspect of the present invention shown in FIG. The same components are denoted by the same reference numerals, and detailed description thereof will be omitted. In the figure, the full adder 32 and the half adder 38 are shown as blocks for simplification of the drawing.

As described above, by using the upper bits of the set value output from the register 14 as the switching signal, the first mode and the second mode can be effectively used and the switching signal can be set. External terminal,
There is an advantage that a storage element, a switch, etc. are unnecessary. When the most significant bit of the register 14 is used as the switching signal, the frequency division ratio obtained in the first mode is 2 ^{8 + 1} / R (however, 128 ≦ R ≦ 255), and
The frequency division ratio obtained in the mode is 2 × (N + 1) (where 0 ≦ R ≦ 127).

[0094]

As described above in detail, in the variable frequency divider of the present invention, the accumulator accumulates the set value for each reference clock, and the counter outputs the overflow signal output from the accumulator. By counting, the reference clock is frequency-divided to output the frequency-divided clock, and the frequency of the frequency-divided clock can be easily adjusted even at a high frequency as compared with the conventional variable frequency divider. Further, the variable frequency divider of the present invention has a small circuit scale and further has the function of the conventional variable frequency divider, so that the frequency division clock can be finely adjusted even at a low frequency. Therefore, according to the variable frequency divider of the present invention,
In addition to low-frequency support, by appropriately determining the bit number and setting value of the accumulator at high frequency, the reference clock can be divided by the division ratio of the value that has a value after the decimal point. Even if the reference clock or the communication speed is increased and the required frequency division ratio becomes smaller, the frequency division clock can be easily obtained with high accuracy in a programmable manner.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a variable frequency divider according to the first aspect of the present invention.

FIG. 2 is a configuration circuit diagram of an embodiment of an accumulator and a counter that constitute the variable frequency divider according to the first aspect of the present invention.

3 (a) and 3 (b) are both an example of a diagram showing a relationship between a reference clock, a count signal, and a cumulative addition value in the variable frequency divider according to the first aspect of the present invention.

FIG. 4 is a block diagram of an embodiment of a variable frequency divider according to the second aspect of the present invention.

FIG. 5 is a block diagram of another embodiment of the variable frequency divider according to the second aspect of the present invention.

FIG. 6 is a block diagram of an embodiment of a variable frequency divider according to the third aspect of the present invention.

FIG. 7 is a block diagram of another embodiment of the variable frequency divider according to the first aspect of the present invention.

FIG. 8 is a block diagram of another embodiment of the variable frequency divider according to the third aspect of the present invention.

FIG. 9 is a partial block diagram of an embodiment showing a modification of the variable frequency divider of the third aspect of the present invention in FIG.

FIG. 10 is a partial block diagram in which a part of the variable frequency divider of the third aspect of the present invention shown in FIG. 9 is modified.

11 is a partial block diagram in which a part of the variable frequency divider according to the third aspect of the present invention shown in FIG. 10 is modified.

FIG. 12 is a block diagram of an embodiment of an accumulator, a counter, a detector, and a first and a second switch, which constitute a variable frequency divider according to the third aspect of the present invention.

FIG. 13 is a block diagram of another embodiment of an accumulator, a counter, a detector, and first and second switchers which constitute the variable frequency divider of the third aspect of the present invention.

FIG. 14 is a block diagram of an example of a conventional variable frequency divider.

FIG. 15 is a block diagram of another example of a conventional variable frequency divider.

FIG. 16 is an example timing chart showing an operation of a conventional variable frequency divider.

FIG. 17 is a block diagram of still another example of the conventional variable frequency divider.

[Explanation of symbols]

10, 48, 56, 62, 74, 82, 84, 88, 1
00, 104 Variable frequency divider 12 Reference clock generator 14, 68 Register 16 Accumulator 18, 50, 58 Counter 20, 73, 76, 80 Selector 22 CPU (central processing unit) 24, 24a, 24b Cumulative addition unit 26 , 28, 42 EXOR gate 30 AND-OR composite gate 32, 38, 70 adder 34, 46 flip-flop 36, 44 AND gate 40, 40a, 40b counter unit 52, 60, 66 detector 54, 64 switch 72 decrementer (Subtractor) 90 OR gate 92, 94 NOR gate 96 XNOR gate 102 Toggle flip-flop

Claims (7)

[Claims] 1. A register for outputting a set set value,
An accumulator of at least 1 bit that accumulates the set value output from the register and outputs an overflow signal and a overflow signal output from the accumulator are counted for each reference clock of a predetermined frequency. And a counter for outputting a count signal of at least 1 bit. 2. The variable frequency divider according to claim 1, further comprising a second count signal reset by a detection signal and outputting at least a 1-bit second count signal counted for each of the reference clocks. And a detector that outputs the detection signal when the second counter counts the count value corresponding to the set value output from the register, and the overflow signal output from the accumulator. A variable frequency divider comprising: a switch that selectively outputs a detection signal output from the detector to the counter according to a switch signal. 3. A register for outputting a set set value,
A first switch that selectively outputs a set value and a predetermined value output from the register according to the switch signal and the detection signal, and an output signal of the first switch that accumulates the output signal of the first switch for each reference clock of a predetermined frequency. An accumulator of at least 1 bit which outputs a summation signal and an overflow signal, and the detection signal when the accumulator accumulates a count value corresponding to the set value output from the register. A detector for outputting, a second switch for selectively outputting the overflow signal output from the accumulator and the detection signal output from the detector in response to the switch signal, and the second switch. A variable frequency divider comprising: a counter that counts the output signal of the switch and outputs a count signal of at least 1 bit. 4. The variable frequency divider according to claim 3, wherein the predetermined value output from the first switch is 1 or -1. 5. The second switch, instead of selectively outputting the overflow signal output from the accumulator and the detection signal output from the detector in response to the switch signal,
The variable frequency divider according to claim 3, wherein the polarity of the overflow signal output from the accumulator is inverted according to the switching signal. 6. The variable frequency divider according to claim 3, wherein the switching signal is one of upper bits of a set value output from the register. 7. The variable frequency divider according to claim 1, further comprising: when the count signal of at least 1 bit is a count signal of 2 bits or more, A variable frequency divider comprising a selector that selectively outputs 1 bit as a divided clock according to a selection signal.