JPH08340243A - Bias circuit - Google Patents
Bias circuitInfo
- Publication number
- JPH08340243A JPH08340243A JP7147133A JP14713395A JPH08340243A JP H08340243 A JPH08340243 A JP H08340243A JP 7147133 A JP7147133 A JP 7147133A JP 14713395 A JP14713395 A JP 14713395A JP H08340243 A JPH08340243 A JP H08340243A
- Authority
- JP
- Japan
- Prior art keywords
- current
- circuit
- current mirror
- supplied
- circuit block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はバイアス回路に係わり、
特にIC内の複数の回路ブロックにおいて相対精度の良
いカレントミラーを実現するバイアス回路に関するもの
である。BACKGROUND OF THE INVENTION The present invention relates to a bias circuit,
In particular, the present invention relates to a bias circuit that realizes a current mirror with high relative accuracy in a plurality of circuit blocks in an IC.
【0002】[0002]
【従来の技術】従来、複数の回路ブロックにおいて同一
の電流値のバイアスを供給するバイアス回路としては図
2に示す構成がとられている。すなわち、図2に示すよ
うに、回路ブロック1の内に形成したバイアス回路のバ
イアス電圧を、他の回路ブロック2,3,4…に供給
し、回路ブロック1と同様な構成のカレントミラーによ
り、各回路ブロック内でバイアス電流を発生させてい
る。2. Description of the Related Art Conventionally, a configuration shown in FIG. 2 has been adopted as a bias circuit for supplying a bias of the same current value in a plurality of circuit blocks. That is, as shown in FIG. 2, the bias voltage of the bias circuit formed in the circuit block 1 is supplied to the other circuit blocks 2, 3, 4, ... Bias current is generated in each circuit block.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、上記従
来のバイアス回路ではバイアス電圧を供給する配線16
や電源配線6の配線抵抗と、配線を流れる電流とにより
電圧降下が生じるため、IC上の各回路ブロックの配置
や回路ブロック間の配線抵抗というレイアウト的要素で
各回路ブロックのバイアス電流の相対精度が悪化すると
いう問題があった。However, in the above-mentioned conventional bias circuit, the wiring 16 for supplying the bias voltage is used.
Since a voltage drop occurs due to the wiring resistance of the power supply wiring 6 and the wiring resistance of the power supply wiring 6, the relative accuracy of the bias current of each circuit block is determined by the layout element such as the layout of each circuit block on the IC and the wiring resistance between the circuit blocks. There was a problem that was worse.
【0004】本発明の目的は、回路ブロック間の配線抵
抗と、回路ブロック内でミラーする電流値に影響されな
い、相対精度の高いバイアス回路を実現することにあ
る。An object of the present invention is to realize a bias circuit with high relative accuracy, which is not affected by the wiring resistance between circuit blocks and the current value mirrored in the circuit block.
【0005】[0005]
【課題を解決するための手段】本発明のバイアス回路
は、第1のカレントミラー回路を有する一の回路ブロッ
クと、該第1のカレントミラー回路の出力電流が供給さ
れる第2のカレントミラー回路をそれぞれ有する複数の
他の回路ブロックとを備えたものである。A bias circuit according to the present invention comprises a circuit block having a first current mirror circuit and a second current mirror circuit to which an output current of the first current mirror circuit is supplied. And a plurality of other circuit blocks each having
【0006】[0006]
【作用】本発明では一の回路ブロック内のカレントミラ
ー回路の出力を他の回路ブロックに供給するため、回路
ブロック間の配線抵抗の値に依存しない電流を供給出来
る。According to the present invention, since the output of the current mirror circuit in one circuit block is supplied to another circuit block, a current that does not depend on the value of the wiring resistance between the circuit blocks can be supplied.
【0007】また、カレントミラー回路を他の複数の回
路ブロック内のそれぞれに構成することにより、カレン
トミラーを構成する素子をバイアスするバイアスライン
の配線抵抗の影響を極力小さくすることが可能となり、
相対精度の良いカレントミラーを実現出来る。Further, by configuring the current mirror circuit in each of the other plurality of circuit blocks, it becomes possible to minimize the influence of the wiring resistance of the bias line for biasing the elements constituting the current mirror.
A current mirror with high relative accuracy can be realized.
【0008】なお、本発明において、他の回路ブロック
のカレントミラー回路にバイポーラトランジスタを使用
すれば、絶縁ゲート型トランジスタを使用した場合に比
べ、出力インピーダンスの高いカレントミラー回路を構
成することができる。また、カレントミラーを構成する
バイポーラトランジスタのベース電流を絶縁ゲート型ト
ランジスタで供給すれば、各回路ブロックでのミラーす
る電流値に影響されない相対精度の高いバイアスを実現
出来る。In the present invention, if a bipolar transistor is used for the current mirror circuit of another circuit block, a current mirror circuit having a higher output impedance can be constructed as compared with the case where an insulated gate transistor is used. Further, by supplying the base current of the bipolar transistor forming the current mirror by the insulated gate transistor, it is possible to realize a bias with high relative accuracy that is not affected by the current value of the mirror in each circuit block.
【0009】[0009]
【実施例】以下、本発明の実施例について図面を用いて
詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
【0010】図1は本発明のバイアス回路の一実施例を
示す回路構成図であり、1は他の回路ブロックに電流を
供給するカレントミラー回路を内蔵する回路ブロック、
2,3,4は回路ブロック1により電流が供給される他
の回路ブロック、5は第1の電源ライン、6は第2の電
源ライン、7はミラーする電流の元となる電流源、8,
9,10は他の回路ブロック2,3,4へ電流を供給す
るカレントミラーを構成するバイポーラトランジスタ、
11は回路ブロックに供給された電流をミラーするため
のバイアスを発生させるためのバイポーラトランジス
タ、13,14,15は回路ブロック内の回路にミラー
した電流を供給するためのバイポーラトランジスタ、1
2はカレントミラーを構成するバイポーラトランジスタ
のベース電流を供給する絶縁ゲート型トランジスタたる
MOSトランジスタである。FIG. 1 is a circuit configuration diagram showing an embodiment of a bias circuit of the present invention, in which 1 is a circuit block containing a current mirror circuit for supplying a current to another circuit block,
2, 3, 4 are other circuit blocks to which current is supplied by the circuit block 1, 5 is a first power supply line, 6 is a second power supply line, 7 is a current source which is a source of mirrored current, 8,
9 and 10 are bipolar transistors forming a current mirror that supplies current to the other circuit blocks 2, 3 and 4.
Reference numeral 11 is a bipolar transistor for generating a bias for mirroring the current supplied to the circuit block, 13, 14, 15 are bipolar transistors for supplying the mirrored current to the circuits in the circuit block, 1
Reference numeral 2 is a MOS transistor which is an insulated gate type transistor which supplies a base current of a bipolar transistor forming a current mirror.
【0011】電流源7より供給された電流は回路ブロッ
ク1内のカレントミラー回路により、他の回路ブロック
2,3,4に供給される。ここでは、カレントミラーを
構成するバイポーラトランジスタ8,9,10のベース
電流をバイポーラトランジスタ17により供給している
がこのベース電流供給トランジスタにMOSトランジス
タを使用しても良い。その場合、回路ブロック1のカレ
ントミラー回路の出力電流はベース電流を供給するトラ
ンジスタのベース電流の影響を受けなくなる。また、電
流源7は、ある電圧との間に抵抗を挿入しただけの簡単
なものから、外部での調整を可能とする可変電流源な
ど、複雑な形式のものまで使用可能であり、その構成を
答わない。The current supplied from the current source 7 is supplied to the other circuit blocks 2, 3 and 4 by the current mirror circuit in the circuit block 1. Here, the base currents of the bipolar transistors 8, 9 and 10 forming the current mirror are supplied by the bipolar transistor 17, but a MOS transistor may be used as the base current supply transistor. In that case, the output current of the current mirror circuit of the circuit block 1 is not affected by the base current of the transistor that supplies the base current. Further, the current source 7 can be used from a simple type in which a resistor is inserted between a certain voltage and a complex type such as a variable current source that can be adjusted externally. Don't answer.
【0012】回路ブロック1でミラーされた電流は他の
回路ブロック2,3,4…へ供給される。各回路ブロッ
ク2,3,4…へ供給された電流は、それぞれの回路ブ
ロックでミラーされ、各回路ブロック内の回路に使用さ
れる。例えば、トランジスタ8のコレクタから回路ブロ
ック2へ供給された電流はトランジスタ11によりカレ
ントミラーのバイアス電圧へと変換され、カレントミラ
ーを構成する他のバイポーラトランジスタ13,14,
15…のベースに電圧供給される。また、このカレント
ミラーを構成するバイポーラトランジスタのベース電流
はMOSトランジスタ12により供給される。回路ブロ
ック1及び2に示したカレントミラーを構成するトラン
ジスタをバイポーラトランジスタで構成しているのはM
OSトランジスタを使用するのに比べ、出力インピーダ
ンスを大きくすることが出来るここと、一般的に同一面
積を占めるMOSトランジスタより相対精度を良くする
ことが出来るためである。また、カレントミラーを構成
するバイポーラトランジスタのエミッタと電源との間に
抵抗を挿入しているのは、カレントミラーの出力インピ
ーダンスをさらに高め、また相対精度をさらに良くする
ためであるが、抵抗を挿入するかどうか、また、抵抗の
値をいくらにするかは、電流の精度やミラーを構成する
バイポーラトランジスタのコレクタ電位の取りうる範囲
や、電流のノイズスペックなどにより決定される。カレ
ントミラーを構成するトランジスタ11,13,14,
15…のベース電流はMOSトランジスタ12により供
給される。このため、複数の回路ブロック2,3,4…
のそれぞれでカレントミラーされる電流値はそれぞれの
回路ブロックのカレントミラー回路のミラーするトラン
ジスタの数の影響を受けない。たとえば、回路ブロック
2,3,4が、gm アンプを用いたフィルターであり、
カレントミラーの出力電流が、gm アンプのgmを決定
する電流源に使われている場合を考えてみる。この場
合、各フィルターに求められる特性が異なれば、当然、
カレントミラーでミラーされる電流値も異なる場合が多
い。この時カレントミラーを構成するバイポーラトラン
ジスタのベース電流をバイポーラトランジスタで供給し
ようとすると、そのトランジスタのベース電流により、
ミラーされる電流に誤差が発生する。したがって、電流
源7の値を調整してフィルターのfc を調整しようとし
た時、回路ブロック2,3,4…の特性がまったく同調
しては調整されなくなってしまう。The current mirrored in the circuit block 1 is supplied to the other circuit blocks 2, 3, 4 ... The current supplied to each circuit block 2, 3, 4 ... Is mirrored in each circuit block and used for the circuit in each circuit block. For example, the current supplied from the collector of the transistor 8 to the circuit block 2 is converted into the bias voltage of the current mirror by the transistor 11, and the other bipolar transistors 13, 14, which form the current mirror,
A voltage is supplied to the bases of 15 ... Further, the base current of the bipolar transistor forming the current mirror is supplied by the MOS transistor 12. The transistors forming the current mirror shown in the circuit blocks 1 and 2 are bipolar transistors.
This is because the relative accuracy can be improved compared to the case where the OS transistor is used and the case where the output impedance can be increased and the MOS transistor which generally occupies the same area. A resistor is inserted between the emitter of the bipolar transistor forming the current mirror and the power supply in order to further increase the output impedance of the current mirror and further improve the relative accuracy. Whether or not to set the resistance value is determined by the accuracy of the current, the range of the collector potential of the bipolar transistor forming the mirror, the noise specification of the current, and the like. Transistors 11, 13, 14 forming the current mirror,
The base current of 15 ... Is supplied by the MOS transistor 12. Therefore, the plurality of circuit blocks 2, 3, 4 ...
The current value of each of the current mirrors is not affected by the number of transistors to be mirrored in the current mirror circuit of each circuit block. For example, the circuit blocks 2, 3 and 4 are filters using a g m amplifier,
Consider the case where the output current of the current mirror is used as a current source that determines g m of the g m amplifier. In this case, if the characteristics required for each filter are different,
The current value mirrored by the current mirror often differs. At this time, if it is attempted to supply the base current of the bipolar transistor that constitutes the current mirror by the bipolar transistor, the base current of the transistor causes
There is an error in the mirrored current. Therefore, when the value of the current source 7 is adjusted to try to adjust the filter f c , the characteristics of the circuit blocks 2, 3, 4, ...
【0013】本発明によれば、カレントミラーを構成す
るバイポーラトランジスタのベース電流をMOSトラン
ジスタにより供給しているため、各回路ブロック2,
3,4…でのカレントミラーのミラー数によらず、各回
路ブロックのカレントミラーの電流値の相対精度を高く
することが可能となっている。According to the present invention, since the base current of the bipolar transistor forming the current mirror is supplied by the MOS transistor, each circuit block 2,
It is possible to increase the relative accuracy of the current value of the current mirror of each circuit block regardless of the number of current mirrors of 3, 4 ,.
【0014】[0014]
【発明の効果】以上説明したように、本発明によれば、
複数の回路ブロックのカレントミラーの値の相対精度を
高くすることが可能となる。これにより、たとえばgm
アンプを用いたフィルターに使用した場合、各フィルタ
ーの特性の相対精度を高くすることが可能となり、フィ
ルターのfc をgm アンプのバイアス電流により調整し
ようとした場合、各フィルターの特性を精度よく調整す
ることが可能となる。また、この回路を用いたICをレ
イアウトする場合、回路ブロック間の配線抵抗の影響を
受けないことから、レイアウト時の自由度が増し、レイ
アウト時間の短縮、及び性能の向上が可能となる。As described above, according to the present invention,
It is possible to increase the relative accuracy of the values of the current mirrors of a plurality of circuit blocks. This gives, for example, g m
When used in a filter that uses an amplifier, it is possible to increase the relative accuracy of the characteristics of each filter. If you try to adjust f c of the filter by the bias current of the g m amplifier, the characteristics of each filter will be accurate. It becomes possible to adjust. Further, when an IC using this circuit is laid out, it is not affected by the wiring resistance between the circuit blocks, so that the degree of freedom in layout is increased, the layout time can be shortened, and the performance can be improved.
【図1】本発明のバイアス回路の一実施例を示す回路構
成図である。FIG. 1 is a circuit configuration diagram showing an embodiment of a bias circuit of the present invention.
【図2】従来のバイアス回路の回路構成図である。FIG. 2 is a circuit configuration diagram of a conventional bias circuit.
1 第1の回路ブロック 2〜4 第2〜第4の回路ブロック 5 第1の電源ライン 6 第2の電源ライン 7 電流源 8〜10 第1のカレントミラーを構成するトランジス
タ 11,13〜15 第2のカレントミラーを構成するバ
イポーラトランジスタ 12 第2のカレントミラーを構成するMOSトランジ
スタ 16 バイアス電圧配線DESCRIPTION OF SYMBOLS 1 1st circuit block 2-4 4th 2nd-4th circuit block 5 1st power supply line 6 2nd power supply line 7 Current source 8-10 Transistor 11, 13-15 which comprises 1st current mirror Bipolar transistor 12 forming a current mirror 2 MOS transistor 16 forming a second current mirror 16 Bias voltage wiring
フロントページの続き (72)発明者 松野 靖司 東京都大田区下丸子3丁目30番2号 キヤ ノン株式会社内Front page continuation (72) Inventor Yasushi Matsuno 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.
Claims (2)
回路ブロックと、該第1のカレントミラー回路の出力電
流が供給される第2のカレントミラー回路をそれぞれ有
する複数の他の回路ブロックとを備えたバイアス回路。1. A circuit block having a first current mirror circuit, and a plurality of other circuit blocks each having a second current mirror circuit to which an output current of the first current mirror circuit is supplied. Bias circuit provided.
前記第2のカレントミラー回路は、電流をミラーするバ
イポーラトランジスタと、該バイポーラトランジスタの
ベース電流を供給する絶縁ゲート型トランジスタとを備
えてなるバイアス回路。2. The bias circuit according to claim 1, wherein
The second current mirror circuit is a bias circuit including a bipolar transistor that mirrors a current and an insulated gate transistor that supplies a base current of the bipolar transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7147133A JPH08340243A (en) | 1995-06-14 | 1995-06-14 | Bias circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7147133A JPH08340243A (en) | 1995-06-14 | 1995-06-14 | Bias circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08340243A true JPH08340243A (en) | 1996-12-24 |
Family
ID=15423317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7147133A Pending JPH08340243A (en) | 1995-06-14 | 1995-06-14 | Bias circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08340243A (en) |
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