JPH08327695A - Lsi test circuit - Google Patents

Abstract

PURPOSE: To obtain an LSI test circuit in which the operation of an arbitrary operating circuit in an LSI can be determined under a state where the LSI is built in an actual machine and the signal from an output terminal, which is not used during normal operation, is invariant. CONSTITUTION: The LSI test circuit comprises operating circuits 1, 2, 3 having different functions, delay circuits 4, 5, 6 having time lags similar to those of the operating circuits 1, 2, 3, selectors 7, 8, 9, 12 for selecting respective outputs, a gate processing circuit 11, and a circuit for controlling the selectors 7, 8, 9, 12 and a processing circuit 11. The selectors are controlled to select an arbitrary operating circuit and delay circuits for other operating circuits thus outputting a signal with same time lag as normal operation. Signal from an output terminal, which is not used during normal operation, can be prevented from varying by gating the signal through the processing circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for verifying the operation of an internal circuit of an LSI incorporated in a system for actual operation.

[0002]

2. Description of the Related Art In recent years, L has been incorporated in complicated systems.
There is a growing need to verify the operation of SI.

FIG. 3 shows an example of a conventional LSI test circuit, and its operation will be described with reference to this figure.

In FIG. 3, reference numeral 1 is an arithmetic circuit having an input signal and having a specific function, 2 is an arithmetic circuit having a function different from that of the arithmetic circuit 1, and 3 is a function different from the arithmetic circuits 1 and 2. A selector for switching between an input signal and an output signal of the arithmetic circuit 1, a selector for switching between an input signal and an output signal of the arithmetic circuit 2, and a selector 12 for switching between the output signals of the arithmetic circuits 1 and 2. Selector to switch,
Reference numeral 10 is a circuit that controls switching of the selectors 7, 8 and 12.

When verifying the operation of the arithmetic circuit 1 in the conventional circuit, the control circuit 10 operates so that the video signal is inputted from the input terminal A and the output of the arithmetic circuit 1 is outputted through the selector 12. Similarly, when verifying the operation of the arithmetic circuit 2, the control circuit 10 operates so that the selector 7 selects the input signal and outputs it through the selector 12. When verifying the operation of the arithmetic circuit 3, the selector 8 selects the input signal and outputs it.
Works.

However, although the outputs of the arithmetic circuits 1 and 2 and the output of the arithmetic circuit 3 are output from separate output terminals B and C in FIG. 1, the input of the selector 12 is increased by one input and the output of the arithmetic circuit 3 is increased. The output terminal may be shared by connecting to the end.

[0007]

However, in the above configuration, when outputting an output signal in which only a specific arithmetic circuit is operated, the delay time of the output signal is the output signal obtained by operating all arithmetic circuits. However, there is a problem in that it is not possible to verify the operation of an arbitrary partial arithmetic function of the LSI in a system incorporating the LSI because the delay time is different from the delay time.

Further, there is a problem that power consumption increases because an output signal of a certain arithmetic circuit is output to an output terminal which is not used during normal operation.

In view of the above problems, the present invention can verify an arbitrary functional operation inside an LSI by using an actual video signal in a system incorporating the LSI, and can stop a change in an output signal of an unused output terminal. It is an object of the present invention to provide an LSI test circuit that can be used.

[0010]

In order to solve the above problems, an LSI test circuit of the present invention has a first arithmetic circuit having a certain specific function and a function different from the first arithmetic circuit. A second arithmetic circuit; a third arithmetic circuit having a function different from those of the first and second arithmetic circuits; a first delay circuit having the same delay time as that of the first arithmetic circuit; A second delay circuit having the same delay time as the second arithmetic circuit, a third delay circuit having the same delay time as the third arithmetic circuit, an output of the first arithmetic circuit and the first delay circuit. A first selector that receives the output of the circuit as an input and outputs to the second arithmetic circuit and the second delay circuit, and outputs the output of the second arithmetic circuit and the output of the second delay circuit as the input. The third operation circuit and the second selector which outputs to the third delay circuit, A third selector that receives the output of the third arithmetic circuit and the output of the third delay circuit, and a circuit that controls switching between the first, second, and third selectors. .

A selector which receives signals output from a plurality of arithmetic circuits, a gate arithmetic processing circuit which performs a gate arithmetic operation on an output signal of the selector, the selector and the gate arithmetic processing circuit. And a circuit for controlling the.

[0012]

According to the present invention, with the above configuration, when only an arbitrary arithmetic circuit is operated, a portion corresponding to the other arithmetic circuit is provided with a delay time corresponding thereto,
The output signal obtained has the same delay time as in normal operation,
It is possible to verify the arithmetic function inside the LSI in a state where it is incorporated in an actually operated system.

Further, by changing the signal output to the output terminal which is not used during the normal operation inside the LSI, the change of the output signal can be stopped.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of an LSI test circuit according to an embodiment of the present invention.

In FIG. 1, 1 is an arithmetic circuit having a specific function, 2 is an arithmetic circuit having a different function from the arithmetic circuit 1, 3 is an arithmetic circuit having a different function from the arithmetic circuits 1 and 4, 4 Is a delay circuit having the same delay time as the arithmetic circuit 1,
Reference numeral 5 is a delay circuit having the same delay time as that of the arithmetic circuit 2, 6 is a delay circuit having the same delay time as that of the arithmetic circuit 3, and 7 is an arithmetic circuit 2 by selecting the output of the arithmetic circuit 1 and the output of the delay circuit 4.
A selector for outputting to the arithmetic circuit 2 and the delay circuit 5, and a selector 8 for selecting the output of the arithmetic circuit 2 and the output of the delay circuit 5 and outputting them to the arithmetic circuit 3 and the delay circuit 6. 9 indicates the output of the arithmetic circuit 3 and the delay circuit 6. A selector 10 that selects and outputs an output is a circuit that controls the selection circuits 7, 8, and 9.

The operation of the LSI test circuit configured as described above will be described below.

In FIG. 1, when verifying the operation of the arithmetic circuit 1, the input signal from the input terminal is input to the arithmetic circuit 1 and the delay circuit 4. Here, the control circuit 10 controls the selector 7 so as to select the output signal of the arithmetic circuit 1. The output signal of the selector 7 is input to the arithmetic circuit 2 and the delay circuit 5, and the control circuit 10 controls the selector 8 to select the output signal of the delay circuit 5. The output signal of the selector 8 is input to the arithmetic circuit 3 and the delay circuit 6, and here also, the control circuit 10 controls the selector 9 to select the output signal of the delay circuit 6. Through this series of operations, an output signal having the same delay time as the normal operation in which all the functions are operated can be obtained.

As described above, according to this embodiment, by controlling the arithmetic circuit, the delay circuit corresponding thereto, and the selector for selecting these outputs, in the entire system including this LSI, a certain inside of the LSI is specified. Only the function can be operated.

The operation verification of the arithmetic circuit 1 has been described above. However, even when other arithmetic circuits or a plurality of arithmetic circuits are combined, the control circuit 10 devises control of each selector so that an arbitrary functional operation can be performed. Can be verified.

(Embodiment 2) Next, an LS according to an embodiment of the present invention
The I test circuit will be described with reference to the drawings.

1 and 2 are block diagrams of an LSI test circuit according to an embodiment of the present invention.

In FIG. 1, 1 is an arithmetic circuit having a specific function, 2 is an arithmetic circuit having a different function from the arithmetic circuit 1, 3 is an arithmetic circuit having a different function from the arithmetic circuits 1 and 4, 4 Is a delay circuit having the same delay time as the arithmetic circuit 1,
Reference numeral 5 is a delay circuit having the same delay time as that of the arithmetic circuit 2, 6 is a delay circuit having the same delay time as that of the arithmetic circuit 3, and 7 is an arithmetic circuit 2 by selecting the output of the arithmetic circuit 1 and the output of the delay circuit 4.
A selector for outputting to the arithmetic circuit 2 and the delay circuit 5, and a selector 8 for selecting the output of the arithmetic circuit 2 and the output of the delay circuit 5 and outputting them to the arithmetic circuit 3 and the delay circuit 6. 9 indicates the output of the arithmetic circuit 3 and the delay circuit 6. A selector 10 that selects and outputs an output is a circuit that controls the selection circuits 7, 8, and 9. A selector 12 receives the output signals of a plurality of arithmetic circuits 1 and 2 and selects an arbitrary output and outputs it to the gate arithmetic circuit 11. A gate arithmetic 11 performs a gate arithmetic on the output signal of the selector 12. It is a processing circuit.

In FIG. 2, 13 is an AND gate, which is an example of the configuration of the gate arithmetic processing circuit 11 in FIG.
The terminal D corresponds to the output end of the selector 12 in FIG. 1, the terminal E corresponds to the output end of the control circuit 10, and the terminal F corresponds to the output end of the gate arithmetic processing circuit 11.

The operation of the LSI test circuit configured as described above will be described below.

The selector 12 selects and outputs the signal to be observed from the outputs of the arithmetic processing circuits 1 and 2. In the gate arithmetic processing circuit 11, the output of the selector 12 and the control circuit 1
The output of 0 is used for input to the AND gate 13. This gate output is output from the dedicated test terminal.

As described above, according to this embodiment, when it is desired to observe the output of a certain arithmetic circuit, the output signal of the control circuit 10 is set to the high level and the output of the arithmetic circuit is output to the terminal. By changing the output signal of the circuit 10 to the low level and fixing the output to the low level, the change of the signal of the test-dedicated output terminal can be stopped.

Here, the case where the AND gate 13 is used as the gate arithmetic processing circuit 11 has been described, but it can also be realized by an OR gate or the like.

[0029]

As described above, according to the LSI test circuit of the present invention, by providing a plurality of arithmetic circuits, a delay circuit corresponding thereto, a selector for selecting them, and a control circuit for the selector, the LSI can be implemented. In the included system, it is possible to verify the function of the LSI by using the actual signal.

Further, by providing a selector which receives signals respectively output from a plurality of arithmetic circuits, a gate arithmetic processing circuit, and a circuit which controls these, from an output terminal which is not used in actual operation, There is no signal change, and power consumption can be reduced and interference can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of an LSI test circuit according to the present invention.

FIG. 2 is a block diagram of a gate arithmetic processing circuit according to the present invention.

FIG. 3 is a block diagram of a conventional LSI test circuit.

[Explanation of symbols]

 1 1st Arithmetic Circuit 2 2nd Arithmetic Circuit 3 3rd Arithmetic Circuit 4 1st Delay Circuit 5 2nd Delay Circuit 6 3rd Delay Circuit 7 1st Selector 8 2nd Selector 9 3rd Selector 10 Control circuit 11 Gate arithmetic processing circuit 12 Fourth selector 13 AND gate

Claims (2)

[Claims] 1. A first arithmetic circuit, a second arithmetic circuit,
The first arithmetic circuit, the third arithmetic circuit, the first delay circuit having the same delay time as the first arithmetic circuit, and the second delay circuit having the same delay time as the second arithmetic circuit. And a third delay circuit having the same delay time as that of the third arithmetic circuit, the output of the first arithmetic circuit and the output of the first delay circuit as inputs, and the second arithmetic circuit and the third arithmetic circuit. A first selector for outputting to the second delay circuit; a second selector for receiving the output of the second arithmetic circuit and the output of the second delay circuit as an input; and outputting to the third arithmetic circuit and the third delay circuit. A second selector, a third selector that receives the output of the third arithmetic circuit and the output of the third delay circuit, and a circuit that controls switching between the first, second, and third selectors. LSI test circuit equipped with. 2. A selector which receives signals output from a plurality of arithmetic circuits, a gate arithmetic processing circuit which performs a gate arithmetic operation on an output signal of the selector, the selector and the gate arithmetic processing circuit. An LSI test circuit including a circuit for controlling the.