JPH0832546A - Orthogonal frequency division multiplex signal transmitter-receiver - Google Patents

Abstract

PURPOSE:To keep the synchronization relation of a receiver side constant by setting a pilot signal the configuration so that an integral number of wavelengths is in existence in a guard interval period and sending the signal continuously including a signal in this period. CONSTITUTION:An output signal of an IFFT and a pilot signal generating circuit 3 are fed to a guard interval (gi) setting circuit 4 having a RAM4A, in which the gi for a prescribed period is set. The circuit 4 is operated based on a clock signal from a clock signal generating circuit 10 and generates a pilot signal with higher frequencies in which its angular modulation component is kept constant for plural symbol periods. Then the pilot signal is set so that an integral of wavelengths or an odd multiple of a half wavelength is set in existence in the gi period set by the circuit 4 and the resulting signal is continuously sent together with the signal in this gi period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to OFDM (Orthogonal Frequency Division Multiplexing Orthogonal Frequency).
Division Multiplexing) signal transmitting / receiving apparatus, particularly suitable for digital mobile communication.
The present invention relates to an FDM signal transmitting / receiving device.

[0002]

2. Description of the Related Art A conventional OFDM signal transmitting apparatus will be described with reference to FIG. First, the digital information data signal is supplied to the serial-parallel conversion circuit 70 via the input terminal,
An error correction code is added as needed. The output signal of the circuit 70 is supplied to the IFFT circuit 71, and the output signal thereof is supplied to the D / A converter 73 via the guard interval circuit 72 for reducing multipath distortion. Here, it is converted into an analog signal and the next LPF 7
4 allows only the components in the required frequency band to pass. The output signal of the real, imaginary part of analog value is supplied to the quadrature modulator 75, and the OFDM signal is output.

This OFDM signal is frequency-converted into a frequency band to be transmitted by a frequency converter 76 and supplied to the next transmitting section 77, and is transmitted via a linear amplifier and a transmitting antenna constituting the same. To be done. The output signal of the intermediate frequency generation circuit 78 and the signal passed through the 90 ° shift circuit 78A are supplied to the quadrature modulator 75, respectively. The output signal of this circuit 78 is supplied to the clock signal generation circuit 79. The output clock signal of the circuit 79 is supplied as an operation signal to the serial / parallel conversion circuit 70, the IFFT circuit 71, the guard interval circuit 72, and the D / A converter 73, respectively.

Next, the OFDM signal receiving apparatus will be described with reference to FIG. The receiving section 80 amplifies the signal from the transmitting section 77 obtained by the receiving antenna constituting the same by a high frequency amplifier, supplies the amplified signal to the intermediate frequency amplifying circuit 82 via the frequency converter 81, and further, orthogonally. Demodulator 83
Is supplied to. The output signal of the circuit 82 is supplied to the intermediate frequency generation circuit 89 via the carrier detection circuit 90. The output signal of the circuit 89 and the signal passed through the 90 ° shift circuit 89A are supplied to the quadrature demodulator 83, respectively, and the output signals of the real and imaginary reparts are decoded. Quadrature demodulator 8
The output signal of 3 is sent to the A / D converter 85 via the LPF 84.
And converted into a digital signal,
The output signal of is also supplied to the synchronization signal generation circuit 91.

These signals are supplied to the FFT and QAM decoding circuit 87 via the next guard interval circuit 86. This circuit 87 is supplied with a synchronizing signal generating circuit 91.
Based on the synchronization signal of, the complex Fourier operation is performed, the level of the real part and imaginary part signal (real part, imaginary part) of each frequency of the input signal is obtained, and the quantization transmitted by the carrier for digital information transmission. The level of the digital signal thus obtained is obtained, and the digital information is decoded. The output signal of the FFT / QAM decoding circuit 87 is output via the parallel-serial conversion circuit 88. Here, if the intermediate frequency of the transmitting device and the intermediate frequency of the receiving device are completely the same, only the modulation component is obtained, and there is no problem, but the intermediate frequency generating circuit, the local oscillator of the frequency converter (not shown). If the frequency stability is not high, or if there is a phase error between both output signals, it will affect the subsequent demodulation operation and increase the probability of symbol error occurrence.

[0006]

In the OFDM signal transmitting / receiving apparatus, it is very difficult to completely reproduce the phases of all multi-carriers on the receiving side without having a time-axis fluctuation component. In order to reduce multipath distortion, the guard interval circuit is set on the transmission side. Therefore, when receiving a transmission signal under such conditions, the effective symbol length part and the guard interval part are There is a problem that it is more difficult to reproduce the phase in the completely same state. The present invention has been made by paying attention to the above points, and provides an OFDM signal transmitting / receiving apparatus in which a pilot signal is set in a specific carrier of OFDM, and thereby it is possible to maintain a constant synchronization relationship on the receiving side. The purpose is to

[0007]

The OFDM signal transmitting / receiving apparatus of the present invention is supplied with a digital information signal, and multilevel QAM.
An IFFT for generating a modulation signal, a pilot signal generation circuit, a guard interval setting circuit configured to repeatedly transmit a part of the modulation signal for a predetermined time, and a clock signal generation circuit for driving both circuits. Then, the IFFT and pilot signal generating circuits generate a pilot signal of a high-order frequency in which the angle modulation component is held constant in a plurality of symbol periods, and the pilot signal is set to the guard interval set by the guard interval setting circuit. The above-mentioned object is achieved by having an integral wavelength within a section and continuously transmitting the signal including the section.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of an OFDM signal transmitting / receiving apparatus of the present invention will be described below with reference to the attached FIGS. FIG. 1 shows an embodiment of an OFDM signal transmitting apparatus of the present invention, in which digital data transmitted here are compressed audio, video signals and the like. In OFDM, a large number of carriers are arranged orthogonally and independent digital information is transmitted by each carrier. Since the carriers are orthogonal, the spectrum of adjacent carriers becomes zero at the frequency position of the carrier. . IFFT circuit technology is used to create this orthogonal carrier. Time interval T
If an inverse DFT (discrete Fourier transform) with N complex numbers is executed during
Points correspond to the modulated signal output.

The basic specifications of the device of the present invention shown in FIGS. 1 and 2 are as follows. (a) Central carrier frequency ... 100 MHz (b) Number of carriers for transmission ... 248 waves (c) Modulation method ... 256QAM OFDM (d) Number of carriers used ... 257 waves (e) Transmission bandwidth ... 100 kHz, bandwidth ... 99 k
Hz (f) Transfer rate ... 750 kbps (g) Guard interval ... 60.6 μsec As shown in FIG. 1, for example, a digital information signal, which is an audio or video signal whose information signal is compressed by an encoding system such as MPEG, It is supplied to the serial-parallel conversion circuit 2 via the input terminal 1, and an error correction code is added as necessary. In this circuit 2, the input signal is arranged and output as a 256QAM modulation signal. This 256QA
The M modulation defines 16 levels in the amplitude direction and 16 levels in the angle direction with respect to a carrier for transmitting information.
In this method, 256 values of x16 are specified and transmitted. In this embodiment, of the 257 wave carriers, 248 waves are used to transmit information, and the remaining 9 waves are used for calibration and for transmitting other auxiliary signals.

The serial-parallel conversion circuit 2 is configured to output 248 bytes of digital data in one symbol period, that is, 248 sets of parallel data of 4 bits each in one symbol period. The output signal of the serial-parallel conversion circuit 2 is
It is supplied to the IFFT and pilot signal generation circuit 3. This circuit 3 operates according to the clock signal output from the clock signal generation circuit 10, performs 256QAM modulation on a 248-wave carrier, and outputs each output signal in real,
Output as an imaginary component. Further, the discrete frequency point information of the circuit 3 is transmitted as Nyquist frequency information which is a value of 1/2 with respect to the cycle N. Since this frequency information is 1/2 of the discrete frequency point information, the Nyquist signal information is received by the receiving device. Can be decoded and multiplied to generate a sampling position signal for operating the FFT circuit. This Nyquist frequency information is obtained by applying a signal of a constant level to the N / 2 real part input terminal R (imaginary part input terminal I) of the IFFT and pilot signal generation circuit 3.

The output signals of these circuits 3 are output to the next RAM.
It is supplied to a guard interval setting circuit 4 having a (random access memory) 4A, and this circuit sets a guard interval gi of a predetermined section for reducing multipath distortion in the transmission path as shown in FIG. The guard interval setting circuit 4 operates according to the clock signal output from the clock signal generation circuit 10,
The last part in the window section obtained from the IFFT / pilot signal generation circuit 3 is arranged immediately before the window section signal. To achieve this, the guard interval setting circuit 4 sets the last period (equal to gi) when reading the signal from the IFFT / pilot signal generation circuit 3 fetched in the RAM (4A) of the guard interval setting circuit 4. .), The effective symbol period ts is read and the signal of the symbol period ta is transmitted. The Nyquist frequency information is transmitted even within the guard interval, but in order to maintain continuity with the preceding and following IFFT window section signals, the transmitted pilot signal has an integral wavelength within the guard interval.

Although the case where the Nyquist frequency is used as the pilot signal has been described, the Nyquist frequency does not have to be the Nyquist frequency if the sampling position signal and the sampling position signal have a simple integer ratio. Higher ones may be used. When considering the IFFT of period M, M / 4,
Further, the pilot signal is arranged at a position of 1/2 of the Nyquist frequency, which is 3M / 4, and the carriers transmitted by OFDM are from the first to the M / 4th and from the 3M / 4th to the fourth in the IFFT. The signals output up to the Mth are used. As a result, a signal equivalent to that when M = 2N in the above example can be obtained. Therefore, a continuous pilot signal can be transmitted even within the guard interval, and a sampling position signal can be obtained by decoding this pilot signal and multiplying it by four. FF
If the window section signal information of T can be decoded separately, the FFT operation of the OFDM signal can be performed by combining with the sampling position signal obtained in the present embodiment, and the decoding of the OFDM signal can be performed.

Next, the symbol period of the guard interval setting circuit 4 will be described with reference to FIG. First, when the used bandwidth is 99 kHz and the cycle is N = 256, the effective symbol frequency fs and the effective symbol period ts are as follows, respectively. fs = 99,000 / 256 = 387 Hz ts = 1 / fs = 2586 μsec Further, when the guard interval period gi, which is a section for multipath distortion removal, is determined for 6 carrier wavelengths, gi is set as follows. gi = (1 / 99,000) × 6 = 60.6 μsec The symbol period ta and the symbol frequency fa at this time are as follows. ta = ts + gi = 2586 + 60.6 = 2646.6
μsec fa = 1 / ta = 378 Hz

The output signals of these guard interval setting circuits 4 are supplied to the D / A converter 5, where they are converted into analog signals, and only the necessary frequency band components are passed through by the next LPF 6. Real analog value,
The imaginary output signal is supplied to the next quadrature modulator 7,
Further, the modulator 7 is supplied with the output signal of the 10.7 MHz intermediate frequency generation circuit 9 and the signal through the 90 ° shift circuit 8, respectively, and outputs an OFDM signal. This OF
The DM signal is frequency-converted into a frequency band to be transmitted by the frequency converter 11 and supplied to the next transmission unit 12, and is transmitted via the linear amplifier and the transmission antenna which configure the DM unit. The output signal of the 10.7 MHz intermediate frequency generation circuit 9 is also supplied to the clock signal generation circuit 10. Since 248 sets of 4 + 4 bits of parallel data are transmitted by the carrier of 248 waves, the transmission rate of this device is 248 bytes per symbol period. Therefore, the transmission rate per second is approximately 750 Kbits.

Next, the phase relationship between the guard interval, the symbol period and the synchronizing signal (pilot signal) will be described below with reference to the drawings. In FIG. 7, a case will be described in which sync signals of the same phase are generated in each symbol period and sync signals of integer wavelength are present in the guard interval. (This is a first example of generating a continuous synchronizing signal without inverting the phase.) IFFT is synonymous with the effective symbol period, and one cycle at the end (right part) of the IFFT period is I as it is.
The signal is the guard interval signal (left part) before the FFT. In this example, the synchronization signal (pilot signal) of the same phase is generated for each IFFT, and since the synchronization signal has an integral wave in the guard interval section, the pilot signal is continuously generated over a plurality of symbol sections. Has been. The case of FIG. 3 already described is the same as that of FIG. 7, and since the synchronizing signal exists in the guard interval section as an integral wave, the pilot signal is continuously generated over a plurality of symbol sections.

In FIG. 8, a case will be described in which sync signals of the same phase are generated in each symbol period, and there is a sync signal having a guard interval that is an odd multiple of a half wavelength.
(This is a second example of generating a continuous synchronization signal without inverting the phase.) IFFT is synonymous with the effective symbol period, and the 1/2 cycle of the end part (right part) of the IFFT period is IFFT as it is. It is the signal of the guard interval in front of (left part). In this example, a synchronization signal (pilot signal) having an opposite phase is generated for each IFFT, and since a synchronization signal having an odd multiple of a half wavelength is present in the guard interval section, the pilot signal is continuous over a plurality of symbol sections. Has been generated.

In FIG. 9, the case where the synchronization signal exists in the guard interval in an odd multiple of half the wavelength will be described.
(This is a first example of generating a synchronization signal with inverted phase.) In this case, the pilot signal is in phase before the guard interval, that is, for each symbol period. That is,
The terminal voltage corresponding to the frequency for generating the synchronizing signal of the IFFT for generating the frequency division multiplexed signal is constant for each symbol, and the synchronizing signal of the same phase is always generated. Therefore, when the guard interval is an odd multiple of half the wavelength, the synchronization signal becomes a continuous signal when the receiving device inverts the phase of the synchronization signal every other symbol period. in this case,
The synchronization signal can be detected using a PLL circuit as shown in FIG.

In FIG. 10, the case where the synchronization signal exists in the guard interval at an even multiple of half the wavelength will be described. (This is a second example of generating a synchronization signal with inverted phase.) As shown in FIG. 10, even when the synchronization signal existing in the guard interval is an integer wave (even multiple of half wavelength), As in the case of FIG. 9, if the synchronization signal is inverted and output every other symbol period, a synchronization output in which the phase is inverted for each symbol is obtained. Also in this case, the PLL circuit as shown in FIG. 11 can be used to detect the synchronization signal.

FIG. 11 shows a synchronizing circuit for detecting a synchronizing signal which is inverted every other symbol period. This circuit includes a phase comparator PD2 (112), Amp (amplifier) 1
P composed of 13, LPF 114 and VCO circuit 115
This is a configuration in which the signal switch 116 configured by an exclusive OR is inserted in the VCO output of the LL circuit. .
The phase comparator PD1 (121) is a VCO of the phase synchronization circuit.
It constitutes a synchronous detection circuit with the output as input. The frequency division multiplexed signal including the synchronization signal is input to both the phase synchronization circuit and the synchronization detection circuit. PD1 (11
The output of 1) is configured to invert the output of the VCO circuit 115 of the PLL, but the synchronization signal whose phase is inverted for each symbol is detected by the synchronous detector, and the PD2 (112) forming the PLL has Since the phase-inverted VCO output is supplied, the lock operation is continuously performed even for the phase-inverted sync signal.

FIG. 12 shows output waveforms of the terminals B and A in FIG. The output A is a sync signal output waveform, and the output B is a symbol period signal that is phase-inverted and transmitted for each symbol period. FIG. 13 shows another embodiment of FIG.
The signal switch 136 is inserted between the phase comparator PD2 (132) and the amplifier 133. At the same time that the synchronization signal is inverted, it is detected and the polarity of the error signal is inverted, and the operation mode is the same as in FIG. In either case, even if the sync signal is inverted every other symbol period, it is detected and the characteristics of the loop of the PLL are inverted, so that the VCO continues the continuous operation without being inverted. Therefore, the synchronization signal can be decoded normally.

Next, an embodiment of the receiving apparatus of the present invention will be described with reference to FIG. Each component of the receiving device is composed of a circuit that operates in reverse to the transmitting device. Receiver 20
The high-frequency amplifier amplifies the signal from the transmitting unit 12 obtained by the receiving antenna constituting the unit, and supplies the amplified signal to the frequency converter 21. This output signal is supplied to the intermediate frequency amplifier circuit 22 and outputs a reception signal of a predetermined level. The output signal of the circuit 22 is supplied to the quadrature demodulator 23 and the carrier detection circuit 29, respectively. The circuit 29 has a PLL circuit including a phase comparator (multiplier), an LPF, a VCO circuit, and a 1/4 frequency divider circuit. The intermediate frequency oscillation circuit 31 to which the output signal is supplied is at the center. This is a circuit that extracts carriers with a small phase error.

In this embodiment, carriers for transmitting information are arranged adjacent to each other at a symbol frequency of 378 Hz to form an OFDM signal. The information carrier adjacent to the center carrier is also 378 Hz apart, and it is necessary to perform the center carrier without being influenced by the adjacent information carrier, and a circuit with high selectivity is used. In this embodiment, the central carrier is extracted by using the PLL circuit, which is approximately 1/2 of the frequency of the adjacent carrier ± 20.
A crystal oscillator (VCXO) that oscillates at about 0 Hz is used as a voltage controlled oscillator (VCO) 43 to operate the circuit. The LPF used in the PLL circuit also has a cutoff frequency sufficiently low with respect to 378 Hz.
The output signal of the intermediate frequency generation circuit 31 and the signal passed through the 90 ° shift circuit 30 are supplied to the quadrature demodulator 23 having the multipliers 40 and 41, respectively, and the real and imaginary part (real part, imaginary part) are supplied. The output signal is decoded. The real part and imaginary part output signals are supplied to the LPF 24 and
A signal of a required frequency band transmitted as FDM signal information is passed, an input analog signal is sampled, an output signal is supplied to an A / D converter (sampling circuit) 25, and converted into a digital signal. .

The sample synchronizing signal generating circuit 32 is generated by a PLL circuit which is phase-locked with the pilot signal, and the analog output signal of the quadrature demodulator 23 is supplied to this circuit. PL is added to the pilot signal transmitted as a continuous signal in each symbol section including the guard interval period.
L is phase-locked, and pilot frequency information is obtained. In the transmitter, the pilot signal is set to a predetermined integer ratio with respect to the sample clock frequency, and frequency multiplication is performed according to the frequency ratio to obtain the sample clock signal. The guard interval processing circuit 26 obtains an effective symbol period signal which is less affected by multipath distortion than the transmitted signal, and the FFT / QAM decoding circuit 27.
Supply an output signal to.

The symbol synchronization signal generating circuit 33 for detecting the symbol period detects the symbol period.
The next FFT and QAM decoding circuit 27 is supplied with the obtained clock synchronization signal and symbol synchronization signal, performs a complex Fourier operation, and outputs a real part and an imaginary part signal (real part, imaginary part) for each frequency of the input signal. Part) ask for the level. The real and imaginary part signal levels for each frequency obtained in this way are compared with the demodulated output of the reference carrier, and the level of the quantized digital signal transmitted by the carrier for digital information transmission is obtained. And the digital information is decoded. The output signal of this circuit 27 is
It is output via the parallel-serial conversion circuit 28.

Next, the carrier extraction circuit and the sample synchronization (sample clock) signal generation circuit will be described with reference to FIG. The purpose of this circuit is to extract a more accurate sample synchronization (sample clock) signal from the pilot signal transmitted at a constant level. First, the VCO circuit 43 forming the carrier extraction circuit is oscillated at a frequency of 42.8 MHz which is four times the intermediate frequency of 10.7 MHz. The output signal of the circuit 43 is supplied to the multipliers 40 and 41 via the 1/4 frequency dividing circuits 44 and 45, respectively. An output signal from one of the multipliers 41 is supplied to the LPF 42, a component having a frequency equal to or lower than the symbol frequency is extracted, and the output signal controls the VCO circuit 43. Multiplier 41, L
A loop formed by the PF 42, the VCO circuit 43, and the frequency dividing circuit 45 constitutes a PLL circuit.

The intermediate frequency amplified signals are applied to the input terminals of the multipliers 40 and 41, and orthogonal decoding is performed by this circuit to obtain the output signals of the real number part and the imaginary number part. The sample sync signal generation circuit 32 will be described below. The real part output signal from the quadrature demodulator 23 is supplied and the Nyquist frequency component transmitted as a pilot signal is detected. The frequency division ratio variable circuit (VCO circuit) 50 includes a VCO circuit 43.
Output signal is supplied, and the division ratio is from 1/426 to 1/4
It is configured to be set up to 38. The multiplier 52 in the clock extraction unit is supplied with the output signal from the quadrature demodulator 23 and the signal from the VCO circuit via the 1/2 frequency divider circuit 51, and operates as a phase comparator.

As the output signal of the multiplier 52, only the error signal related to frequency control is passed by the LPF circuit 53. The delay circuit 54 and the adder circuit 55 are circuits for attenuating adjacent carrier components and have a symbol frequency of 387H.
It has a characteristic that z has a dip. VCO circuit 5
The PLL circuit composed of 0, the multiplier 52, and the LPF 53 oscillates the VCO output signal synchronized with the continuous pilot signal included in the real part output signal of the carrier extractor, and outputs it as the sample clock output signal of 99 kHz. It In the above embodiment, the case of using the 256 IFFT to generate the carrier of 257 waves was described, but as another embodiment, an example of using the 512 IFFT will be described below. In the other embodiment, the Nyquist frequency is not used as the pilot frequency, but a high-order frequency having a simple integer ratio relationship with the sampling position signal is used.

That is, when considering an IFFT having a period M, M
/ 4 and 1/2 of the Nyquist frequency, which is 3M / 4
The pilot signals at the positions are arranged and the carriers transmitted in OFDM use the signals output from the first to M / 4th and from the 3M / 4th to Mth in IFFT. This makes it possible to obtain a signal equivalent to that when M = 2N in the above embodiment. Therefore, it is possible to transmit a continuous pilot signal even within the guard interval, and it is possible to obtain a signal at the sampling position by decoding the pilot signal and multiplying it by four.

In the block of the clock extraction unit used at this time, the frequency of the pilot signal is the same as that in the above-mentioned embodiment, but the sample clock frequency for driving the FFT and QAM decoding circuit 27 is doubled. Accordingly 2
And outputs a doubled 198 kHz sample clock signal.
Therefore, in this block, the frequency division ratio of the frequency division ratio variable circuit 50 is 1/213 to 1/219, and the frequency division ratio of the frequency division circuit 51 is 1/4 as compared with the above embodiment. The other configuration is the same as that of FIG. 4, and the description thereof is omitted.

According to the OFDM signal transmitting / receiving apparatus of the present invention,
The guard interval period is determined by the same sample clock that drives the IFFT and pilot signal generation circuit, and the pilot signal used for transmitting the sample clock information is set so that the guard interval period is also continuous, and is actually transmitted. The frequency spectrum of the pilot signal is single. Therefore, a pilot signal without jitter can be decoded in the receiving device, and an IFFT circuit operating in the transmitting device and an FFT operating in the receiving device.
It becomes easy to set the time relation of the circuits to be the same, and I
The FFT operation can be performed in a form close to the signal subjected to the FFT operation, and more accurate information can be transmitted.
Also, the phase synchronization method according to the present invention can normally decode the synchronization information with respect to the synchronization signal information transmitted continuously or inverted every symbol period. This means that even in the case of mobile reception or the like, even when the time division synchronizing signal is decoded with phase noise, it can be received while being corrected, so that the clock synchronizing signal and the symbol position signal can be well decoded. Furthermore, since the symbol synchronizing information is inserted into the clock information signal transmitted in the information signal, the synchronizing signal can be decoded before the time division synchronizing signal comes in, which is short even when the channel of the receiver is switched. It has an effect that a frequency division multiplexed signal can be decoded in time.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an OFDM signal transmission apparatus of the present invention.

FIG. 2 is a block diagram of an embodiment of an OFDM signal receiving apparatus of the present invention.

FIG. 3 is a diagram showing a relationship between a symbol period and a guard interval according to the embodiment of the transmission / reception device of the present invention.

FIG. 4 is a block diagram of a carrier extraction unit and a sample clock extraction unit of the embodiment of the OFDM signal receiving apparatus of the present invention.

FIG. 5 is a block diagram of a conventional OFDM signal transmitter.

FIG. 6 is a block diagram of a conventional OFDM signal receiving apparatus.

FIG. 7 is a diagram showing a relationship between a synchronization signal and a symbol period.

FIG. 8 is a diagram showing a relationship between a synchronization signal and a symbol period.

FIG. 9 is a diagram showing a relationship between a synchronization signal and a symbol period.

FIG. 10 is a diagram showing a relationship between a synchronization signal and a symbol period.

FIG. 11 is a diagram showing an example of a synchronization circuit.

FIG. 12 is an output waveform diagram of the synchronization circuit.

FIG. 13 is a diagram showing another example of the synchronization circuit.

[Explanation of symbols]

 2 serial-parallel conversion circuit 3 IFFT, pilot signal generation circuit 4 guard interval setting circuit 4A RAM (random access memory) 5 D / A converter 6, 24, 42, 53, 114, 134 LPF 7 quadrature modulator 8, 30 90 ° shift circuit 9,31 intermediate frequency generation circuit 10 clock signal generation circuit 11,21 frequency converter 12 transmitter 20 receiver 23 quadrature demodulator 25 A / D converter (sampling circuit) 26 guard interval processing circuit 27 FFT, QAM decoding circuit 28 Parallel-serial conversion circuit 29 Carrier detection circuit 32 Sample synchronization signal generation circuit 33 Symbol synchronization signal generation circuit 40, 41, 52 Multiplier (phase comparator) 43, 50, 115, 135 VCO circuit 44, 45 1 / 4 divider circuit 51 1/2 divider circuit 111, 112, 131 , 132 Phase comparator (PD) 116, 136 Signal switching device

Claims (6)

[Claims] 1. A multilevel QAM supplied with a digital information signal.
An IFFT for generating a modulation signal, a pilot signal generation circuit, a guard interval setting circuit configured to repeatedly transmit a part of the modulation signal for a predetermined time, and a clock signal generation circuit for driving both circuits. Then, the IFFT / pilot signal generation circuit generates a pilot signal of a high-order frequency in which the angle modulation component is kept constant in a plurality of symbol periods, and the pilot signal is a guard interval section set by the guard interval setting circuit. There is an integer wavelength within, or
An orthogonal frequency division multiplex signal transmission device, characterized in that it is set so that an odd number of half wavelengths are present, and is configured to be continuously transmitted including the section. 2. A multilevel QAM supplied with a digital information signal.
An IFFT for generating a modulation signal, a pilot signal generation circuit, a guard interval setting circuit configured to repeatedly transmit a part of the modulation signal for a predetermined time, and a clock signal generation circuit for driving both circuits. Then, the IFFT / pilot signal generation circuit generates a pilot signal of a high-order frequency in which the angle modulation component is kept constant in a plurality of symbol periods, and the pilot signal is a guard interval section set by the guard interval setting circuit. There is an integer wavelength within, or
An orthogonal frequency division multiplex signal transmission device, characterized in that the pilot signal is set to be present in odd multiples of a half wavelength, and the pilot signal is inverted and transmitted every other symbol period. 3. The method according to claim 1, wherein the clock signal of the clock signal generating circuit is commonly used as the clock signal for driving the IFFT / pilot signal generating circuit and the guard interval setting circuit. Orthogonal frequency division multiplex signal transmitter. 4. The frequency of the pilot signal and the IFF
The orthogonal frequency division multiplex signal transmission device according to claim 1 or 2, wherein T and the frequency of the clock signal for driving the pilot signal generation circuit are constituted by a simple integer ratio. 5. A frequency converter for converting the frequency of a received frequency division multiplexed signal, a sampling circuit for sampling the output signal of the converter at a predetermined time interval, and a multipath by a set guard interval section. An FFT and QAM decoding circuit configured to obtain a frequency division multiplexed signal with a small amount of interference distortion component due to distortion, and set to have an integer wavelength or an odd multiple of a half wavelength within the guard interval section. And a synchronization signal generating circuit for converting the obtained angle demodulation component into a predetermined frequency ratio and outputting a clock signal for driving the sampling circuit. Orthogonal frequency division multiplex signal receiver. 6. A frequency converter for frequency-converting a received frequency division multiplexed signal, a sampling circuit for sampling an output signal of the converter at a predetermined time interval, and a multipath by a set guard interval section. An FFT and QAM decoding circuit configured to obtain a frequency division multiplex signal with less interference distortion component due to distortion, and angle demodulation of a pilot signal that is inverted and transmitted every other symbol period are obtained. An orthogonal frequency division multiplex signal reception device comprising: a synchronization signal generation circuit that converts an angle demodulation component into a predetermined frequency ratio and outputs a clock signal that drives the sampling circuit.