JPH08171553A - Digital filter - Google Patents

Abstract

PURPOSE: To obtain a digital filter which is variable in the number of bits of a cumulative data output after a rounding process by selecting rounding process bits by specifying one of plural rounding process parts, and rounding the selected rounding process bits. CONSTITUTION: The outputs of multipliers 11 -1n are added by adders 41 -4n to cumulative data 14 or the outputs of the adders of the precedent stages and the results are outputted to the following stages. For example, 32 multipliers 11 -1n (n=32) are provided, data supplied to the multipliers 11 -1n are composed of 8 bits, and coefficient data are also composed of 8 bits. In this case, cumulative data inputted from the adder 432 to a rounding arithmetic part 10 consists of 18 bits. At this time, a rounding address decoder 12 selects 2 or 3 rounding process bits in the rounding arithmetic part 10 and performs the rounding process to obtain a 16-bit or 17-bit cumulative data output.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to digital filters.

[0002]

2. Description of the Related Art A digital filter is composed of a plurality of multipliers for multiplying input data by a predetermined coefficient, an adder for accumulating outputs of the multipliers, and the like. In the conventional digital filter, for example, rounding is performed after the output of each multiplier, or rounding is performed after the addition of the n-th multiplier and the accumulated data of the n-1 term. FIG. 6 shows a configuration example of the latter digital filter. In the digital filter shown in FIG. 6, for example, the data bus 1
The data supplied to 2 and the coefficient data supplied to the coefficient data bus 13 are each 8 bits, and the internal multipliers 1 ₁ to
When 1 _n is 32 (n = 32), the cumulative data output in the adder 4 ₃₂ is 19 bits. If the rounding process is set to 3 bits, the cumulative data input to the rounding operation unit 8 will be the upper 17-bit data. Then, the least significant bit of the higher 17 bits is rounded and output as 16-bit (3-bit rounded) cumulative data. Figure 7
Shows the details of the rounding operation unit 8. Calculating unit 8 rounding is constituted by sequentially connecting a carry circuit 81 ₁ to 81 ₁₆ as shown in FIG. 7 (A). Each carry circuit 81 has four input / output parts as shown in FIG. 7B, and performs rounding processing by operating as shown in FIG. 6C for an input signal.

[0003]

However, in the conventional digital filter, the rounding operation unit 8 which performs rounding determines the number of rounding processing bits. Therefore, in a digital filter with accumulated data output of n bits, n + 1 bits or more are used. It could not be used when cumulative data output was required. That is, the example shown in FIG. 6 cannot be used when cumulative data output having more bits than 17 bits is required.

Therefore, an object of the present invention is to provide a digital filter in which the number of bits of accumulated data output after rounding processing is variable.

[0005]

According to a first aspect of the present invention, the input data is multiplied by predetermined coefficient data n
Number of multipliers, n coefficient latches for supplying coefficient data to each multiplier, and n for accumulating the output of each multiplier.
A plurality of adders, a plurality of delay elements that delay the output of the previous stage adder and output it to the subsequent stage adder, and a plurality of rounding processing units that round the output of the nth adder by a predetermined number of bits. By designating any one of the plurality of rounding processing units, a rounding address decoder for selecting rounding processing bits is provided in the digital filter to achieve the above object.
According to a second aspect of the invention, in the digital filter according to the first aspect, the number of rounding processing units is two, thereby achieving the above object.

[0006]

In the digital filter according to the first aspect, each multiplier multiplies the input data by a predetermined coefficient data.
Each coefficient latch provides coefficient data to each multiplier. Each adder accumulates the output of each multiplier.
The plurality of delay elements delay the output of the adder at the preceding stage and output the delayed output to the adder at the subsequent stage. The rounding address decoder selects a rounding processing bit by designating one of a plurality of rounding processing units. As a result, the rounding processing unit performs the rounding processing on the output of the n-th adder for the selected rounding processing bit. In the digital filter according to the second aspect, one of the two rounding processing units is selected by the rounding address decoder. Then, the rounding process is performed on the selected rounding bit.

[0007]

Embodiments of the digital filter of the present invention will be described in detail below with reference to FIGS. FIG. 1 shows the configuration of a digital filter according to the first embodiment of the present invention. This digital filter has n multipliers 1 ₁ , 1 ₂ , ..., 1 _n for multiplying input data by predetermined coefficient data, and n coefficient latches 2 ₁ for supplying coefficient data to the respective multipliers. 2 ₂ , ... 2 _n
, A coefficient address decoder 3 for decoding the coefficient address 11 to selectively enable the coefficient latches 2 ₁ , 2 ₂ , ..., 2 _n, and n adders for accumulating the outputs of the multipliers. 4 _1, 4 _2, ..., 4 _n, a plurality of retarders 5 ₁ for outputting a predetermined time the output of the preceding adder, for example, one sampling period delay to a subsequent adder, 5 _2, ...,
5 _n-1 .

The multipliers 1 ₁ , 1 ₂ , ..., 1 _n are connected to the data bus 12, and the coefficient latches 2 ₁ , 2 ₂ , ..., 2 _n are connected to the coefficient data bus 13. Adder 4 at the front stage
₁ is for adding the accumulated data 14 and the output data of the multiplier 1 ₁ . The output data of the adder 4 ₁ is delayed by the delay element 5 ₁ for a predetermined time and input to the adder 4 ₂ in the subsequent stage. The adder 4 ₂ adds the output data of the delay element 5 _{1 and} the output data of the multiplier 1 ₂ . Subsequent delay elements 5 ₂ , ..., 5 _n-1 and adders 4 ₃ ,.
_The same applies to _n . The digital filter according to the present embodiment is a rounding operation unit 1 that rounds output data of an adder 4 _n.
It has 0. The rounding operation unit 10 has a rounding processing bit that rounds, for example, 2 bits or 3 bits of the accumulated data supplied from the adder 4 _n . A rounding address decoder 12 that selects a rounding processing bit is connected to the rounding operation unit 10. A rounding address for designating a processing bit is input to the rounding address decoder 12.

FIG. 2 shows the internal structure of the rounding operation unit 10. However, in this example, the multipliers 1 ₁ to 1 _n are set to 3
This is a case in which two pieces (n = 32) of data and coefficient data respectively supplied to each of the multipliers 1 ₁ to 1 ₃₂ are 8 bits. In this example, the carry circuits 100 _{1 to} 100 ₁₈
, 17 are connected as shown in FIG.
_The cumulative data input from ₃₂ to the rounding operation unit 10 is 18
It has become a bit. In this embodiment, the carry circuit 10
0 ₁ is a rounding bit of 2 bits, and the carry circuit 100 ₂ is a rounding bit of 3 bits. These two carry circuits 100 ₁ as rounding processing circuits,
At 100 ₂ , a predetermined signal S from the address decoder 12
The rounding bit is selected by supplying E1 and SE2, respectively. Other carry circuit 100 _{3-100 18} has the same configuration as the carry circuit 18 shown in FIG. 7 (B).

Next, the operation of the embodiment thus constructed will be described. The coefficient address decoder 3 decodes the coefficient address 11 to generate coefficient latches 2 ₁ , 2 ₂ , ..., 2
_n is selectively enabled and the coefficient data on the coefficient data bus 13 is sequentially supplied to the coefficient latches 2 ₁ , 2 ₂ , ..., 2 _n.
To take in. The input data (multiplier) output onto the data bus 12 is the coefficient data (multiplicand) output from the coefficient latches 2 ₁ , 2 ₂ , ..., 2 _n by the multipliers 1 ₁ , 1 ₂ , ..., 1 _n . ). Each multiplier 1 ₁ ,
The outputs of 1 ₂ , ..., 1 _n are adders 4 ₁ , 4 ₂ ,
..., by 4 _n, is added to the output of the cumulative data 14 or the front stage of the adder is output to the subsequent stage.

Assuming that the number of multipliers 1 ₁ to 1 _n is 32 (n = 32), the data supplied to each of the multipliers 1 ₁ to 1 ₃₂ is 8 bits, and the coefficient data is 8 bits, as described above. The cumulative data input from the adder 4 ₃₂ to the rounding operation unit 10 is 18 bits. At this time, in the present embodiment, the rounding address decoder 12 causes the rounding operation unit 10
A rounding process bit of 2 bits or 3 bits is selected and a rounding process is executed to obtain a cumulative data output of 16 bits or 17 bits.

Next, a digital filter according to the second embodiment of the present invention will be described. The same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be appropriately omitted. In the present embodiment, the rounding operation unit 20 has a plurality of rounding processing bits, and the rounding address decoder 22 selects the processing bits in the rounding operation unit 20. That is, when the addition result of the output of the multiplier 1 _n and the accumulated data up to n−1 terms is m bits, the rounding operation unit 20 has processing bits for rounding 0 bits to m−1 bits, and the rounding address The decoder 22 selects a rounding bit from 0 bit to m-1 bit.

FIG. 4 shows the internal structure of the rounding operation unit 20. The rounding operation unit 20 of the present embodiment, as a rounding processing circuit, has a bit number m of accumulated data from the multiplier 1 _n.
It has the same number of m carry circuit 200 ₁ to 200 DEG _m and, carry circuit 200 20 ₁ to 20 to the m-1 th
0 _m-1 performs rounding processing of 0 to _m-1 bits. The rounding processing bit is selected by the rounding address decoder 22 from each carry circuit 200 ₁ to 200.
_This is executed according to the signals SE0 to SEm-1 supplied to _m-1 . FIG. 5 shows a simple circuit example of the rounding operation unit 20.

Next, the operation of the embodiment thus constructed will be described. In the present embodiment, the rounding address decoder 22 selects a rounding bit of 0 bits to m-1 bits in the rounding operation unit 20 to execute a rounding process of 0 to m-1 bits. As a result, it is possible to obtain the accumulated data output from the rounding operation unit 20 in which the rounding processing of 0 to m-1 bits has been executed. In the present embodiment, the rounding operation unit 20 has a plurality of rounding processing bits, and the rounding address decoder 22 selects the rounding bit. Therefore, the rounding processing according to the required number of bits can be performed. it can.

[0015]

According to the digital filter of the present invention, the number of bits of accumulated data output after the rounding process can be changed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital filter according to a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a rounding operation unit of the digital filter.

FIG. 3 is a block diagram showing a digital filter according to a second exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing an internal configuration of a rounding operation unit of the digital filter.

FIG. 5 is a diagram showing a circuit configuration example of the rounding operation unit.

FIG. 6 is a block diagram showing a configuration of a conventional digital filter.

FIG. 7 is a block diagram showing a circuit configuration of a rounding operation unit of the digital filter.

[Explanation of symbols]

_{1 1, 1 2, ...,} 1 n multipliers _{2 1, 2 2, ...,} 2 n coefficient latch 3 coefficient address decoder _{4 1, 4 2, ...,} 4 n adder _{5 1, 5 2, ...,} 5 n _-1 retarders 10, 20 rounding section 12, 22 rounding the address decoder _{100 1 ~100 18, 200 1 ~200} m-1 digit up circuit

Claims (2)

[Claims] 1. N multipliers for multiplying input data by predetermined coefficient data, n coefficient latches for giving coefficient data to each multiplier, and n multipliers for accumulating outputs of the multipliers. An adder, a plurality of delay elements for delaying the output of the previous stage adder and outputting it to the subsequent stage adder, and a plurality of rounding processing units for rounding the output of the nth adder by a predetermined bit. By specifying one of multiple rounding units,
A digital filter, comprising: a rounding address decoder for selecting rounding processing bits. 2. The digital filter according to claim 1, wherein the number of rounding processing units is two.