JPH07111454A - High-speed switching frequency synthesizer circuit - Google Patents

Abstract

PURPOSE:To form the high-speed switching frequency synthesizer circuit by setting forcibly a frequency division ratio of a prescaler at the start of operation and resetting a program counter and a swallow counter of a comparison frequency divider in the initial state, thereby improving the leading speed to a set frequency. CONSTITUTION:A prescaler 3 frequency-divides an output frequency fVCO and a comparison frequency divider 4 frequency-divides the output frequency fVCO and the frequency divider 4 frequency-divides a frequency division output of the prescaler 3 to generate a signal of a comparison frequency division frequency fV and a phase comparator 5 compares a phase of the signal of a reference frequency fr with a phase of a signal of the comparison frequency division frequency fV to provide an error output and a VCO 7 controls a generated frequency depending on the error output to generate the output frequency fVCO. The frequency divider 4 resets the program counter 11 and the swallow counter 12 in the initial state. Thus, the leading speed to the set frequency is improved to form the high-speed frequency synthesizer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer circuit, and more particularly to a high speed switching frequency synthesizer circuit capable of switching frequencies at high speed.

The frequency synthesizer circuit is capable of generating a highly accurate variable frequency controlled by a reference oscillator, and is widely used in communication devices and various electronic circuits.

In some applications, such a frequency synthesizer circuit is required to be able to perform high-speed switching to a designated frequency when switching frequencies.

[0004]

2. Description of the Related Art In a communication device or the like, it is sometimes necessary to start up to a designated channel frequency or switch the channel frequency at high speed. In such a frequency synthesizer circuit, it is necessary to perform frequency switching at high speed.

FIG. 4 shows a conventional frequency synthesizer circuit. Reference numeral 1 denotes a reference oscillator, which is composed of, for example, a crystal controlled oscillator or the like, and generates a signal having a reference frequency. 2 is a reference divider, the output frequency of the reference oscillator 1 by dividing, for generating a signal of a reference divider frequency f _r.
A prescaler 3 divides the output frequency f _VCO of the frequency synthesizer circuit by the division ratio P or P + 1.

Reference numeral 4 denotes a comparison frequency divider, which is a prescaler 3
The output frequency is further divided to generate a signal having a comparison division frequency f _v . Reference numeral 5 denotes a phase comparator, which compares the phase of the signal of the reference frequency division frequency f _r of the reference frequency divider 2 and the phase of the signal of the comparison frequency division frequency f _v of the comparison frequency divider 4 to obtain a phase error. Generate a voltage signal having a proportional magnitude. Reference numeral 6 denotes a loop filter, which band-limits the output signal of the phase comparator 5 and generates a control signal composed of a DC component.

7 is a voltage controlled oscillator (VCO),
Its output frequency is controlled by the output signal of the loop filter 6, and an output signal of the frequency f _VCO is generated. Reference numeral 8 denotes a charge pump, which has the function of speeding up the rise of the output of the loop filter 6 by charging / discharging the capacitor of the loop filter 6 to a predetermined value when the frequency is switched.

The frequency division ratio of the prescaler 3 can take one of two values P and P + 1, for example P = 6.
4, P + 1 = 65 is used. At the start of the operation, the frequency division ratio of the prescaler 3 is indefinite, and the comparison frequency divider 4
Recognizes the frequency division ratio of the prescaler 3 and performs the frequency division operation. During operation, the frequency division ratio of the prescaler 3 is calculated by the comparison frequency divider 4
It can be switched according to the control from.

CLK is a clock signal and is used to determine the operation timing of each unit. DATA is data that determines the frequency division ratio in the reference frequency divider 2 and the comparison frequency divider 4, and is externally given according to the channel frequency to be generated by the frequency synthesizer circuit. STB
Is a strobe signal, by which data is read in the reference frequency divider 2 and the comparison frequency divider 4. PS is a power save signal, whereby the frequency synthesizer circuit is stopped except for the reference oscillator 1, and power consumption is saved.

FIG. 5 shows an example of the structure of the comparison frequency divider, in which the same components as those in FIG.
In the comparison frequency divider 4, 11 is a program counter, 1
Reference numeral 2 is a swallow counter, and 13 is a controller.

At the time of switching the channel frequency of the communication device or at the time of starting from a power save state to an operating state for saving power consumption, the program counter 11 and the swallow counter 12 are provided with a required output frequency f _VCO of the _{VCO 7} . Then, the predetermined values N and A are set, and the prescaler 3 and the comparison frequency divider 4 _{divide the} output frequency f _VCO by the following relationship to generate a signal of the comparison frequency division frequency f _v . f _VCO = f _v (P · N + A) (1)

When the output frequency f _VCO is equal to the set value, the comparison frequency division frequency f _v is equal to the reference frequency division frequency f _r, and therefore f _VCO = f _r (P · N + A) (2) . Where P · N defines a rough dividing ratio, A becomes remainder term for P · N, the value of A varies 1, the frequency f _VCO is changed by f _r.

On the other hand, since f _VCO = f _v {(P + 1) · A + (NA) · P} (3) from the equation (1), the output frequency f _VCO is set by the equation (1) as follows: It can be done as follows.

At the start of operation, the controller 13 recognizes the frequency division ratio in the prescaler 3 and operates the program counter 11 or the swallow counter 12 in accordance with this.

First, when the frequency division ratio of the prescaler 3 is P + 1, the output pulse of the prescaler 3 is counted by the swallow counter 12, and when the count value becomes A, the controller 13 causes the frequency division ratio of the prescaler 3 to change. To P. Next, by the program counter 11,
The output pulse of the prescaler 3 is counted, and when the count value becomes N−A, the counting is finished.

First, when the frequency division ratio of the prescaler 3 is P, the program counter 11 counts the output pulses of the prescaler 3 and the count value is N.
-When it becomes A, the controller 13 is the prescaler 3
The division ratio of is changed to P + 1. Next, swallow counter 12
Count the output pulses of prescaler 3 by
When the count value reaches A, the counting ends.

[0017]

[Problems to be Solved by the Invention] Frequency synthesizer circuit
On the road, when starting from a power save state, etc.
First, the reference frequency division frequency f_rAdjust the signal phase of
Then, the comparison division frequency f _vTo be in phase with the signal of
Then, after that, set the frequency according to equation (3).
Output frequency f_VCOThe rising edge of

On the other hand, the operation of the program counter 11 and the swallow counter 12 in the comparison frequency divider 4 is performed according to the equation (3), and the order is first whether the frequency division ratio in the prescaler 3 is P or P + 1. Determined by
Conventionally, the first frequency division ratio in the prescaler 3 was indefinite, so the controller 13 identifies the frequency division ratio in the prescaler 3 at the start of operation, and then determines the operation sequence of the program counter 11 and the swallow counter 12. Need to do so, so it took time.

Further, in the conventional frequency synthesizer circuit shown in FIGS. 4 and 5, the program counter 11 and the swallow counter 12 do not reset at the start of operation, but start counting from the count value at that time. .
Therefore, each counter starts counting, restarts counting from the state of reaching full count and returning to 0, the swallow counter 12 counts the set value A, and the program counter 11 sets the set value (NA). Since it counts, there were times when wasted time was spent.

Therefore, in the conventional frequency synthesizer circuit, depending on the state of the count value of each counter at the start of the operation, it may take some time until the phase pull-in to the set frequency is finally completed. There was a problem that the startup from the power saving state was delayed when switching the channel frequency.

The present invention is intended to solve the problems of the prior art, and provides a high speed switching frequency synthesizer circuit capable of speeding up a rise to a predetermined frequency in a frequency synthesizer circuit. Is intended.

[0022]

[Means for Solving the Problems]

 (1) The present invention, as shown in FIG.
Force frequency f_VCOPrescaler 3 and the prescaler
Frequency-divided frequency f _vSignal of
And the reference frequency f_rSignal and ratio
Frequency division frequency f _vGenerates an error output by comparing the phase of the
The generated phase comparator 5 and the generated frequency according to the error output
Controlled output frequency f_VCOWith VCO7 to generate
Comparing frequency divider in a large frequency synthesizer circuit
4 is a program counter for counting the set value N-A
11 and a swallow counter 12 for counting the set value A
When the program counter 11 has finished counting,
Change the dividing ratio of the rescaler 3 to P, and swallow counter 1
At the end of counting 2, the division ratio of prescaler 3 is changed to P.
In addition, f_VCO= F_v{(P + 1) ・ A + (NA) ・
P division frequency f_vWhen the signal of
At the start of the operation, set the division ratio of the prescaler 3 to P or P
It is provided with an initial setting section 9 for setting to either +1.
is there.

(2) Further, in the present invention according to (1), the count values of the program counter 11 and the swallow counter 12 are reset to 0 when the operation of the comparison frequency divider 4 is started.

[0024]

[Action]

(1) In the frequency synthesizer circuit, the prescaler 3 divides the output frequency f _VCO , and the comparison frequency divider 4
The frequency-divided output of the prescaler 3 to generate a signal having a comparison frequency division frequency f _v .
An error output is generated by phase-comparing the signal of the reference frequency f _{r and} the signal of the comparison frequency division frequency f _v , and the VCO 7 controls the generation frequency according to the error output to output the output frequency f.
Generate _VCO .

In the comparison frequency divider 4, the program counter 11 counts the set value NA, the swallow counter 12 counts the set value A, and at the end of the count of the program counter 11, the prescaler 3 counts. By changing the division ratio to P and changing the division ratio of the prescaler 3 to P when the count of the swallow counter 12 is finished, a signal of the comparison division frequency f _v is generated according to the relationship of the expression (3).

At this time, in the fast switching frequency synthesizer circuit of the present invention, the initial setting section 9 is provided to set the frequency division ratio of the prescaler 3 to either P or P + 1 at the start of the operation.

Therefore, according to the present invention, it is not necessary for the comparison frequency divider 4 to recognize the frequency division ratio in the prescaler 3 at the start of the operation and determine the operation sequence of the program counter 11 and the swallow counter 12, so that the frequency It is possible to speed up the start-up to the designated frequency in the synthesizer circuit.

(2) In the fast switching frequency synthesizer circuit of the present invention, in the configuration of (1), the count values of the program counter 11 and the swallow counter 12 are reset to 0 at the start of operation.

Therefore, according to the present invention, since the count of the program counter 11 and the count of the swallow counter 12 at the time of operation are performed quickly, it is possible to improve the rising speed to the designated frequency in the frequency synthesizer circuit. You can

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows an embodiment of the present invention, in which only the essential parts are shown. The same parts as those in FIG. 5 are indicated by the same numbers, and 9 is an initial setting unit for setting an initial value of the frequency division ratio in the prescaler 3.

The initial setting section 9 sets the initial value of the frequency division ratio in the prescaler 3. Therefore, at the start of the operation of the frequency synthesizer circuit, the controller 13 determines the program counter 11 and the swallow counter 12 according to the initial value.
To start counting.

As described above, the operations of the program counter 11 and the swallow counter 12 in the comparison frequency divider 4 are (3)
According to the equation, the order is initially determined by whether the division ratio in the prescaler 3 is P or P + 1. Conventionally, the first frequency division ratio in the prescaler 3 was indefinite, so the controller 13 needs to identify the frequency division ratio in the prescaler 3 and then determine the operation sequence of the program counter 11 and the swallow counter 12. However, in the present invention, since the first frequency division ratio in the prescaler 3 is set by the initial setting unit 9 at the time of starting the operation, the program counter 11 and the swallow counter 12 should start the operation immediately accordingly. Therefore, it is possible to improve the frequency rising speed in the frequency synthesizer circuit.

Further, in the comparison frequency divider 4, the controller 13 controls the program counter 11 and the swallow counter 12 when the strobe signal STB in the frequency synthesizer circuit or the active signal ACTIVE given at the time of rising from the power save state is generated. A reset signal is generated to reset each count state to 0.
Reset to.

Therefore, at the time of setting the channel frequency for the frequency synthesizer circuit or at the time of starting from the power save state, the program counter 11 and the swallow counter 12 in the comparison frequency divider 4 start counting from the reset state. Since the predetermined frequency dividing operation is performed, it is possible to accelerate the rise to the predetermined frequency as compared with the conventional frequency synthesizer circuit in which the program counter 11 and the swallow counter 12 are not reset.

FIG. 3 shows the operation timing of the frequency synthesizer circuit to which the present invention is applied, and explains the operation when the designated frequency is raised from the power save state.

When the power save signal PS is off,
The frequency division ratio of the prescaler 3 is determined by the operating state at that time. When the power save signal PS is on, the frequency division ratio of the prescaler 3 is P = 64 or P + 1 = 65.
It takes any value of and is indefinite.

However, when the frequency is raised to the designated frequency, the frequency division ratio of the prescaler 3 is forcibly set to either P or P + 1 by the initial setting section 9, and is set to 64 as shown in FIG. 3, for example. Become.

In this state, the generation of the active signal ACTIVE instructing the rise from the power save state causes the phase comparator 5 to perform the initial phase adjustment, and the comparison frequency divider 4 starts its operation.

[0039]

As described above, according to the present invention, in the frequency synthesizer circuit, the frequency division ratio of the prescaler is forcibly set at the start of operation, and the program counter and the swallow counter in the comparison frequency divider are set. Since the resetting is performed in the initial state, the rising speed to the set frequency can be improved, and the high-speed switching frequency synthesizer circuit can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing an operation timing of a frequency synthesizer circuit to which the present invention is applied.

FIG. 4 is a diagram showing a conventional frequency synthesizer circuit.

FIG. 5 is a diagram illustrating a configuration example of a comparison frequency divider.

[Explanation of Codes] 3 Prescaler 4 Comparison Divider 5 Phase Comparator 7 VCO 11 Program Counter 12 Swallow Counter

Claims (2)

[Claims] 1. A prescaler (3) for dividing an output frequency (f _VCO ) and a comparison component for dividing a divided output of the prescaler (3) to generate a signal of a comparison division frequency (f _v ). A frequency divider (4), a phase comparator (5) for phase-comparing the signal of the reference frequency ( _fr ) and the signal of the comparison frequency division frequency ( _fv ) to generate an error output, and the phase comparator (5) A frequency synthesizer circuit comprising: a VCO (7) which controls a generation frequency in accordance with the output frequency (f _VCO ) to generate a signal of the output frequency (f _VCO ). ) And a swallow counter (12) that counts a set value (A). When the count of the program counter (11) is completed, the frequency division ratio of the prescaler (3) is changed. Change to (P + 1), and the swallow counter At the end of the counting 12), by changing the division ratio of the prescaler (3) to _{(P), f VCO = f} v {(P + 1) · A + (N-A) · P} wherein the comparison frequency divider frequency by When the signal of (f _v ) is generated, the frequency division ratio of the prescaler (3) is set to (P) at the start of operation.
Alternatively, a fast switching frequency synthesizer circuit is provided with an initial setting section (9) for setting either (P + 1). 2. The high speed switching frequency synthesizer circuit according to claim 1, wherein when the operation of the comparison frequency divider (4) is started, the count values of the program counter (11) and the swallow counter (12) are set to 0. A high-speed switching frequency synthesizer circuit characterized by being reset.