JPH0678533A - Dc/dc converter - Google Patents

Abstract

PURPOSE:To reduce the rated voltage of each switching means of a DC/DC converter, by minimizing the voltage stress applied to each switching means. CONSTITUTION:Switches Q1, Q2 having capacitors C1, C2 respectively are connected with each other in the form of a totempole. The switch Q1 and a transformer T1 are so connected by a blocking capacitor C3 as to insert the capacitor in between the switch and transformer. Thereby, the source-drain voltage of a FET S1 when operating is restricted to at most an input voltage VS added to the voltage drop of a diode DI. Similarly, the source-drain voltage of a FET S2 when operating is restricted to at most the input voltage VS added to the voltage drop of a diode D2 too.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called resonance type DC / DC converter capable of achieving a high switching frequency in the MHz region.

[0002]

2. Description of the Related Art Conventionally, the trend of DC / DC converter technology has been directed to a high switching frequency in the MHz region in order to reduce the shape and weight of a magnetic or filter element. However, conventional pulse width modulation (PW
In M) converters, very high switching losses have generally made it impossible to use them in these high frequency regions. For this reason, recently
IEEE Power Electronics Bulletin Vo. 1. P
E-1, January 1987, pages 62-71, K.K. H. Riu, Organty, F.M. C. Lee's Topology and Characteristics of Quasi-Resonant Converters
Or K. H. Liu, F. C. Lee, US Pat.
Zero current switching quasi-resonant converter (ZCS-Q
RC) or IEEE PESC record 19
K. K., published on pages 58-70 of the June 1986 issue. H.
Liu, F. C. Lee, "Zero Voltage Switching Techniques in DC / DC Converters" and W. W., IEEE Power Electronics Specialist Conference, Blacksburg, Va., Pp. 404-413. A. Davids, P. Grazky, F.F. C. Lee's "Zero Voltage Switch Quasi-Resonant Buck or Flyback Converter-Experimental Results at 10MHz"
Zero-Voltage Switching Quasi-Resonant Converter (ZVS-QRC) or IEEE / PE
SC Conference 1988, W. A. Davids, F.F. C. Lee's "Zero Voltage Switching Multi-Resonance Technology: A Novel Approach for Performance Improvement in High Frequency Quasi-Resonant Converters", Power Electronics NO-1,
As described on pages 141 to 150 of the January 1991 issue,
Researchers are paying attention to resonant switches such as the latest type of zero-voltage switching multi-resonant converter introduced by "Constant frequency control of quasi-resonant converter" by Dorakan Makshimovich and Slobodan Cook. Also, four switches are required, I
EEE Power Electronics Specialist Conference, 1987, pages 424-430,
O. D. Patterson, D. M. "Quasi-Resonant Full Bridge DC / DC Converter" by Devan, Bassett, John A. European Patent 0 428
The "new PWM topology featuring zero voltage switching and constant switching frequency" known from 377 A2 is also a converter of noteworthy value.

FIG. 12 shows the above-mentioned European Patent 0 428 37.
7 shows a DC / DC converter using an insulation type transformer proposed in No. 7 A2. Reference numeral 1 is an insulation type transformer having a primary winding 1A on the primary side and a secondary winding 1B on the secondary side. The primary winding 1A and the MOS type FE
By connecting the series circuit with T2 to both ends of the DC input power source 3, the DC input voltage VIN from the DC input power source 3 is selectively applied to the primary winding 1A of the transformer 1. Also,
Between the primary winding 1A, capacitors 4 and M, which are capacitive elements,
A series circuit with the OS type FET5 is connected to these FETs.
The capacitors 2 and 5 include capacitors 6 and 7, which are inherent capacitances, and diodes 8 and 9, respectively, and the FET 2 and the diode 8 form a first switching means, while the FET 5 and the diode 9 form a second switching means. Switching means is configured.

On the other hand, on the secondary side of the transformer 1, a filter circuit 10 is connected to the secondary winding 1B via rectifying diodes 11 and 12, and the filter circuit 10 includes an inductor 13 and a smoothing capacitor. Consisting of 14 and. Then, by switching the FETs 2 and 5 by a control circuit (not shown), the voltage induced in the secondary winding 1B is output as the DC output voltage Vout via the diodes 11 and 12 and the filter circuit 10. At this time, FET
Before turning on 2, the primary winding 1 of the transformer 1
If the capacitor 6 is discharged by the energy stored in A and the capacitor 7 is discharged by the energy stored in the primary winding 1A before the FET 5 is turned on, zero voltage switching is achieved. At the same time, the switching loss in each FET 2, 5 is minimized.

The principle behind each of these converters is that either the current or the voltage is set to zero before the active elements 2 and 5 composed of MOS type FETs are turned on, and the switching elements 2 and 5 are turned off. It is to perform soft switching in the meantime. That is, the leakage inductance that is inherent in the isolation transformer and the parasitic capacitances 6 and 7 of the switching elements 2 and 5 are commonly used to achieve the zero voltage / current switching mechanism. The switching loss at is approximately zero in these converters.

[0006]

In the circuit shown in the above-mentioned prior art, the voltage Vc across the capacitor 4 is
If the duty for the FETs 2 and 5 is D, Vc =
It becomes VIN × D / (1-D). If the duty D is 0.5 and the voltage Vc of the capacitor 4 is the input voltage VIN
When the FET2 is turned on, the capacitor 4 is charged so that the drain potential of the FET5 is + VIN when the source of the FET2 is the reference potential.
Therefore, a voltage twice the input voltage VIN is applied between the source and drain of the FET 5. On the other hand, when the FET 2 is off, the drain potential of the FET 5 becomes −VIN when the source of the FET 2 is used as a reference potential by discharging the capacitor 4, so that the input voltage VIN is also applied between the source and drain of the FET 2. Double the voltage is applied.
In other words, by switching the FETs 2 and 5, this FE
Since a voltage stress at least twice the input voltage VIN is applied between the source and drain of T2 and T5, switching elements 2 and 5 having a larger rated voltage must be used, and in addition, the FET2 , 5 has a large on-resistance, so that the primary side power loss of the transformer 1 increases.

Therefore, the present invention solves the above problems,
An object of the present invention is to provide a DC / DC converter capable of minimizing the voltage stress applied between each switching means and reducing the rated voltage thereof without impairing the advantages of the resonant converter.

[0008]

SUMMARY OF THE INVENTION The present invention is a DC input power supply, a transformer having a primary side and a secondary side, and a primary capacitance of the transformer which includes an inherent capacitance and selectively powers from the DC input power supply. A first switching means applied to the winding; a capacitive element inserted and connected between the primary winding of the transformer and the first switching means; and a primary winding of the transformer including an inherent capacitance; A second switching means connected to both ends of a series circuit with the switching means, a rectifier circuit connected to the secondary side of the transformer, and a capacitive or inductive filter circuit connected to the rectifier circuit. The first switching means and the second switching means are alternately turned on at predetermined time intervals, and a certain dead band between them is turned on. Those configured to stationary.

[0009]

With the above structure, when the first switching means and the second switching means are switched, the voltage applied between the respective switching means is
It is approximately equal to the input voltage from the power supply, and zero voltage switching is achieved in this state.

[0010]

Embodiments of the present invention will be described below with reference to FIGS.

1 to 6 show the DC / D according to the present invention.
1 shows a first embodiment of a C converter. FIG. 1 shows a circuit diagram of a soft switch converter with a capacitive filter, frequency control and proposed novel asymmetric pulse width modulation (PWM) control (D, 1-D).
It is a new DC / DC converter topology that can be applied to both. In the figure, VS is a DC input power source as a power source, and the power from this DC input power source VS is M
It is selectively applied to the primary winding of the transformer T1 by the OS type FET S1. Also, the primary winding of the transformer T1 and the FE
A blocking capacitor C3, which is a capacitive element, is inserted and connected between TS1 and TS1.
A MOS type FET S2 is connected to both ends of a series circuit constituted by 3 and the primary winding of the transformer T1. Each of the FETs S1 and S2 has capacitors C1 and C2 as its own capacitance and diodes D1 and D2.
And the diodes D1 and D2 are MOS type FETS.
It is possible to use a body diode built in 1, S2 or an external diode. Also,
The capacitors C1 and C2 are capacitor elements C on the output side.
It can be configured with o. A switch Q1 as a first switching means is used to represent the diode D1 and the FET S1 as a whole, and similarly, a diode D2 and a FET S2 are represented as a switch Q2 as a second switching means.

Since the switches Q1 and Q2 are connected in a totem pole type, there is no additional loss in the rated voltage of the device. The switches Q1 and Q2 are alternately turned on, and there is a dead band between them to allow voltage transfer, so that zero voltage switching can be achieved. The capacitor C3 acts as an energy source for part of the operating cycle. The other function of this capacitor C3 is the transformer T1.
Is to act as a blocking capacitor to avoid saturation. Further, under the steady operation state, the magnetizing current of the transformer T1 is automatically set to an appropriate value so that the average amount of charge absorbed / exhausted by the capacitor C3 becomes equal to zero throughout one cycle. The inductor L can use the leakage inductance of the transformer T1 and can be increased by an external inductor if necessary. This inductor L is used to achieve zero voltage switching of the device.

The secondary side current of the transformer T1 is rectified by a center tap type rectifier circuit in which diodes D3 and D4 are connected to both ends of the secondary winding of the transformer T1 and a capacitor which is a direct capacitive filter circuit is rectified. Supplied to CO. An important advantage of this output method is that the output side diodes D3 and D4 are ideally limited to twice the output voltage Vo. Therefore, the low forward voltage drop of the diodes D3, D4 is used to improve the overall efficiency.

Switch Q1 is at intervals of time DT, and
Switch Q2 is alternately turned on at intervals of time (1-D) T so that there is a certain dead band in between. The change of D is based on the duty cycle during operation, and by changing the duty cycle D, control of the output is achieved. Such control is different from the conventional "quasi-resonant full-bridge DC / DC converter" in which each pair of switches is turned on at an interval of time DT. The operation of the circuit is actually asymmetric for duty cycles D between 0% and 50% and between 50% and 100%.
Thus, the full range of control can be achieved with a duty cycle D of 50% to 100% and 0% to 50% and the converter operation is analyzed for only one of the duty cycle D ranges. It is necessary. In the following explanation, the range of duty cycle D is 0
% To 50%.

Next, the operating principle of the circuit in FIG. 1 will be described. First, as the basic operation of this circuit, the following assumptions are established.

Ignore the secondary side leakage inductance of the transformer T1.

The forward drop of the output side diodes D3, D4 and the junction capacitance shall be ignored.

The blocking capacitor C3 has a voltage Vc across the capacitor C3 that is substantially constant, and is large enough to ignore ripples.

A large capacitor Co is used so that the output voltage Vo is constant.

The magnetizing inductance LM is the magnetizing current I
Use a large one such that M is almost constant.

By ignoring the voltage ripple, the voltage VC applied to the blocking capacitor C3 is D × V
DC voltage is almost equal to S.

Waveforms of the circuit in FIG. 1 based on the operating state are shown in FIGS. 2 and 3. In each of these states, the circuit of FIG. 1 undergoes various topological modes during one cycle of operation. 2 and 3, the approximate current conversion ratio of the circuit is shown by the following mathematical formula.

[0023]

[Equation 1]

[0024]

[Equation 2]

However, VO = output side voltage, VS = input side DC voltage, n = transformer winding ratio, fs = switching frequency, D = duty cycle of switch Q1.

FIG. 4 illustrates the scheme for the various topological modes that the circuit of FIG. 1 goes through. The operation of the circuit can be described as follows. First, assume the circuit is in the mode 1 state in FIG. 4a.
This mode is common to both FIG. 2 and FIG. In mode 1, switch Q1 (F
The ETS1 or diode D1) and the diode D3 are turned on, while the switch Q2 (FETS2 or diode D2) and the diode D4 are turned off. The inductor current iL rises and rises at a predetermined rate from the level of the magnetizing current IM as shown in the following equation until the switch Q1 is switched off.

[0027]

[Equation 3]

[0028]

[Equation 4]

However, VO '= output voltage reflected on the primary side, VC = constant DC voltage applied to the capacitor C3,
iL = primary-side inductance current.

Immediately, the inductor L becomes the capacitor C1,
Resonating with C2, the converter is in the mode 2 state of Figure 4b. First, the current flowing through the FET S1 is switched to charge / discharge the capacitors C1 and C2, respectively. Capacitor C1 acts as a lossless snubber for FET S1, thereby achieving soft switching with the switch turned off. Ordinary capacitor C1,
Since C2 is a very small value, the duration of this resonance is usually very short. First, the input supply voltage VS
The capacitor C2 to which is applied discharges to zero volts, and the capacitor C1 charges to the input voltage VS. When the capacitor C2 is completely discharged, the circuit moves to mode 3 in FIG. 4c and the diode D2 of the switch Q2 starts to conduct. Thereafter, before the inductor current iL changes its polarity, FETS2 performs zero voltage switching.
Here, the inductor current iL has a descending slope shown in the following equation.

[0031]

[Equation 5]

In this mode, the inductor current iL becomes equal to the magnetizing current IM and the current i flowing through the diode D3 is
Continue until D3 matches zero amps. From this state, the voltage VC of the blocking capacitor C3 (D × VS
) Is greater or less than the output voltage VO 'reflected on the primary side, the circuit transitions to either mode 4 of Figure 4d or mode 7 of Figure 4g. Probably, in the light load state where the duty is small, the voltage Vc of the blocking capacitor C3 becomes smaller than the output voltage VO 'reflected on the primary side, and as a result, the circuit shifts to the mode 7. On the other hand, if the voltage Vc of the blocking capacitor C3 is larger than the output voltage VO 'reflected on the primary side, the mode 4 is entered. Assuming a transition to mode 4 of Figure 4d,
The diode D4 begins to conduct. Inductor current iL
Slops down at a new rate as shown in the following equation.

[0033]

[Equation 6]

When FETS2 is turned off, this mode ceases and the circuit transitions to mode 5 in Figure 4e. Again in this mode 5, the inductor L is connected to the capacitor C.
1 and C2 resonate, but in the opposite direction compared to mode 2. In this mode, FETS2 turns on softly and FETS1 turns on losslessly. As soon as the voltage on the capacitor C1 reaches zero volts, the diode D1 begins to conduct and the circuit goes into mode 6 in FIG. 4f. At this point, until the inductor current iL again equals the magnetizing current IM and the current iD4 through the diode D4 decreases to zero, the inductor current iL ramps up as Complete the cycle.

[0035]

[Equation 7]

Following Mode 3, if the voltage VC on blocking capacitor C3 is less than or equal to the output voltage VO 'reflected on the primary side, the circuit selectively transitions to Mode 7 of FIG. 4g. . Magnetizing inductance L
Since M is much larger than the inductor L, the voltage VX of the transformer T1 is the voltage VX of the blocking capacitor C3.
Equal to the negative voltage on C. The magnetizing inductance LM is large, and as a result, the inductor current iL decreases as shown by the following equation and becomes substantially zero.

[0037]

[Equation 8]

Therefore, the inductor current iL exhibits a substantially constant value and becomes equal to the magnetizing current IM. Then, this constant state is maintained until the switch Q2 is switched off again. The circuit then transitions to mode 2 in Figure 4b, where the inductor L resonates with the capacitors C1, C2. When the voltage applied to capacitor C2 reaches zero volts, the circuit returns to mode 1, which causes it to operate at one
The cycle is complete.

As mentioned above, the circuit of FIG. 1 can also be operated under a fixed duty cycle D with variable frequency control. Duty cycle D
Can be any value, but the effective current is the lowest, and a duty D of about 50%, which achieves the highest efficiency by this, is sensible. However, IEEE
E Power Electronics Bulletin Vol. 4, NO.
4, October 1987, pages 459-469, M.S.
M. Jovanovich, W. A. Davids, F.F. C. In the half-bridge type zero-voltage switching quasi-resonant converter described in "High-frequency offline power conversion using zero-voltage switching quasi-resonant type and multi-resonant type technology" by Lee, the frequency control method uses an input voltage VS. And can vary over a wide frequency range due to variations in load RL. Therefore, this control method is only a good candidate for use in a limited load range.

The method proposed to solve the above-mentioned problem of the wide frequency range is to introduce a frequency control mechanism that changes only in response to fluctuations in the input voltage VS. This causes the range of frequencies to be controlled to be narrower, i.e. the converter is PWM
Operates against load variations under control.

When the FETS1 is on and the FETS2 is off, the source-drain voltage of the FETS2 is the input voltage VS plus a voltage drop due to the diode D1 of the switch Q1, and the FETS1 is off and the FETS2 is on. In this state, the source-drain voltage of the FET S1 is similarly added to the input voltage VS by the voltage drop due to the diode D2 of the switch Q2. That is, the charge / discharge voltage of the capacitor C3 is not directly applied between the source and drain of the FETs S1 and S2 in any case, and the FETs S1 and S2 are not directly applied.
The voltage stress on the circuit is much smaller than that of the conventional circuit.

Next, experimental results for the circuit shown in FIG. 1 will be described. As a new soft switch converter, a converter with an output of 50 W has an input range of 42 V to 63
Designed for V, output 5V, load range 0-10A. The parts used for the power stage are shown in the table below.

[0043]

[Table 1]

FIG. 5 shows current and voltage waveforms of the circuit in FIG. In the figure, the upper stage is the inductor current iL, the middle stage is the gate-source voltage VGS1 and the drain-source voltage VDS1 of the switch Q1, and the lower stage is the gate-source voltage VGS2 and the drain-source voltage VDS2 of the switch Q2. Waveforms were measured under conditions of 42V input, 5V output, and 10A load range.
Further, the duty is about 50% in the operating state.

The upper waveform in FIG. 5 is for the inductor current iL, and its shape is the triangular wave shape predicted in the theoretical analysis. The voltage waveform in the middle of FIG. 5 drops to zero before switch Q1 turns on, and
The drain-source voltage VDS1 of the switch Q1 gradually increases at turn-on. This proves that the switch Q1 is losslessly switched. On the other hand, the lower waveform shows the switch Q
It is shown that zero voltage switching is being performed on No. 2.

FIG. 6 shows the efficiency vs. output power curve at each input voltage VS. The solid line indicates that the converter has input voltage V
For the whole S, it shows that it is operating under fixed frequency operation, and the dotted line is for different input voltage VS.
It shows operation under different frequencies. It can be seen that this circuit has the highest efficiency when the input voltage VS is 42 V, the frequency is 142 kHz, and the full load state. This allows an efficiency of about 85% to be achieved, excluding gate drive losses. However, if the input voltage VS is 50V and 63
The other two solid lines at V show a decrease in efficiency with increasing input voltage VS. This is because the higher input voltage VS causes the circuit to operate at a lower duty under full load conditions. The effective current of the circuit becomes higher than that when the duty is about 50% and the input voltage VS is 42V, and as a result, the efficiency is deteriorated.

The dotted lines show the switching frequencies of 2
It shows the improved efficiency for input voltages VS of 50V and 43V when increasing to 45kHz and 335kHz. The increased frequency allows the circuit to actually operate at higher duty, ultimately reducing the effective current of the circuit. That is, it is suitable for the circuit if the switching frequency changes based on the input voltage VS.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows an inductive filter type topology and FIG. 8 shows each current and voltage waveform for different modes of operation under the proposed asymmetric duty cycle PWM control. The filter on the output side in FIG. 1 is changed from a capacitive filter to an inductive filter. The secondary side current of the transformer T1 is rectified and supplied to the inductive filter formed by the inductor L0 and the capacitor C0. An important advantage of this topology, which requires an additional inductor LO in this scheme, is that the primary and secondary currents approach a square wave. The control method proposed for the circuit in this embodiment is a novel asymmetric type pulse width modulation control method (D, 1-D), which is used in the half bridge type zero voltage switching quasi-resonant converter. This solves the problem that a large control frequency is changed. During operation of each switch Q1 and Q2, the first of zero voltage switching, constant frequency, and low voltage stress
Most of the features of the circuit in the embodiment are retained in this circuit. Furthermore, the rectangular current waveforms on the primary and secondary sides are
It provides a lower effective current, which allows lower conduction losses for power semiconductor devices and other devices. The approximate voltage conversion ratio is expressed by the following equation.

[0049]

[Equation 9]

However, the duty cycle is D = Q1. As shown in FIG. 8, the circuit only has one sequence to perform its operation,
The actual operating mode in this circuit is very complicated. However, this can be clearly explained by the eight basic modes of operation, and an illustration for each topological mode is shown in FIG. The hypotheses made in the circuit 1 for the capacitor C3, the magnetizing inductance LM and the forward voltage drop VF are used as they are in the following description.

Assume that the circuit is in Mode 1 state, as shown in FIG. 9a. In this mode, the FET
The S1 turns on and the FET S2 turns off. The output current flows through the diode D3, and the primary-side inductor current iL rises and rises based on the inclination of Lo. This slope is approximated by the following equation.

[0052]

[Equation 10]

However, Lo = the inductance of the output side filter. When FET S1 is turned off, the circuit moves to mode 2 shown in FIG. 9b, where the continuous current in inductor L discharges / charges capacitors C2 and C1 linearly. The voltage of the capacitor C2, that is, the input voltage VS is
The capacitor C3 is quickly discharged to the voltage Vc, while the capacitor C1 is charged to a voltage (VS-VC).
After that, the converter goes to mode 3 shown in Figure 9c,
The voltage Vx of the transformer T1 is clamped to zero volt, and the inductor L resonates with the capacitors C1 and C2 by the time the voltage of the capacitor C2 reaches zero volt. The interval time between mode 2 and mode 3 is usually very short because of the low values of capacitors C1 and C2 and the reasonably high inductor current iL. Capacitor C2
When is discharged to zero volt, the body diode D2 of the switch Q2 gives off a current. While diode D2 is conducting, FET S2 is turned on, which results in zero voltage switching.

The conduction between the diode D2 and the FET S2 is
The operation in Mode 4 of the present converter shown in FIG. 9d will be described. In this mode, the transformer T1 remains short circuited, so that both output side diodes D3, D4 are conducting, allowing the core of the output side inductor LO to reset. During this mode, the voltage of the primary side inductance L is clamped at VC and the inductor current iL
Is inclined downward at a predetermined rate as shown in the following formula.

[0055]

[Equation 11]

While the inductor current iL is changing, the current iD3 in the diode D3 slopes down, while the current iD4 in the diode D4 slopes up until the current iD4 = iO flowing through the diode D4.
In mode 5 shown in FIG. 9e, the diode D3 is completely turned off, and the voltage VX of the transformer T1 reverses its polarity from zero volt to the negative voltage of the voltage VC of the capacitor C3. At this time, the inductor current iL further declines and slopes at a gentle rate as shown in the following equation.

[0057]

[Equation 12]

In mode 6 shown in FIG. 9f, S2 is switched off and, as in mode 2, the negative continuous inductor current iL causes the capacitor C1 / C2 to become (VS -VC) / Vc.
Charge / discharge to each voltage. Thereafter, the mode 7 shown in FIG. 7g is entered, while the capacitor C2 is charged to VS by resonance.

When body diode D1 conducts, switch Q1 turns on in mode 8. In this mode, the voltage VX of the transformer T1 is short-circuited so that the inductor LO of the output filter can be reset as in the mode 4. However, the inductor current iL at this time rises and inclines at the rate shown in the following equation.

[0060]

[Equation 13]

At this point, the cycle of the entire operation is completed.
Also, during operation, like the circuit in FIG.
When FETS1 is on and FETS2 is off, FE
As for the source-drain voltage of TS2, when the voltage drop due to the diode D1 of the switch Q1 is added to the input voltage VS, the FETS1 is off and the FETS2 is on,
The source-drain voltage of FETS1 is the input voltage VS
Is added to the voltage drop due to the diode D2 of the switch Q2. Therefore, in any case, FETS
Since the charging / discharging voltage of the capacitor C3 is not directly applied between the source and the drain of S1 and S2, the voltage stress on the FETs S1 and S2 becomes much smaller than that of the conventional circuit.

Next, experimental results of the circuit shown in FIG. 7 in this embodiment will be described. In this embodiment, FIG.
Similarly, a converter with an output of 50 W is designed by adding an output inductor L0 of 962 nH to the circuit shown in FIG. The changes are shown in the table below.

[0063]

[Table 2]

FIG. 10 shows experimental waveforms for the current and voltage of the circuit shown in FIG. In the figure, the upper stage is the inductor current iL, the middle stage is the gate-source voltage VGS1 and the drain-source voltage VDS1 of the switch Q1,
The lower row shows the gate-source voltage VGS2 and the drain-source voltage VDS2 of the switch Q2. In FIG. 10, the upper waveform is for the inductor current iL. The lower four waveforms show that this circuit also achieves zero voltage switching for both switches Q1, Q2.

FIG. 11 shows the efficiency vs. output power curve at each input voltage VS. This circuit achieves an efficiency of 87.6% when the output side is at full load current and the input voltage VS is 42V. However, like the circuit of the first embodiment, as the input voltage VS increases,
Efficiency is reduced. That is, when the input voltage VS is 60V, the efficiency is 87.1%, and when the input voltage VS is 63V, the efficiency is 85.8%. However, due to the current in the form of a quasi-square wave, this drop is not very rapid. It is speculated that the decrease in efficiency is caused by the higher ripple of the magnetizing current IM due to the higher input voltage VS.

As described above, in each of the above-described embodiments, as a part of the resonance circuit, a novel asymmetrical PWM control using the leakage inductance of the insulation type transformer T1 and the parasitic capacitance of the MOS type FETs S1 and S2 is involved. A new soft switch converter was introduced. The circuits of the respective embodiments in FIGS. 1 and 7 are FETS.
Since 1 and S2 are connected in a totem pole type, the voltage applied between the source and drain of these FETs S1 and S2 is only the input voltage VS plus the voltage drop of the diodes D1 and D2. That is, FETS1,
Since the voltage stress on S2 is much smaller than that of the conventional example, it is possible to use the FETs S1 and S2 having a smaller rated voltage without deteriorating the advantage of the resonant converter, and at the same time, turning on the FETs S1 and S2. Since the resistance is also reduced, the power loss on the primary side of the transformer T1 can be reduced and the overall efficiency of the circuit can be improved.

The advantages and effects of the above circuits are as follows.

In the circuit shown in FIG. 1, the voltage stress on the output side diodes D3, D4 can be reduced, and the conduction loss for the diodes D3, D4 can be reduced.

In the circuit shown in FIG. 7, since the effective current of the circuit can be reduced, the conduction loss for the diodes D1 and D2 and the MOS type FETs S1 and S2 can be reduced.

Since the FETs S1 and S2 are connected in a totem pole type, the voltage stress on the FETs S1 and S2 can be reduced. That is, MOS type FETS
The rated voltage and conduction loss of 1 and S2 can be suppressed low.

The circuit current on the input side can be reduced in the full load state. That is, the current stress on each element on the input side can be reduced.

In particular, the circuit shown in FIG. 1 can be constructed with a small number of parts.

By passing a current in the positive and negative directions with respect to the transformer T1, it becomes possible to fully utilize the core of the transformer T1.

It is possible to fix the operating frequency with respect to load fluctuations.

A wide range of load conditions including no load can be handled.

The overall efficiency is high even in an incompletely loaded state.

[0077]

According to the present invention, a DC input power supply, a transformer having a primary side and a secondary side, and an electric power from the DC input power supply including a specific capacitance are selectively applied to the primary winding of the transformer. Of the primary winding of the transformer, a capacitive element inserted and connected between the primary winding of the transformer and the first switching means, and a primary winding of the transformer including the inherent capacitance and the first switching means. Second switching means connected to both ends of the series circuit;
A rectifier circuit connected to the secondary side of the transformer and a capacitive or inductive filter circuit connected to the rectifier circuit are provided, and the first switching means and the second switching means are respectively provided for a predetermined time. It is configured to switch on alternately at intervals with a certain dead band in between, minimizing the voltage stress applied between each switching means without compromising the advantages of the resonant converter. Thus, it is possible to provide a DC / DC converter whose rated voltage can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram of each part of the above.

FIG. 3 is a waveform diagram of each part of the same as above.

FIG. 4 is an explanatory diagram showing an operating state of the same circuit.

FIG. 5 is a waveform diagram showing current and voltage of the same circuit.

FIG. 6 is a graph showing the characteristics of efficiency vs. output power at each input voltage.

FIG. 7 is a circuit diagram showing a second embodiment of the present invention.

FIG. 8 is a waveform diagram of each part of the above.

FIG. 9 is an explanatory diagram showing an operating state of the same circuit.

FIG. 10 is a waveform diagram showing current and voltage of the same circuit.

FIG. 11 is a graph showing characteristics of efficiency vs. output power at each input voltage.

FIG. 12 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 VS DC input power supply T1 transformer Q1 switch (first switch means) Q2 switch (second switch means) C3 capacitor (capacitive element) D3, D4 diode (rectifier circuit) CO capacitor (filter circuit) LO inductor (filter circuit) )

Claims (1)

[Claims] 1. A direct current input power supply, a transformer having a primary side and a secondary side, and a first capacitance for selectively applying power from the direct current input power source to a primary winding of the transformer. Switching means, a capacitive element inserted and connected between the primary winding of the transformer and the first switching means, and a series circuit of the primary winding of the transformer and the first switching means including a specific capacitance. The second switching means connected to both ends, a rectifier circuit connected to the secondary side of the transformer, and a capacitive or inductive filter circuit connected to the rectifier circuit, the first switching The means and the second switching means are alternately turned on at predetermined time intervals, and there is a certain dead band between them. DC / characterized by being
DC converter.