JPH0654528A - Drive circuit for power switch of zero- volt switching power converter - Google Patents

Abstract

PURPOSE: To lighten switching loss by controlling it so that the dead time for performing the zero-volt turn on of first and second power switching transistors may be generated between alternating on periods, in a bridge type of power converter. CONSTITUTION: For input voltage, a voltage is converted by the FETs 111 and 112 connected with a half-bridge circuit 110 and coupled with a transformer 133 of an integrated magnetic circuit 130. The output of the converter 133 is outputted through the following synchronized rectifier 150 and output filter 160, via the ripple offsetting magnetic circuit of an integrated magnetic circuit 130. A control circuit 170 generates control pulse waveform corresponding to the error voltage, and a gate drive circuit 120 turns on them alternately at each duty ratio different in phase. Here, the zero-volt switching is achieved by controlling it, so that the dead time may occur between the alternate on periods.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a zero volt switching power converter.
ters).

[0002]

BACKGROUND OF THE INVENTION One important aspect of modern power source design is that power sources are located because many power applications are positioned such that the size of the power source for its power output is constrained by spatial considerations. Is to require an increase in power density. Power train (powe
In addition to being highly compact, the r train) and control circuitry must have a high overall efficiency to limit the heat-producing dissipation. An example application of a high density power source is an off-line power supply used to power a laptop computer or similar device.
Is. Bridge type converters are suitable for such applications because they can be designed to operate at resonance, a mode of operation that allows very high power densities and high power efficiencies.

Half bridge converter
power switching transistor (po)
The wer switching transistors are push-pull converters with comparable power handling capabilities.
ter) with an applied voltage stress that is half that of the switching transistor in ter). Half-bridge converters are used in high input voltage applications, such as power factor correction boost converters powered directly from or away from the rectified AC power line.
It is particularly suitable for high input voltage applications such as power converters powered by a power converter.

[0004]

An off-line switching power source embodying the principles of the present invention and having a bridge topology power converter operating in a resonant mode operates at a high power density.
used as upply). Novel drive configurations and operating schemes for driving power switching transistors limit dissipative losses in power switching transistors.

[0005]

Two switching transistors are connected in a half-bridge configuration. The drive circuit causes the two power switching transistors to have unequal duty cycles with conduction durations such that the sum of the conduction periods is substantially equal to the combined switching period of the two power switching transistors.
s) to drive. These conduction intervals are separated by a very short dead time interval controlled by the different turn-on and turn-off times of these two power switching transistors. This short period between the alternating conductions of the two power switching transistors is long enough to allow zero volt turn-on of the power switching transistors, but short enough to minimize power loss and conduction noise. In one embodiment, this dead time is on the order of magnitude smaller than at least the shortest duty cycle time interval. Adjusting the output of the converter is accomplished by adjusting the ratio of the first and second duty factors or the conduction interval.

In addition, the drive circuit for the FET power switch operating in the zero volt switching mode according to the present invention provides a feedback of the current output of the parasitic capacitance of the discharge drain source to keep the gate below the turn-on voltage of the FET power switch. It includes circuitry used to generate a voltage drop across a resistor in the circuit. When the drain-source parasitic capacitance is discharged, the application of turn-on voltage to the gate is activated.

[0007]

DETAILED DESCRIPTION A schematic diagram of a DC / DC converter embodying the principles of the present invention is shown in FIG. The converter 100 is a half bridge power switching circuit.
chingcircuit) 110, integrated magnetics processing circuit 13
0, synchronous rectifier 150, output 160, and control circuit 17
Including 0.

Input power is applied to input terminals 101 and 102. This input power is, in this example circuit, a power factor boost converter (po) connected to be energized by the AC line voltage via a rectifier circuit.
wer factor boost converter). This input power is connected to a half-bridge switching circuitry and is coupled to a primary winding 132 of a transformer 133 contained within the integrated magnetics processing circuit 150. Two power switches 111 and 112 (in one exemplary embodiment). FET power switch).
The primary winding 132 is connected to the capacitor 123 in a series circuit. This series circuit is connected in parallel with the power switch 112. The average voltage across capacitor 123 is equal to the average voltage across power switch 112.
The secondary winding 134 of the power transformer 133 has conductors 135, 1
36 and 137, and a ripple canceling magnetic circuit including transformers 138 and 139.
uit) and is connected to the synchronous rectifier 150. Two FET rectifier devices 151 and 152 are connected to provide a rectified voltage to the output filter 160.
The DC voltage output of the converter is provided at output terminals 161 and 162.

DC of the converter at terminals 161 and 162
The output voltage is sensed by the control circuit 170 and the lead 1
It is supplied via 71 and 172 to a voltage divider consisting of resistors 173 and 174. Central node 1 of the divider
The divided voltage at 75 is the opamp 17
6 connected to the inverting input. Reference voltage 177 is connected to its non-inverting input. The output of the op amp 176 is terminal 1.
A control error voltage representing the deviation of the converter DC output voltage at 61 and 162 from some preselected regulated voltage value.

This control error voltage is applied to the inverting input of comparator 180. Periodic ramp voltage
voltage) is applied to the non-inverting input by the ramp generator 181. The output of comparator 180 on lead 183 is a rectangular voltage waveform with finite rise and fall times. This duration or duty cycle (i.e. the ratio of high voltage to period) is controlled by the amplitude of the control error voltage.

A typical sawtooth waveform 201 provided by a ramp generator is shown in FIG. A typical control error voltage level (ie its ordinate) is the vertical axis 20 of FIG.
3 is indicated by the amplitude mark 202. The control output voltage of the comparator is a pulse signal with finite rise and fall times as shown by waveform 205 in FIG. This high duration (D) is dominated by the time interval required for the positive sloped ramp 206 of waveform 201 to achieve the ordinate value of the error voltage level.
Therefore, the output of the comparator is the increasing ramp waveform (increasing r
The remaining duration (1-D) of the amp waveform) is low. The period of the ramp waveform (1) determines the period of operation of the converter. These corresponding conduction intervals have substantially different durations, as indicated by pulse 210 and the low state between them. These two power switches are only activated for significantly different non-identical durations (D and D-1) as shown by waveform 205. The ratio of these two unequal durations is changed in response to the control error voltage to achieve regulation of the output voltage.

The waveform (2
05) is coupled to the primary winding 114 of the transformer 115 of the gate drive 120 via the lead 183 and the capacitor 184. The capacitance of capacitor 184 is selected to block the DC portion of waveform 205 while leaving the pulse waveform substantially unchanged.

The gate drive 120 shown in FIG. 1 includes an input transformer 115 whose primary winding 114 has a pulse waveform 205 (also shown as voltage waveform 301 in FIG. 3).
Be connected to receive. The pulse waveform 205 is coupled to two secondary windings 116 and 117, which have a winding orientation such that they provide opposite polarity voltages on the windings. These opposite polarities of voltage are applied to the gate drive resistors 126 and 127, respectively. The pulse waveform supplied to the gate resistor 126 is substantially the waveform 2 shown in FIG.
05, while the waveform supplied to the gate resistor 127 is the inverse of waveform 205 (ie, out of phase with waveform 205). The corresponding duty factors of these two switches do not take up all of the allotted time period due to the finite rise and fall times of the antiphase pulses.

Waveform 302 in FIG. 3 is the output of secondary winding 116 of transformer 121. The waveform 303 in FIG.
1 is the output of the secondary winding 117. The waveform 302 is in phase with the control waveform 301 and the waveform 303 is out of phase.
The high state portions of waveforms 302 and 303 put FET power switches 111 and 112 into their respective conducting states for the duration of the high state of these waveforms. Power switches 111 and 112 are conducting during opposite phase periods and for different durations (D and 1-D).

The circuitry associated with each FET power switch has an applied gate source drive waveform.
It is designed to add a controlled time delay to the initial rise of ource drive waveform). FET power switch 1
In the drive circuit for 11, the drive signal is applied via secondary winding 116 of transformer 115, resistor 126, and capacitor 128. Slewing across the FET power switch 111
) Causes current to flow through capacitor 128. This current causes a voltage to drop across resistor 126. This voltage serves to reduce the gate voltage of the FET power switch 111, thereby delaying the rise time of the gate signal until the drain source voltage of the FET power switch 111 reaches a minimum value. This drop to the minimum occurs partly as a result of the leakage inductance of transformer 133 and partly as a result of the magnetizing current of transformer 133. This minimum voltage is limited by the clamp voltage of the parasitic diode of the FET power switch.

When the drain source voltage of the FET power switch 111 is dropping, current is drawn through the series resistor 126 and the capacitor 128, and the rise time of the gate source voltage (shown by waveform 401 in FIG. 4) is drain source. The voltage (depicted by waveform 401 in FIG. 4) is delayed until it reaches its minimum value. Thus, a small time delay (indicated by time increment 403 in FIG. 4) occurs between the turning off of FET power switch 112 and the turning on of FET power switch 111. The FET power switch 111 is thus turned on at the minimum drain-source voltage, which minimizes turn-on losses.

The drive circuit for the FET power switch 112 is energized by the output of the secondary winding 117 of the transformer 115. It includes a resistor 127 and a capacitor 129 connected in series. This series circuit is
Gate-source voltage at FET power switch 12 (as illustrated by waveform 402 in FIG. 4) as described in connection with applying drive to T power switch 111.
Is delayed until its drain-source voltage reaches a minimum (delay shown by time increment 404 in FIG. 4).

In each drive circuit, each resistor (1
26, 127) and the value of resistance for each capacitor (1
28, 129) is selected such that the current flowing through the source-drain parasitic capacitor of the FET power switch produces a voltage sufficient to keep the gate-source voltage below the turn-on threshold voltage value.

[Equation 1]

This current is a function of the drain source voltage slew rate and the capacitance value.

[Equation 2]

Capacitors 128 and 129 are not already present on their own, but are not sufficient to provide the required capacitance value.
Itance) and is added to this size. The resistance of resistors 126 and 127 must be low enough to ensure a fast rise in gate voltage when the capacitor current reaches zero value. Diode 11
8 and 119 are added to provide a low impedance path for the turn-off signal and to improve the turn-off efficiency of these power switches.

As explained above, the FET power switches 111 and 112 are out of phase with each other and there is a small dead time between the unequal conduction periods (D and 1-D) of the two power switches. Drive to do. This dead time that occurs during the conduction period of the two switches is very important for minimizing switching losses.

If it is defined that the switching period of the power converter is unity (that is, "1"), the power switch 111 has a conduction shock coefficient (conduction d) of "D".
utycycle) and the power switch 112 has "1-
It has a conduction duty factor of D ". The voltage across the power switch 112 (as shown by the waveform 501 in FIG. 5) is substantially" 1- "during the switching period.
D "generally equal to 0 volts to the portion, substantially all of the remaining switching period" equal to the input voltage V _in. Relation between these voltages is shown clearly in FIG. 5 for the D "portion Where waveform 501 represents the voltage across power switch 112 and voltage waveform 502 represents the voltage applied to primary winding 132 of transformer 133. Waveform 503 represents primary winding 132 as an input lead. Represents a voltage across a capacitor 123 connected to a return lead 138 connected to 102. This voltage, represented by waveform 503, is substantially equal to the product of period "D" and the input voltage V _in . The average voltage across winding 132 is zero for this switching period.

Dead times 505 and 50 shown in FIG.
During 6, the leakage energy of transformer 133 resonates with the parasitic capacitances of power switches 111 and 112, causing the voltage across the power switches to reach zero volts just before it turns on. In addition to this leakage energy, the transformer magnetizing current acts to force the voltage across the power switch to zero volts just before it turns on. The inductive energy of transformer 133 acts to reverse its voltage when the current flow is interrupted at the end of the conduction period of transistor switch 111 during dead time 505. This reversal of the transformer voltage causes the voltage across the transistor switch 112 to go to the zero volt value. Zero volt switching is achieved for transistor switch 112 when the inductive energy is sufficient to bring the voltage across transistor switch 112 to zero volts prior to the beginning of the conduction period "1-D". Similarly, zero volt switching is achieved for transistor switch 111 during dead time 506 at the end of the conduction period for transistor 112.

The value required for the magnetizing energy and leakage energy of transformer 133 to achieve zero volt switching depends on the impedance of the secondary winding of the converter. In this embodiment (a half-bridge buck type converter), zero volt switching sets the magnetizing current above the output current reflected or discharges the leakage energy into the parasitic capacitances of transistor switches 111 and 112. It is obtained by setting the energy larger than that required for.

Under the condition of low output current, the effect of the magnetizing current is dominant. At high output current conditions, the effect of leakage energy dominates. Zero volt switching can be obtained for the full range of output currents by maximizing both magnetizing current and leakage energy.
This zero volt turn-on transition timing is obtained by automatic adjustment of the dead time value through the novel gate drive circuit according to the present invention. Achieving a zero volt turn-on transition minimizes power loss and limits radiated and conducted noise.

In order to prevent the transformer 133 from saturating due to the asymmetrical drive applied to it during operation of the converter, this core typically contains a high magnetizing current. A gap is given. Transformer 1
33 and the inductances 135, 136 and 137 are configured in an integrated form. An equivalent magnetics core model 601 is shown in Figure 6, which is equivalent to a 3-leg magnetics core structure. Equivalent electrical model 7
01 is shown in FIG. 7, the actual circuit of FIG. 1 includes a delta connection loop of three conductors 135, 136 and 137. FIG. 7 shows the coupling of transformer windings 134, 146 and 147 to individual conductors 135, 136 and 137, respectively, which is equivalent to the circuit configuration of integrated magnetics circuit 130 shown in FIG. is there.

The integrated magnetics circuit 130 provides three reluctance paths for the output current. In the first phase of the switching cycle, the current output flows in winding 146 with inductance 137. In the other half cycle, current flows through winding 146 and its inductance 136. Since their corresponding duty factors (D, and 1-D) are not equal, these ripple currents are out of phase and cancel each other, so the resulting ripple currents are less than ripples in any one conductor. Get smaller. If the value of conductors 135, 136 and 137 is equal to the ratio of the duty factors of the opposite phases when a particular operating point is predominant, then at that operating point all ripple currents are substantially cancelled. To be specifically selected. If the ratio of the inductances is chosen to be equal to the voltage applied to them, the currents are out of phase, sum to zero, and the ripple current is zero.

By choosing the values for conductors L ₁ and L ₂ correctly, the ripples can cancel at a defined load. Here, L ₁ is the conductor 136 and L ₂ is the conductor 137. For the D portion of this cycle; _VL1 = _Vout (3), and for this cycle (1-D) portion: _VL1 / _VL2 = D / (1-D) (4 ) Is.

Thus, throughout the entire switching cycle, equation (6) defines the voltage ratio substantially across these conductors. V _L1 / V _L2 = L ₁ / L ₂ (5) These currents therefore exactly cancel at this operating point if: L ₁ / L ₂ = D / (1-D) (6)

Through the duration of conduction of the FET power switch 112, the secondary conductor 1 of the integrated magnetics circuit 130 is
37 is connected to the output terminals 161 and 162 via the FET rectifier 151 of the synchronous rectifier circuit 150. A secondary voltage balance appears across the conductor 136. During the opposite phase of the FET power switch 111 conduction period, the secondary inductance 136 is connected across the output voltage terminals 161, 162 through the synchronous rectifier switch 152. The remaining portion of the output voltage occurs across the secondary conductor 137.

The voltage waveform of the integrated magnetics circuit is shown in FIG.
Shown in. Voltage waveform 803 represents the voltage across secondary conductor 137 and voltage waveform 802 represents the voltage across secondary conductor 136. The voltage waveform 801 is the transformer 13
3 represents the voltage across three primary windings 132. The steady state output voltage of the converter at output leads 161 and 162 is ensured by equalizing the volt seconds across the two inductances during opposite phases of operation.

Self-synchronizing rectifier 150 (shown in FIG. 1)
Uses two FETs 151 and 152. Each FET
The gates of 151 and 152 are the other FET 15 respectively.
Driven by drain voltages of 2 and 151.
These rectifiers rectify from full load to zero load without the need for bleeders and without significant changes in duty cycle.

The current flowing in the output capacitor 163 that shunts the output leads 161 and 162 equalizes the sum of the currents flowing in these conductors. The output voltage is given by the following expression (Equation 3).

[Equation 3]

Although the above converters have typically been described in the context of an off-line converter operating with a power factor booster circuit at its input, the principles of the present invention are readily applicable to converters operating without power factor correction. I want to be careful. Furthermore, the principles of the present invention apply equally to other bridge topologies in addition to the half bridge circuit of one embodiment described above. Examples of these include other variations of full-bridge and half-bridge topologies.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a bridge type power converter embodying the principles of the present invention.

FIG. 2 is a waveform diagram of voltage waveforms to help explain the operation of the converter.

FIG. 3 is a diagram showing representative gate voltage drive waveforms for a power switch to help explain the operation of the converter.

FIG. 4 is a diagram showing a waveform of a switching voltage of a power switch of a half-bridge to help explain the operation of the converter.

FIG. 5 is a diagram showing a waveform of a switching voltage of a power switch to help explain the operation of the converter.

FIG. 6 shows a magnetic model of integrated magnetics used in a converter.

FIG. 7 shows an electrical model of integrated magnetics used in a converter.

FIG. 8 is a diagram showing voltage waveforms to help explain the operation of integrated magnetics.

[Description of Reference Signs] 110 Half Bridge 120 Gate Drive 130 Integrated Magnetics 150 Synchronous Rectifier 160 Output Filter 170 Control

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Thomas Patrick Loftus, Junia USA 75044 Texas, Garland, Indian Hills Drive 5821

Claims (23)

[Claims] 1. A bridge-type power converter in which the conducting / non-conducting transition of a power switching transistor occurs at zero volts, which is an input circuit for receiving an energy source; connected in series, said series circuit being said input circuit. A first and a second power switching transistor shunted with; a primary winding connected to a common node connecting the first and second power switching transistors, and a secondary winding A power transformer; a rectifier circuit connected to the secondary winding for rectifying the voltage output of the secondary winding; and an output circuit for coupling the rectified voltage of the rectifier circuit to a load to be energized The improvement includes: alternating alternating conduction periods of the first and second power switching transistors to the first and second power. A control circuit for periodically controlling such that the dead time permitting zero volt turn-on of the switching transistor is present during these alternating conduction periods, the first conduction period of the first power switching transistor having a duration of At a time substantially shorter than the second conduction period of the second power switching transistor described above,
The dead time is at least on the order of a scale smaller than the first conduction period, and the combined duration of the first and second conduction periods and the dead time is equal to the periodic interval. Is a bridge type power converter. 2. As an improvement, the control circuit further comprises: an error signal circuit for generating an error signal representative of the deviation of the voltage at the output circuit from some preset adjusted value, A pulse circuit responsive to the error signal for generating a pulse signal representative of the error signal, the pulse circuit having a controlled duration substantially less than half a switching ig period of the bridge type power converter; And a drive circuit for applying a drive signal of opposite phase to the second power switch transistor, the drive circuit being applied to the primary winding and the primary winding connected to receive the pulse signal. A pulse transformer having first and second secondary windings polarized to produce opposite phases of the signal, and A first and a second drive winding for coupling the first and second secondary windings of the transformer to the first and the second power switch transistors, each drive transmission circuit comprising: The conducting / non-conducting transition of the power switching transistor of claim 1 including a resistive capacitance timing circuit for ensuring a controlled rise time for pulse outputs of the first and second primary windings. A bridge type power converter that occurs at zero volts. 3. As a further improvement, the pulse circuit further comprises a comparator having a first input connected to receive the error signal and a second input; a saw connected to the second input. The power switching transistor of claim 2 including a ramp generator for generating a blade ramp voltage waveform, and a dc blocking capacitor interconnecting the output of the comparator to the primary winding of the pulse transformer. Bridge-type power converter in which the conduction / non-conduction transition occurs at zero volts. 4. The improvement further comprises: a storage capacitor coupling the primary winding of the power transformer to the input and a series connection of the power transformer primary winding, wherein the storage capacitor is the second power. A bridge-type power according to claim 3, characterized in that the conducting / non-conducting transition of the power switching transistor shunts the switching transistor and operates to store an average voltage of the voltage level of the common node. converter. 5. An improvement further comprises: a bypass circuit for allowing the drive signal to bypass the resistance of the resistive capacitance timing circuit upon turn-off of the first and second power switching transistors. A bridge-type power converter according to claim 4, wherein the conducting / non-conducting transition of the power switching transistor occurs at zero volts. 6. The improvement further comprises: the first and second power switching transistors being FET power switching transistors.
A bridge-type power converter in which the conduction / non-conduction transition of its power switching transistor occurs at zero volts. 7. A bridge type power converter comprising: one input for accepting a DC voltage; one output for providing a regulated DC voltage; a DC voltage across said input. A power circuit coupling the input to the output including first and second power switches connected together; a power transformer having a primary winding connected across the second power switch; and Control for alternately driving one and second power switches to energize for each cycle of operation of the first power switch to energize for a significantly shorter period than the second switch energizes. A bridge-type power converter including a circuit. 8. As an improvement, the control circuit further comprises: an error signal circuit for generating an error signal representative of the deviation of the DC voltage at the output circuit from some preset adjusted value. A pulse circuit for generating a pulse signal representative of the error signal in response to the error signal, the pulse circuit having a controlled duration substantially less than half a switching period of the bridge-type power converter; A drive circuit for applying a drive signal of opposite phase to the second power switch, a primary winding connected to receive the pulse signal and an opposite phase of the signal applied to the primary winding. Transformer having first and second secondary windings oriented in such a way, and said first and second secondary windings of said pulse transformer A first and a second drive transmission circuit for coupling a line to said first and second power switches, each drive transmission circuit being controlled for pulse output of said first and second primary windings. 8. The bridge type power converter of claim 7 including a resistive capacitance timing circuit for ensuring high rise time. 9. A further improvement, wherein said pulse circuit further comprises a comparator having a first input connected to receive said error signal and a second input; a saw connected to said second input. 9. The bridge type power of claim 8 including a ramp generator for generating a blade ramp voltage waveform, and a dc blocking capacitor interconnecting the output of the comparator to the primary winding of the pulse transformer. converter. 10. An improvement further includes: a series connection of a storage capacitor coupling the primary winding of the power transformer to the input and the power transformer primary winding, the storage capacitor being the second power. 9. The bridge type power converter of claim 8 shunting a switch to operate to store an average voltage of the common node voltage levels. 11. A bridge-type power converter in which the conducting / non-conducting transition of a power switching transistor occurs at zero voltage, which is an input circuit for receiving an energy source; connected in series with the series circuit. First and second power switching transistors shunted to the circuit; and a primary winding and a secondary winding connected to a common node for coupling the first and second power switching transistors A power transformer having a primary winding of the power transformer coupled to the input, and a series connection of the power transformer primary winding, the storage capacitor including the second power. Shunts the switching transistor and operates to store an average voltage of the voltage level of the common node, A rectifier circuit connected to the secondary winding for the converter to further rectify the voltage output of the secondary winding; an output circuit for coupling the rectified voltage of the rectifier circuit to the load to be energized, Periodically controlling alternating conduction periods of the first and second power switching transistors such that a dead time allowing zero volt turn-on of the first and second power switching transistors exists between these alternating conduction periods. An error signal circuit for producing an error signal representative of a deviation of the voltage at the output circuit from some preset adjusted value for the error signal, In response, the bridge-type power converter has a controlled duration that is significantly less than half the switching period, and A pulse circuit for generating a pulse signal representative of a pulse signal, and a drive circuit for applying a drive signal of opposite phase to the first and second power switch transistors, the drive circuit including the pulse signal. A pulse transformer having a primary winding connected to receive and first and second secondary windings polarized to produce opposite phases of a signal applied to the primary winding; And first and second drive transmission circuits for coupling the first and second secondary windings of the pulse transformer to the first and second power switch transistors, each drive transmission A circuit includes a resistive capacitance timing circuit for ensuring a controlled rise time for the pulsed outputs of the first and second primary windings, the first power switch The first conduction period of the switching transistor is substantially shorter in duration than the second conduction period of the second power switching transistor,
The dead time is at least on the order of a scale smaller than the first conduction period, and the combined duration of the first and second conduction periods and the dead time is equal to the periodic interval. Is a bridge type power converter. 12. A further improvement, wherein said pulse circuit further comprises a comparator having a first input connected to receive said error signal and a second input, a saw connected to said second input. 12. The power switching transistor of claim 11, including a ramp generator for generating a blade ramp voltage waveform, and a dc blocking capacitor interconnecting the output of the comparator to the primary winding of the pulse transformer. Bridge-type power converter in which the conduction / non-conduction transition occurs at zero voltage. 13. A bridge type power converter, wherein the converter comprises: one input for receiving a DC voltage; one output for providing a regulated DC voltage; and coupling the input to the output. A power circuit, the power circuit having: first and second power switches connected across the DC voltage of the input; a primary winding connected across the second power switch. A power transformer; and a storage capacitor coupling a primary winding of the power transformer to the input and a series connection of the power transformer primary winding, wherein the storage capacitor shunts the second power switch. And storing an average voltage of the voltage level of the common node, the converter further alternating the first and second power switches with the first power. It includes a control circuit for switch said second switch in each cycle of operation to drive energized to energize only considerably shorter than the energized state, the control circuit further;
An error signal circuit for producing an error signal representative of the deviation of the DC voltage at the output circuit from some preset adjusted value; switching of the bridge type power converter in response to the error signal. A pulse circuit for generating a pulse signal representative of the error signal, the pulse circuit having a controlled duration of substantially less than half a period; for applying drive signals of opposite phases to the first and second power switches. A drive circuit, a primary winding connected to receive the pulsed signal, and first and second secondary windings polarized to produce opposite phases of a signal applied to the primary winding. A pulse transformer having a wire, and for coupling said first and second secondary windings of said pulse transformer to said first and second power switches First and second drive transmission circuits, wherein each drive transmission circuit includes a resistive capacitance timing circuit for ensuring a controlled rise time for the pulse output of the first and second primary windings. A characteristic bridge type power converter. 14. A refinement further comprising: a comparator having a pulse circuit, the comparator having a first input connected to receive the error signal, and a second input; and a saw connected to the second input. 14. The bridge type power of claim 13 including a ramp generator for generating a blade ramp voltage waveform, and a dc blocking capacitor interconnecting the output of the comparator to the primary winding of the pulse transformer. converter. 15. A bridge-type power converter in which the conduction / non-conduction transition of the power switching transistor occurs at zero voltage, the input circuit receiving an energy source; connected in series, said series circuit being said input. First and second power switching transistors shunted to the circuit; having one primary winding and one secondary winding, and for ensuring a zero volt turn-on transition of said first and second power switching transistors A power transformer containing sufficient magnetizing energy and leakage inductance, said primary winding being shunted with one of these two series-connected first and second power switch transistors; the voltage of the secondary winding A rectifier circuit connected to the secondary winding for rectifying the output; rectified current of said rectifier circuit An output circuit for coupling a voltage to a load to be energized; and a dead time allowing alternating conduction periods of the first and second power switching transistors to zero volt turn-on of the first and second power switching transistors. Are periodically controlled so that they exist between these alternating conduction periods, and the voltage of the output circuit is adjusted, on the one hand, the imbalance between the first and second conduction periods, and on the other hand, the dead time. A control circuit for adjusting the interval by holding it in a dead time interval having an order of magnitude smaller than one of these alternating periods, wherein the first conduction period of the first power switching transistor is The duration is significantly shorter than the second conduction period of the second power switching transistor, and the Time is at least on the order of a smaller scale than the first conduction period, and the combined duration of the first and second conduction periods and the dead time is equal to the periodic interval. Bridge type power converter. 16. A bridge-type power converter in which a conducting / non-conducting transition of a power switching transistor occurs at zero volts, the input circuit for receiving an energy source; connected in series, said series circuit being said input circuit. A first and a second power switching transistor shunted with; having one primary winding and a secondary winding and sufficient to ensure a zero volt turn-on transition of said first and second power switching transistors Transformer, the primary winding of which includes a variable magnetizing energy and a leakage inductance, the primary winding being shunted to one of these two series-connected first and second power switch transistors; A rectifier circuit connected to the secondary winding for rectifying the rectifier circuit; An output circuit for coupling a voltage to a load to be energized; and a dead time allowing alternating conduction periods of the first and second power switching transistors to zero volt turn-on of the first and second power switching transistors. Includes a control circuit for periodically controlling such that there is an interval between these alternating conduction periods; the first conduction period of the first power switching transistor is the second power switching transistor in duration. Is substantially shorter than the second conduction period of, and the dead time is at least an order of magnitude smaller than the first conduction period, and the dead time is combined with the first and second conduction periods. A bridge-type power converter, characterized in that its duration is equal to said periodic interval. 17. An improvement is further characterized in that the control circuit serves to regulate the voltage of the output circuit by regulating the imbalance between the first and second conduction intervals. Item 16. A bridge type power converter according to item 16. 18. As an improvement, the control circuit further comprises: an error signal circuit for generating an error signal representative of the deviation of the voltage at the output circuit from some preset adjusted value, A pulse circuit responsive to the error signal for producing a pulse signal having a controlled duration that is substantially less than half a switching period of the bridge-type power converter, the pulse circuit representing the error signal; And a drive circuit for applying a drive signal of opposite phase to the second power switching transistor, the drive circuit comprising: a primary winding connected to receive the pulse signal and applied to the primary winding. A pulse transformer having first and second secondary windings polarized to produce opposite phases of the signal, and A drive transmission circuit including first and second drive transmission circuits for coupling the first and second secondary windings of the pulse transformer to the first and second power switching transistors. Includes a resistive capacitance timing circuit for ensuring a controlled rise time for the pulsed outputs of the first and second primary windings; the control circuit imbalances between the first and second conduction intervals. 18. The bridge type power converter according to claim 15, wherein the power converter adjusts the voltage of the output circuit by adjusting the voltage. 19. An error signal circuit for the control circuit to generate an error signal representative of the deviation of the voltage at the output circuit from some preset adjusted value; A drive circuit for applying drive signals of opposite phases to the two power switching transistors, the drive circuit comprising: connecting the first and second secondary windings of the pulse transformer to the first and second A first and a second drive transmission circuit for coupling to a second power switching transistor, each drive transmission circuit ensuring a controlled rise time for the pulse output of the first and second primary windings. 19. The bridge type power converter of claim 18 including the resistive capacitance timing circuit of claim 1. 20. An improvement further comprising: a comparator having a first input connected to receive the error signal, and a second input; a sawtooth ramp voltage waveform connected to the second input. And a ramp generator for generating a signal having opposite polarities from the comparator to the first and second power switching transistors to provide isolation between the signals of opposite polarities. 19. The bridge type power converter of claim 18, further comprising means. 21. An improvement further comprising: including a storage capacitor connected in series with the primary winding and operable to store an average voltage of a voltage level applied across the series circuit. The bridge type power converter according to claim 20. 22. A bridge type power converter comprising an input for receiving a DC voltage; an output for providing a regulated DC voltage; and a power circuit for coupling the input to the output: A power circuit comprising first and second power switches connected across the input DC voltage; and a power transformer having a dc blocking capacitor and a primary winding connected in series, the series circuit comprising: Connected across one of the first and second power switches; the power converter further comprising the first and second power switches in each cycle of operation of the first and second power switches. It drives alternately so that it is conductive for a considerably shorter period than the power switch, and the voltage at the output is also A bridge-type power converter comprising: a control circuit for adjusting the imbalance between the periods of conduction of the first and second power switches by adjusting the imbalance. 23. As an improvement, the control circuit further comprises: an error signal circuit for generating an error signal representative of a deviation of the DC voltage at the output circuit from some preset adjusted value. A pulse circuit for generating a pulse signal representative of the error signal in response to the error signal, the pulse circuit having a controlled duration substantially less than half of a switching period of the bridge-type power converter, and And a drive circuit for applying a drive signal of opposite phase to the second power switch.