JPH06326570A - Variable delay circuit - Google Patents

Abstract

PURPOSE:To reduce the variance of delay time between adjacent delay steps by selecting a desired signal among delayed signals and delay signals and outputting the delay signal. CONSTITUTION:A delay time difference between a delay signal D1 outputted from a delay means 201 in an initial stage and the delayed signal SI and a delay time difference between delay signals Di+1 and Di, which are outputted from the mutually adjacent delay means 20i+1 and 20i (i=1 to n-1), equal to the value of 'adelay time which one delay means 20i has + or - the variation of a delay time which one delay means 20i has'. Thus, a selection circuit 21 where plural selectors are connected in a tree shape is used and an arbitrary signal is selected among the delayed signal SI from a delayed signal terminal 16 and the delay signals D1-Dn from the means 201-20n and a delay signal SO is outputted to a delay signal output terminal 17. Thus, the variance of delay time between the adjacent delay steps can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit suitable for use in signal generators, IC (integrated circuit) testers and the like.

Conventionally, in a signal generator which outputs a plurality of signals, a variable delay circuit composed of a variable length coaxial tube driven by a motor has been used to adjust the phase between the output signals.

As a result, although the phase between the output signals can be adjusted with high accuracy, there is a problem that the device becomes large.

Further, in the IC tester, the variable delay circuit composed of the variable length coaxial tube driven by the motor cannot be incorporated because of its large external size, and the phase between the output signals is adjusted with high accuracy. There was a problem that I could not do it.

Under such circumstances, there has been a demand for the development of a highly accurate variable delay circuit which is integrated into a circuit.

[0006]

2. Description of the Related Art Heretofore, as a variable delay circuit formed as an integrated circuit, there has been proposed a variable delay circuit whose main part is shown in FIG. 14, for example.

In the figure, 1 is a delayed signal input terminal to which a delayed signal SI is input, 2 to 4 are selection signal input terminals to which delay time selection signals C1 to C3 for selecting a delay time are input,
5 is the delayed signal SI input to the delayed signal input terminal 1
Is a delayed signal output terminal from which a delayed signal SO obtained by delaying is output.

Further, 6 to 12 are delay gate circuits forming delay means for delaying the delayed signal SI, and 13 to 15 are 2-input selectors for varying the delay time with respect to the delayed signal SI.

Here, the selector 13 is controlled by the delay time selection signal C1 and the signal output from the delay gate circuit 6 or the delayed signal S input to the delayed signal input terminal 1 is inputted.
One of I is selected and output.

The selector 14 is controlled by the delay time selection signal C2 and selects and outputs either the signal output from the delay gate circuit 8 or the signal output from the selector 13.

The selector 15 is controlled by the delay time selection signal C3, and selects and outputs either the signal output from the delay gate circuit 12 or the signal output from the selector 14.

In this variable delay circuit, eight steps can be obtained as the delay step. Table 1 shows the relationship between the delay step and the route of the delayed signal SI, and Table 2 shows the delay step and the delayed signal SI. The relationship with the received delay time is shown.

However, in Table 1, T1 is the delayed signal input terminal 1, and DGs 6-12 are delay gate circuits 6-.
12, SL 13 to 15 are selectors 13 to 15, respectively.
T5 means the delayed signal output terminal 5.

In Table 2, t (DG) is the delay time of each of the delay gate circuits 6 to 12, ± Δt.
(DG) is the variation in the delay time of each of the delay gate circuits 6-12.

Further, t (SL) is the delay time of each of the selectors 13 to 15, and ± Δt (SL) is the selector 13.
15 to 15 are variations in the delay time of each.

[0016]

[Table 1]

[0017]

[Table 2]

[0018]

In this variable delay circuit, the variation in the delay time difference between the adjacent delay steps and the variation in the delay time difference between the adjacent delay steps are as follows. Delay signal S
Considering the route of I, it becomes as shown in Table 3.

[0019]

[Table 3]

As described above, in this variable delay circuit, the variation in the delay time difference between the delay steps is ± Δt (DG) at the minimum value and ± 7 · Δt (DG) at the maximum value, so that the delay characteristic There is a problem in that the linearity is poor and the delay signal SO with high delay accuracy cannot be obtained.

In view of the above point, the present invention makes it possible to reduce variations in delay time difference between adjacent delay steps, improve linearity of delay characteristics, and obtain a delay signal with high delay accuracy. An object is to provide a delay circuit.

[0022]

FIG. 1 is a diagram for explaining the principle of the present invention, in which 16 is a delayed signal input terminal to which a delayed signal SI is input, and 17 is a delayed signal input terminal 16 to which a delayed signal is input. The delay signal output terminal outputs a delay signal SO obtained by delaying the delay signal SI.

Reference numeral 18 denotes a delay circuit section having an input terminal 19 connected to the delayed signal input terminal 16, and 20 ₁ ,
20 ₂ ... 20 _n are delaying means forming the delay circuit section 18.

Reference numeral 21 denotes a delayed signal SI input to the delayed signal input terminal 16 and delay means 20 ₁ , 20 ₂ ...
A selection circuit unit that selects an arbitrary signal from the delay signals D ₁ , D _2, ... D _n output from 20 _n and outputs the delay signal SO to the delay signal output terminal 17, and includes a plurality of selectors. Are connected in a tree shape.

That is, in the variable delay circuit according to the present invention, delay means 20 ₁ , 20 ₂ ... 20 _n are connected in cascade, and
The delay circuit section 18 in which the input terminal 19 is connected to the delayed signal input terminal 16 and a plurality of selectors are connected in a tree shape, and the delayed signal SI and delay means input to the delayed signal input terminal 16 Selection of selecting a desired signal from the delay signals D ₁ , D ₂ ... D _n output from 20 ₁ , 20 ₂ ... 20 _n, and outputting the delay signal SO to the delay signal output terminal 17. The circuit portion 21 is provided and configured.

[0026]

According to the present invention, the delay time difference between the delay signal D ₁ output from the delay means 20 _{1 at the} first stage and the delayed signal SI and the adjacent delay means 20 _{i + 1} , 20 _i (however,
The delay time difference between the delay signals D _{i + 1} and D _i output from i = 1 to n−1) is the delay time of one delay means 20 _i ± the delay time of one delay means 20 _i. Will vary.

Here, in the present invention, the delayed signal S input to the delayed signal input terminal 16 is used by using the selection circuit section 21 in which a plurality of selectors are connected in a tree shape.
I and the delay means 20 ₁ , 20 _2, ... 20 _n output the delay signals D ₁ , D _2, ... D _n , select an arbitrary signal and output the delay signal SO to the delay signal output terminal 17. Since it is output, it is possible to reduce variations in delay time between adjacent delay steps.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 2 to 13, the first to fourth embodiments of the present invention will be described with reference to FIG. A case where the present invention is applied to a variable delay circuit having is described as an example.

First Embodiment FIG. 2 to FIG. 4 FIG. 2 is a circuit diagram showing a main part of the first embodiment of the present invention.
In the figure, reference numeral 22 denotes a delayed signal input terminal to which the delayed signal SI is input.

Further, 23 to 25 are delay time selection signal input terminals to which the delay time selection signals C1 to C3 for selecting the delay time are input, and 26 is a delay signal SO delayed from the delayed signal SI. This is a delayed signal output terminal.

Reference numeral 27 is a delay circuit section in which an input end 28 is connected to the delayed signal input terminal 22, and 29 to 3 are provided.
Reference numeral 5 is a delay gate circuit which is connected in cascade and outputs delayed signals D _{1 to} D ₇ which are obtained by delaying the delayed signal SI.

Here, these delay gate circuits 29 to 35 are provided.
For example, as shown in the circuit diagram of FIG. 3, ECL (emit
ter coupled logic) circuit. 3 in the figure
6 is a VCC power supply line for supplying a high-voltage side power supply voltage VCC;
It is a power line.

Reference numeral 38 is a differential circuit section, 39 is an output circuit section, 40 is a delayed signal input terminal to which the delayed signal A (SI, D _{1 to} D ₆ ) is input, and 41 is a reference voltage VB. Is a reference voltage input terminal to which is input.

Reference numeral 42 is a reference voltage input terminal to which the reference voltage VCS is input, 43 is an output terminal from which the delay signal X (D _{1 to} D ₇ ) is output, 44 to 48 are NPN transistors,
49 to 53 are resistors.

In this delay gate circuit, when the delayed signal A = “H”, the NPN transistor 44 = ON,
When the NPN transistor 45 = OFF, the collector of the NPN transistor 45 = “H”, and the delay signal X = “H”.
Becomes

On the other hand, when the delayed signal A = “L”, the NPN transistor 44 = OFF, the NPN transistor 45 = ON, the collector of the NPN transistor 45 = “L”, and the delay signal X = “L”. L ”.

In FIG. 2, reference numeral 54 denotes a delay time selection signal from the delayed signal SI input to the delayed signal input terminal 22 and the delay signals D _{1 to} D ₇ output from the delay gate circuits 29 to 35. A selection circuit unit that selects and outputs a signal designated by C1 to C3, and 55 to 61 are 2-input selectors connected in a tree shape (tree shape).

These two-input selectors 55 to 61 are constructed, for example, as shown in the circuit diagram of FIG. 6 in the figure
Reference numeral 2 is a VCC power supply line, 63 is a VEE power supply line, 64 is a delay time selection signal input circuit section, 65 is a selected signal selection processing circuit section, and 66 is an output circuit section.

67 is a delay time selection signal C (C1, C1,
C2, C3) is input to the delay time selection signal input terminal,
Reference numerals 68 and 69 denote selected signal input terminals to which the selected signals A1 and A2 are input.

Reference numeral 70 is a reference voltage input terminal to which the reference voltage VB1 is input, 71 is a reference voltage input terminal to which the reference voltage VB2 is input, 72 is a reference voltage input terminal to which the reference voltage VCS is input, and 73 is an output. An output terminal for outputting the signal X (A1, A2), 74 is a diode, 75 to 84 are NPN transistors, and 85 to 90 are resistors.

In this selector, when the delay time selection signal C = “H”, the NPN transistor 81 = ON,
NPN transistor 80 = OFF, selected signal A
2 is selected, and the selected signal A2 is output as the output signal X.

Here, when the selected signal A2 = “H”,
NPN transistor 79 = ON, NPN transistor 7
8 = OFF, NPN transistor 78 collector =
It becomes "H", and the output signal X becomes "H".

On the other hand, when the selected signal A2 = “L”, the NPN transistor 79 = OFF, the NPN transistor 78 = ON, the collector of the NPN transistor 78 = “L”, and the output signal X = “L”. Becomes

When the delay time selection signal C = “L”, the NPN transistor 81 = OFF and the NPN transistor 80 = ON, the selected signal A1 is selected, and the selected signal A1 is output as the output signal X. It

Here, when the selected signal A1 = "H",
NPN transistor 76 = ON, NPN transistor 7
7 = OFF, NPN transistor 77 collector =
It becomes "H", and the output signal X becomes "H".

On the other hand, when the selected signal A1 = “L”, the NPN transistor 76 = OFF, the NPN transistor 77 = ON, the collector of the NPN transistor 77 = “L”, and the output signal X = “L”. Becomes

In this first embodiment, eight steps can be obtained as the delay step, Table 4 shows the relationship between the delay step and the path of the delayed signal SI, and Table 5 shows the delay step and the delayed signal SI. It shows the relationship with the delay time received by.

However, in Table 4, T22 is the delayed signal input terminal 22, DGs 29 to 35 are delay gate circuits 29 to 35, and SL55 to 61 are selector 55.
˜61 and T26 indicate the delay signal output terminal 26.

In Table 5, t (DG) is the delay time of each of the delay gate circuits 29 to 35, ± Δt.
(DG) is the variation in the delay time of each of the delay gate circuits 29 to 35.

Further, t (SL) is the delay time of each of the selectors 55 to 61, and ± Δt (SL) is the variation of the delay time of each of the selectors 55 to 61.

[0051]

[Table 4]

[0052]

[Table 5]

Therefore, the delay time difference between the adjacent delay steps and the variation in the delay time difference between the adjacent delay steps are as shown in Table 6 when the path of the delayed signal SI in each delay step shown in Table 4 is taken into consideration. Then, considering that Δt (SL) = about Δt (DG), Table 7 is obtained.

[0054]

[Table 6]

[0055]

[Table 7]

That is, in the first embodiment, the variation of the delay time difference between the delay steps is ± Δt at the minimum value.
(DG), the maximum value is ± 5Δt (DG), and the variation in the delay time between adjacent delay steps can be made smaller than in the case of the conventional variable delay circuit shown in FIG. 11 (see Table 3). .

Therefore, according to the first embodiment, it is possible to improve the linearity of the delay characteristic and obtain the delay signal SO having a delay accuracy higher than that of the conventional variable delay circuit shown in FIG.

Second Embodiment ... FIG. 5 and FIG. 6 FIG. 5 is a circuit diagram showing an essential part of a second embodiment of the present invention.
In the figure, 91 is a delayed signal input terminal to which the delayed signal SI is input.

Reference numerals 92 to 94 denote selection signal input terminals to which delay time selection signals C1 to C3 for selecting delay times are input, and 95 delays the delayed signal SI input to the delayed signal input terminal 91. Is a delay signal output terminal for outputting the delay signal SO.

Reference numeral 96 denotes a delay circuit section having an input terminal 97 connected to the delayed signal input terminal 91, and 98 to 1
Reference numeral 04 denotes delay signals D _{1 to} D ₇ obtained by delaying the delayed signal SI.
Is a delay gate circuit that is connected in cascade and outputs.
The delay gate circuits 98 to 104 are, for example,
It is configured as shown in FIG.

Reference numeral 105 denotes the delayed signal SI input to the delayed signal input terminal 91 and the delay gate circuits 98-1.
A selection circuit section for selecting and outputting the signal designated by the delay time selection signals C1 to C3 from the delay signals D ₁ , D ₂ ... D ₇ output from 04, and 106 and 107 are 4-input The selector 108 is a 2-input selector.

Here, four-input selectors 106 and 107 are provided.
Is configured, for example, as shown in the circuit diagram of FIG. 6, and the 2-input selector 108 is configured, for example, as shown in the circuit diagram of FIG. 4 and connected in a tree shape.

In FIG. 6, 109 is a VCC power supply line, 1
Reference numeral 10 is a VEE power supply line, 111 is a delay time selection signal input circuit section, 112 is a selected signal selection processing circuit section, and 113 is an output circuit section.

Reference numerals 114 and 115 denote delay time selection signal input terminals to which the delay time selection signals C1 and C2 are input.
16 to 119 are selected signal input terminals to which the selected signals A1 to A4 are input.

Further, 120 and 121 are reference voltage input terminals to which the reference voltage VB1 is input, 122 and 123 are reference voltage input terminals to which the reference voltage VB2 is input, and 124 is a reference voltage input terminal to which the reference voltage VB3 is input. Is.

Reference numeral 125 is a reference voltage input terminal to which the reference voltage VCS is input, and 126 is an output signal X (A1 to A).
4) is output terminal, 127 is a diode, 12
8 to 146 are NPN transistors, and 147 to 153 are resistors.

In this selector, when the delay time selection signal C1 = "H" and the delay time selection signal C2 = "H", the NPN transistor 136 = ON, the NPN transistor 143 = OFF, and the NPN transistor 135 = O.
The N, NPN transistor 134 is turned off, the selected signal A2 is selected, and the selected signal A2 is output signal X.
Is selected as.

When the selected signal A2 = “H”, the NPN transistor 133 = ON, the NPN transistor 132 = OFF, the collector of the NPN transistor 132 = “H”, and the output signal X = “H”. Becomes

On the other hand, when the selected signal A2 = “L”, the NPN transistor 133 = OFF, NPN
Transistor 132 = ON, NPN transistor 13
The collector of 2 = “L”, and the output signal X = “L”.

When the delay time selection signal C1 = "H" and the delay time selection signal C2 = "L", the NPN transistor 136 = ON, the NPN transistor 143 = OFF,
The NPN transistor 135 = OFF and the NPN transistor 134 = ON, the selected signal A1 is selected, and the selected signal A1 is output as the output signal X.

Here, when the selected signal A1 = “H”, the NPN transistor 130 = ON, the NPN transistor 131 = OFF, the collector of the NPN transistor 131 = “H”, and the output signal X = “H”. Becomes

On the other hand, when the selected signal A1 = “L”, the NPN transistor 130 = OFF, NPN
Transistor 131 = ON, NPN transistor 13
The collector of 1 = “L”, and the output signal X = “L”.

When the delay time selection signal C1 = "L" and the delay time selection signal C2 = "H", the NPN transistor 136 = OFF, the NPN transistor 143 = ON,
The NPN transistor 142 = ON and the NPN transistor 141 = OFF, the selected signal A4 is selected, and the selected signal A4 is output as the output signal X.

When the selected signal A4 = “H”, the NPN transistor 140 = ON, the NPN transistor 139 = OFF, the collector of the NPN transistor 139 = “H”, and the output signal X = “H”. Becomes

On the other hand, when the selected signal A4 = “L”, the NPN transistor 140 = OFF, NPN
Transistor 139 = ON, NPN transistor 13
The collector of 9 = “L”, and the output signal X = “L”.

When the delay time selection signal C1 = "L" and the delay time selection signal C2 = "L", the NPN transistor 136 = OFF, the NPN transistor 143 = ON,
The NPN transistor 142 = OFF and the NPN transistor 141 = ON, the selected signal A3 is selected, and the selected signal A3 is output as the output signal X.

Here, when the selected signal A3 = “H”, the NPN transistor 137 = ON, the NPN transistor 138 = OFF, the collector of the NPN transistor 138 = “H”, and the output signal X = “H”. Becomes

On the other hand, when the selected signal A3 = “L”, the NPN transistor 137 = OFF, NPN
Transistor 138 = ON, NPN transistor 13
8 collector = “L” and output signal X = “L”.

Here, in the second embodiment, eight steps can be obtained as the delay step, Table 8 shows the relationship between the delay step and the path of the delayed signal SI, and Table 9 shows the delay step and the delayed step. It shows the relationship with the delay time that the delay signal SI receives.

However, in Table 8, T91 is a delayed signal input terminal 91, and DGs 98 to 104 are delay gate circuits 98.
To 104 and SLs 106 to 108 are selectors 106 to 10.
8, T95 are delay signal output terminals.

Further, in Table 9, t (DG) is the delay time of each of the delay gate circuits 98 to 104, ± Δ
t (DG) is the variation in the delay time of each of the delay gate circuits 98 to 104.

Further, t (SL) is the selectors 106-108.
Of each of the selectors 106 to 108, ± Δt (SL) is a variation of the delay time of each of the selectors 106 to 108.

[0083]

[Table 8]

[0084]

[Table 9]

Therefore, the delay time difference between the adjacent delay steps and the variation in the delay time difference are as shown in Table 10 when the path of the delayed signal SI in each delay step shown in Table 8 is taken into consideration, and Δt ( SL) = about Δ
Considering that t (DG) is set, it becomes as shown in Table 11.

[0086]

[Table 10]

[0087]

[Table 11]

As described above, in the second embodiment,
Minimum delay time difference between delay steps = ± Δ
t (DG), maximum value = ± 3Δt (DG), and the variation in the delay time between the delay steps can be made smaller than in the case of the first embodiment (see Table 7).

Therefore, according to the second embodiment, it is possible to improve the linearity of the delay characteristic and obtain the delay signal SO having a higher delay accuracy than that of the first embodiment.

Third Embodiment ... FIG. 7 and FIG. 8 FIG. 7 is a circuit diagram showing an essential part of a third embodiment of the present invention.
In the figure, 154 is a delayed signal input terminal to which the delayed signal SI is input, and 155 is a signal path switching signal input terminal to which a signal path switching signal E for switching the signal path is input.

Reference numerals 156 to 158 denote delay time selection signal input terminals to which the delay time selection signals C1 to C3 for selecting the delay time are input, and 159 delays the delayed signal SI input to the delayed signal input terminal 154. Delay signal SO
Is a delayed signal output terminal to which is output.

Reference numeral 160 denotes a delay circuit section having an input terminal 161 connected to the delayed signal input terminal 154.
Reference numeral 62 is a non-NOT / NOT circuit, and 163 to 169 are delay gate circuits connected in cascade to output delay signals D _{1 to} D ₇ obtained by delaying the delayed signal SI. Note that 170
183 to 183 are OR circuits (logical sum circuits), and 184 to 190 are AND circuits (logical product circuits).

These delay gate circuits 163-169 are
For example, as shown in the circuit diagram of FIG. 8, it is composed of a series gate of an ECL circuit. In the figure, 191 is a VCC power supply line, 192 is a VEE power supply line, 193 is an OR-AND processing circuit section, and 194 is an output circuit section.

Reference numerals 195 and 196 denote delayed signals A (S
I, D _{1 to} D ₆ ) is input to the delayed signal input terminal, 19
7 is a signal path switching signal input terminal to which the signal path switching signal E output from the non-NOT / NOT circuit 162 is input;
Reference numeral 198 denotes an inverted signal path switching signal input terminal to which the inverted signal path switching signal / E output from the non-NOT / NOT circuit 162 is input.

Reference numeral 199 is a reference voltage input terminal to which the reference voltage VB1 is input, 200 is a reference voltage input terminal to which the reference voltage VB2 is input, 201 is a reference voltage input terminal to which the reference voltage VCS is input, and 202 is a delay. Signal X (D ₁ ~
D ₇ ) is an output terminal, 203 is a diode, 2
Reference numerals 04 to 213 are NPN transistors, and reference numerals 214 to 219 are resistors.

In this delay gate circuit, the signal path switching signal E = “H” and the inverted signal path switching signal / E =
In the case of “L”, when the delayed signal A = “H”,
NPN transistor 209 = ON, NPN transistor 210 = OFF, NPN transistor 206 = ON, N
With the PN transistor 207 = OFF and the NPN transistor 208 = OFF, the collector of the NPN transistor 208 = “H” and the output signal X = “H”.

On the other hand, the signal path switching signal E =
In the case of “H” and the inverted signal path switching signal / E = “L”, when the delayed signal A = “L”, the NPN transistor 209 = ON and the NPN transistor 210 = OF.
F, NPN transistor 206, 207 = OFF, NP
N transistor 208 = ON, NPN transistor 2
The collector of 08 = “L” and the output signal X = “L”.

When the signal path switching signal E = “L” and the inverted signal path switching signal / E = “H” and the delayed signal A = “H”, the NPN transistor 209 = O.
N, NPN transistor 210 = OFF, NPN transistors 206 and 207 = ON, NPN transistor 20
8 = OFF, NPN transistor 208 collector =
The output signal becomes "H" and the output signal X becomes "L".

On the other hand, the signal path switching signal E =
When the delayed signal A is "L" in the case of "L" and the inverted signal path switching signal / E = "H", the NPN transistor 209 = OFF and the NPN transistor 210 = ON.
Then, the collector of the NPN transistor 210 becomes "L", and the output signal X becomes "L".

As described above, in this delay gate circuit, if the active state of the delayed signal A is "L", the signal path switching signal E = "H" and the inverted signal path switching signal / E = "L". , And the signal path switching signal E =
Since the path of the delayed signal A is different from that in the case of “L” and the inverted signal path switching signal / E = “H”, different delay times are obtained by changing the logic level of the signal path switching signal E. Obtainable.

In FIG. 7, 220 is the delayed signal A input to the delayed signal input terminal 154 and the delayed signals D _{1 to} D ₇ output from the delay gate circuits 163 to 169.
Of the delay time selection signals C1 to C3, and selects and outputs the selected signal.

221 and 222 are 4-input selectors, 223 is a 2-input selector, and the 4-input selectors 221 and 222 are, for example, configured as shown in the circuit diagram of FIG. 223 is, for example, in FIG.
It is configured as shown in the circuit diagram.

In the third embodiment, when the signal path switching signal E = "H", the delayed signal input terminal 154 is used.
The path in the delay circuit section 160 of the delayed signal SI input to the circuit is OR circuit 170 → AND circuit 184 → OR circuit 172 → AND circuit 185 → OR circuit 174 → AND
Circuit 186 → OR circuit 176 → AND circuit 187 → OR
Circuit 178 → AND circuit 188 → OR circuit 180 → AN
The D circuit 189 → OR circuit 182 → AND circuit 190.

On the other hand, the signal path switching signal E =
When set to “L”, the path of the delayed signal SI input to the delayed signal input terminal 154 in the delay circuit section 160 is OR circuit 171 → AND circuit 184 → OR circuit 1
73 → AND circuit 185 → OR circuit 175 → AND circuit 186 → OR circuit 177 → AND circuit 187 → OR circuit 179 → AND circuit 188 → OR circuit 181 → AND circuit 189 → OR circuit 183 → AND circuit 190
It is possible to obtain the delay signals D _{1 to} D ₇ having different delay times from the delay signals D _{1 to} D ₇ obtained when the signal path switching signal E = “H”.

Here, and in the third embodiment, the selection circuit section 220 is the same as the selection circuit section 10 of the second embodiment.
Since it is configured in the same manner as in No. 5, the signal path switching signal E =
In the case of "H", eight steps can be obtained as the delay step, and the signal path switching signal E =
When "L" is set, eight delay steps can be obtained as delay steps, which have different delay times from those when the signal path switching signal E = "H" is set.

The delay gate circuits 163-169 provided in the third embodiment and the delay gate circuits 98-104 provided in the second embodiment have different circuit configurations. Since the circuits are connected in cascade like the circuits 98 to 104, the magnitude of the variation in the delay time between the adjacent delay steps can be considered as in the case of the second embodiment.

Therefore, according to the third embodiment, the linearity of the delay characteristic is improved, the delay accuracy is higher than that of the first embodiment, and the delay signals of two kinds of delay steps having different delay times are used. SO can be obtained.

Fourth Embodiment ... FIG. 9 and FIG. 10 FIG. 9 is a circuit diagram showing an essential part of a fourth embodiment of the present invention.
In the figure, 224 is a delayed signal input terminal to which the delayed signal SI is input, and 225 is a signal path switching signal input terminal to which a signal path switching signal E for switching the signal path is input.

226 to 228 are delay time selection signal input terminals to which the delay time selection signals C1 to C3 for selecting the delay time are input, and 229 delays the delayed signal SI input to the delayed signal input terminal 224. Delay signal SO
Is a delayed signal output terminal to which is output.

Reference numeral 230 denotes a delay circuit section having an input terminal 231 connected to the delayed signal input terminal 224, and 2
Reference numeral 32 is a non-NOT / NOT circuit, and 233 to 239 are cascaded delay gate circuits that output delayed signals D _{1 to} D ₇ obtained by delaying the delayed signal SI. Note that 240
˜253 are OR circuits, and 254˜260 are Ex-NOR circuits (non-exclusive OR circuits).

These delay gate circuits 233 to 239 are
For example, as shown in the circuit diagram of FIG. 10, it is composed of a series gate of an ECL circuit. In the figure, 261 is a VCC power supply line, 262 is a VEE power supply line, 263 is an Ex-NOR processing circuit section, and 264 is an output circuit section.

265 and 266 are the delayed signals A (S
I, D _{1 to} D ₆ ) is input to the delayed signal input terminal, 26
7 is a signal path switching signal input terminal to which the signal path switching signal E output from the non-NOT circuit / NOT circuit 232 is input, and 268 is an inverted signal path switching signal / E output from the non-NOT circuit / NOT circuit 232. This is an input terminal for an inverted signal path switching signal to be input.

Reference numeral 269 is a reference voltage input terminal to which the reference voltage VB1 is input, 270 is a reference voltage input terminal to which the reference voltage VB2 is input, 271 is a reference voltage input terminal to which the reference voltage VCS is input, and 272 is a delay. Signal X (D ₁ ~
D ₇ ) is output from the output terminal, 273 is a diode, 2
74 to 286 are NPN transistors and 287 to 292 are resistors.

In this delay gate circuit, the signal path switching signal E = “H” and the inverted signal path switching signal / E =
In the case of “L”, when the delayed signal A = “H”,
NPN transistor 282 = ON, NPN transistor 283 = OFF, NPN transistor 276 = ON, N
The PN transistor 277 = OFF, the NPN transistor 278 = OFF, the collector of the NPN transistor 278 = “H”, and the output signal X = “H”.

On the other hand, the signal path switching signal E =
In the case of “H” and the inverted signal path switching signal / E = “L”, when the delayed signal A = “L”, the NPN transistor 282 = ON and the NPN transistor 283 = OF.
F, NPN transistor 276 = OFF, NPN transistor 277 = OFF, NPN transistor 278 = O
The collector of the N and NPN transistors 278 = “L”, and the output signal X = “L”.

When the signal path switching signal E = “L” and the inverted signal path switching signal / E = “H” and the delayed signal A = “H”, the NPN transistor 282 = O.
N, NPN transistor 283 = OFF, NPN transistor 280 = ON, NPN transistor 281 = O
N, NPN transistor 279 = OFF, collector of NPN transistor 279 = “H”, output signal X =
It becomes "H".

On the other hand, the signal path switching signal E =
In the case of “L” and the inverted signal path switching signal / E = “H”, when the delayed signal A = “L”, the NPN transistor 282 = OFF, the NPN transistor 283 = ON,
NPN transistor 280 = ON, NPN transistor 281 = OFF, NPN transistor 279 = ON, N
The collector of the PN transistor 279 is "L", and the output signal X is "L".

As described above, in this delay gate circuit, if the active state of the delayed signal A is "L", the signal path switching signal E = "H" and the inverted signal path switching signal / E = "L". , And the signal path switching signal E =
Since the path of the delayed signal A is different from that in the case of “L” and the inverted signal path switching signal / E = “H”, different delay times are obtained by changing the logic level of the signal path switching signal E. Obtainable.

In FIG. 9, reference numeral 293 denotes the delayed signal A input to the delayed signal input terminal 224 and the delayed signals D _{1 to} D ₇ output from the delay gate circuits 233 to 239.
Of the delay time selection signals C1 to C3, and selects and outputs the selected signal.

Note that 294 and 295 are 4-input selectors, 296 is a 2-input selector, and the 4-input selectors 294 and 295 are, for example, configured as shown in the circuit diagram of FIG. 296 is, for example, FIG.
It is configured as shown in the circuit diagram.

In the fourth embodiment, when the signal path switching signal E = “H”, the delayed signal input terminal 224 is used.
The path of the delayed signal SI input to the delay circuit section 230 is OR circuit 240 → Ex-NOR circuit 254 →
OR circuit 242 → Ex-NOR circuit 255 → OR circuit 2
44 → Ex-NOR circuit 256 → OR circuit 246 → Ex
-NOR circuit 257 → OR circuit 248 → Ex-NOR circuit 258 → OR circuit 250 → Ex-NOR circuit 259 →
The OR circuit 252 becomes the Ex-NOR circuit 260.

When the signal path switching signal E = “L”, the path of the delayed signal SI input to the delayed signal input terminal 224 in the delay circuit section 230 is OR circuit 241 → Ex-NOR. Circuit 254 → OR circuit 243 →
Ex-NOR circuit 255 → OR circuit 245 → Ex-NO
R circuit 256 → OR circuit 247 → Ex-NOR circuit 25
7 → OR circuit 249 → Ex-NOR circuit 258 → OR circuit 251 → Ex-NOR circuit 259 → OR circuit 253 →
It becomes the Ex-NOR circuit 260, and the signal path switching signal E =
It is possible to obtain the delay signals D _{1 to} D ₇ different in delay time from the delay signals D _{1 to} D ₇ obtained in the case of “H”.

Here, and in the fourth embodiment, the selection circuit section 293 is the same as the selection circuit section 10 of the second embodiment.
Since it is configured in the same manner as in No. 5, the signal path switching signal E =
In the case of "H", eight steps can be obtained as the delay step, and the signal path switching signal E =
When "L" is set, eight delay steps can be obtained as delay steps, which have different delay times from those when the signal path switching signal E = "H" is set.

Although the delay gate circuits 233 to 239 provided in the fourth embodiment and the delay gate circuits 98 to 104 provided in the second embodiment have different circuit configurations, the delay gate circuits 233 to 239 are different in delay gate circuit. Since the circuits are connected in cascade like the circuits 98 to 104, the magnitude of the variation in the delay time between the adjacent delay steps can be considered as in the case of the second embodiment.

Therefore, according to the fourth embodiment, the linearity of the delay characteristic is improved, the delay accuracy is higher than that of the first embodiment, and the delay signals of two kinds of delay steps having different delay times are used. SO can be obtained.

First Application Example ... FIG. 11 is a block diagram showing the main part of a first application example of the variable delay circuit of the embodiment of the present invention. The variable delay circuit of the embodiment of the present invention has two outputs. An example is shown when used in the signal generator of.

In the figure, 297 is a signal generating circuit for generating a signal, and 298 is a variable of the embodiment of the present invention, that is, the first embodiment, the second embodiment, the third embodiment or the fourth embodiment of the present invention. The delay circuits 299A and 298B are output circuits.

In this signal generator, the phase between output signals A and B can be adjusted by adjusting the delay time of variable delay circuit 298.

Here, the conventional signal generator is
Since a variable delay circuit including a variable length coaxial tube driven by a motor is used to adjust the phase between the output signals A and B, there is a problem that the device becomes large.

However, as shown in FIG. 11, by using the variable delay circuit according to the embodiment of the present invention which is formed as an integrated circuit, the device can be downsized and the phase between the output signals can be reduced. The adjustment can be performed with high accuracy.

Second Application Example ... FIG. 12 and FIG. 13 FIG. 12 is a block diagram showing a main part of an example of an IC tester. 300 is an IC to be tested, 301 is an IC 30.
A signal generator 302 for generating a signal to be supplied to
A measuring unit that measures the phase and the like of the signal output from C300, and a control unit 303 that controls the signal generating unit 301 and the measuring unit 302.

FIG. 13 is a block diagram showing an essential part of a second application example of the embodiment of the present invention. When the embodiment of the present invention is used in the signal generator 301 of the IC tester shown in FIG. Shows an example.

In the figure, 304 is a signal generating circuit for generating a signal, 305A, 305B and 305H are variable delay circuits according to the embodiment of the present invention, and 306A, 306B and 306H are output circuits.

In this IC tester, the phase between output signals A, B ... H can be adjusted by adjusting the delay time of variable delay circuits 305A, 305B ... 305H.

Here, in the conventional IC tester, a variable delay circuit having a large external size, which is a variable length coaxial tube driven by a motor, cannot be incorporated in the apparatus, and therefore phase adjustment between output signals is performed. It has a problem that it cannot be performed with high accuracy.

However, since the variable delay circuit of the embodiment of the present invention is an integrated circuit, it can be incorporated in the IC tester as shown in FIG. 13, whereby the phase between output signals can be increased. The adjustment can be performed with high accuracy.

[0137]

As described above, according to the present invention, the delay means (20 ₁ , 20 ₂ ... 20 _n ) are connected in cascade, and the input end (19) is connected to the delayed signal input terminal (16). A delay circuit section (18) connected to the delay signal section (18) and a plurality of selectors connected in a tree shape, and the delayed signal (SI) input to the delayed signal input terminal (16) and the delay means (20 ₁ ,
20 ₂ ... 20 _n ) output delayed signals (D ₁ , D ₂
Selects a desired signal from the · · · D _n), by which is to be constructed by the selection circuit section for outputting a delay signal in the delay signal output terminal (17) (SO) a (21) is provided, adjacent It is possible to reduce variations in delay time between the delay steps to be performed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a main part of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a delay gate circuit which constitutes the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a two-input selector that constitutes the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration example of a 4-input selector which constitutes a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration example of a delay gate circuit which constitutes a third embodiment of the present invention.

FIG. 9 is a circuit diagram showing a main part of a fourth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration example of a delay gate circuit which constitutes a fourth embodiment of the present invention.

FIG. 11 is a block diagram showing a main part of a first application example of the embodiment of the present invention.

FIG. 12 is a block diagram showing a main part of an example of an IC tester.

FIG. 13 is a block diagram showing a main part of a second application example of the embodiment of the present invention.

FIG. 14 is a circuit diagram showing a main part of an example of a conventional variable delay circuit.

[Explanation of symbols]

16 Delayed Signal Input Terminal 17 Delayed Signal Output Terminal 18 Delay Circuit Section 19 Input Terminal of Delay Circuit Section 20 ₁ , 20 ₂ , 20 _n Delay Means 21 Selection Circuit Section SI Delayed Signal SO Delayed Signal

Claims (4)

[Claims] 1. A plurality of delay means (20 ₁ , 20 ₂ ... 20)
_n ) are connected in cascade and the input terminal (19) is connected to the delayed signal input terminal (16)
And a plurality of selectors are connected in a tree shape, and the delayed signal (S) is input to the delayed signal input terminal (16).
I) and the delay means (20 ₁ , 20 ₂ ... 20)
_n ) a plurality of delayed signals (D ₁ , D ₂ ...
A selection circuit unit (2) for selecting a desired signal from D _n ) and outputting the delay signal (SO) to the delay signal output terminal (17)
1) and a variable delay circuit. 2. The plurality of delay means (20 ₁ , 20 ₂ ...
20 _n ) is a first OR circuit in which the delayed signal is input to one input terminal and a control signal for controlling the passage of the delayed signal is input to the other input terminal, and one input A second logical sum circuit having the delayed signal input to a terminal and a control signal having an inverted relationship with the control signal input to the other input terminal, and one input terminal of the first logical sum circuit. The output is input, and the second input is applied to the other input terminal.
2. The variable delay circuit according to claim 1, wherein a composite gate circuit consisting of an AND circuit to which the output of the OR circuit is input is constituted by a series gate of an ECL circuit. 3. The plurality of delay means (20 ₁ , 20 ₂ ...
20 _n ) has a delayed signal input to one of its input terminals,
A first OR circuit in which a control signal for controlling passage of the delayed signal is input to the other input terminal, the delayed signal is input to one input terminal, and the control signal is input to the other input terminal A second logical sum circuit to which a control signal having an inversion relation is inputted, and an output of the first logical sum circuit is inputted to one input terminal, and an output of the second logical sum circuit is inputted to the other input terminal. 2. The variable delay circuit according to claim 1, wherein a composite gate circuit consisting of a non-exclusive OR circuit to which is input is constituted by a series gate of an ECL circuit. 4. The selector according to claim 1, wherein the plurality of selectors include selectors having three or more inputs, and the selectors at the same stage are selectors having the same circuit configuration. 3. The variable delay circuit described in 3.