JPH0631997B2 - Output holding circuit of voice detector - Google Patents

Description

TECHNICAL FIELD The present invention relates to an output holding circuit of a voice detector.

(Prior art and its problems) A voice detector is mainly incorporated in a DSI (Digital Speech Interpolation) device and used to determine whether or not there is a voice signal in an input channel to the DSI device. . Regarding DSI equipment, for example, refer to the document Comsat Technical Review (COMSAT) issued in March 1976.
TECHNICAL REVIEW) vol.6, No.1 (hereinafter referred to as Reference 1)
SJ Campanella's paper "Digital Speech interpolatio" on pages 127-158 of
n) ”.

The output holding circuit of the speech detector eliminates the artifacts caused by the sensitivity of the ear to cuts to fine signals between words or phrases in a conversation, or to prevent word endings. Therefore, even if the voice judgment circuit is silent, it is used for a while (this time is called a hangover time) to maintain the voice detector output in the voiced state.

What is required of the output holding circuit is that it can be realized with simple hardware, and by adding it, it is possible to provide a voice detector having the ability to prevent unnaturalness during conversation due to cutting or dropping of words. .

FIG. 1 is a block diagram showing an example of a voice detector using the level detection method. From the input terminal 1, the output terminal 2, the code conversion circuit 3, the level detection circuit 4, the determination circuit 5, and the output holding circuit 6, FIG. The part that is configured and is surrounded by a broken line 7 is a voice determination unit, and the part that is surrounded by a broken line 8 is an output holding unit. For example, a PCM-encoded input signal is input from the input terminal 1 and sent to the code conversion circuit 3. In the code conversion circuit 3,
The PCM code is converted into a linear code or a code convenient for subsequent signal processing, and sent to the level detection circuit 4. The level detection circuit 4 compares the code-converted input signal with a predetermined threshold value or a threshold value varying according to the signal level of the input signal, and sends the result to the determination circuit 5.
The judgment circuit 5 judges from the output of the level detection circuit 4 whether or not the input signal includes a voice signal, and sends the result to the output holding circuit 6.

In the output holding circuit 6, not only when the output of the determination circuit 5 is 1, that is, when the determination circuit notifies that the input signal includes the audio signal, the output of the determination circuit further changes from 1 to 0. Even if it changes, the output is held at 1 for a certain period of time.

It should be noted that the input signal input from the input terminal 1 here is PC
Although the M code signal is taken as an example, another code signal may be input, and in that case, the code conversion circuit 3 may be changed according to the input signal input.

By the way, as a conventional example of the output holding time of the output holding circuit (hereinafter referred to as a hangover time), the above-mentioned Document 1 is used.
J. Jankowski, JR., Pp. 159-176, `` (A new digital voice activated switc
h) ”by 170ms.

However, if the hangover time is fixed as in this paper, the output hold circuit adds a hangover time of 170 ms when it is determined that the signal is a voice signal, no matter how short the noise is. This leads to an increase in the malfunction time rate (time ratio in which malfunction occurs) and an increase in the voice operation ratio (time ratio in which the output of the sound detector is ON). This makes effective use of the line difficult by using the DSI device.

(Object of the Invention) An object of the present invention is to provide an output holding circuit in which the malfunction time rate and the voice operation rate are reduced with simple hardware.

(Structure of the Invention) According to the present invention, an audio determination unit that determines the presence or absence of an input sampled audio signal and an output of the audio determination unit is held for a certain period from the time when the audio determination unit notifies the end of the audio signal. And a means for controlling the stepping direction of the reversible counter based on the output of the voice determination unit, and the reversible counter. Means for determining the output of the voice detector by comparing the content of the voice detector with a predetermined threshold value, and a plurality of data according to the content of the reversible counter at the time when the voice determination unit notifies the end of the voice signal. And a means for setting the reversible counter to the reversible counter, wherein a plurality of different predetermined holding times can be set according to the sound duration. A holding circuit is obtained.

(Principle of the Invention) Next, the principle of the present invention will be described. In the present invention, the hangover time is assigned according to the length of the signal duration of the voice signal included in the input signal, and the malfunction time rate and the voice operation rate are reduced.

For example, a signal (35
When a short (short) hangover time of about 20 ms is assigned to a signal (about ms or less) and a long (long) hangover time of about 160 ms is assigned to a relatively long signal (about 40 ms or more). Taking the (variable hangover method) as an example, let's compare the 170ms fixed hangover method with the malfunction time ratio.

In the variable hangover method, the malfunction time rate when T times noise is determined to be a voice signal in N seconds is In contrast to the fixed hangover method, And the ratio of the two Therefore, the variable hangover method reduces the malfunction time rate to about 1/8 of that of the fixed hangover method.

Although the malfunction time rate was calculated assuming that short hangover is added when noise is determined to be a voice signal, it is determined to be a voice signal when malfunction occurs due to noise in an actual system. In most cases, a short hangover is added due to the short duration of noise that occurs.

Although the malfunction time rate has been described above as an example, a reduction in the voice activity rate can be expected by using the variable hangover method. As described above, in the present invention, the above-mentioned variable hangover system is realized with simple hardware,
We are trying to reduce the malfunction time rate and voice operation rate.

(Example) Next, this invention is demonstrated in detail using drawing.

FIG. 2 shows an embodiment of the output holding circuit of the present invention, which is a voice judgment result input terminal 10 and a sampling pulse input terminal 1.
1, audio detector output terminal 12, control pulse generation circuit 1
3, a setting pulse generation circuit 14, a reversible counter 15, a data determination circuit 16, data input terminals 19 and 20, a holding time determination circuit 17, a comparison circuit 18, and threshold value input terminals 21 and 22.

In the control pulse generation circuit 13, the audio determination result input from the input terminal 10, the sampling pulse input from the input terminal 11, and the output of the setting pulse generation circuit 14 described later.
From 141, the output 171 of the holding time determination circuit 17 described later, and the output 181 of the comparator 18 described later, control pulses 131, 133 for controlling the stepping of the reversible counter 15 described later are generated.
Specifically, when the voice determination result is 1, a control pulse 131 for stepping positively is generated, and when it is 0, a control pulse 133 for stepping negatively is generated in synchronization with a clock obtained by thinning sampling repulses. . However, the cycle of the control pulse 131 for stepping positively and the control pulse 133 for stepping negatively are usually the same, but the data determination circuit 16 to be described later is described.
When the data for long hangover and the contents of the reversible counter are selected in, the cycle of the control pulse 133 for stepping negatively for the purpose of effectively utilizing the bit number of the counter is several times as long as the normal case (specifically, Is designed to be about 4 times).

At the same time, the control pulse generation circuit 13 also generates a selection signal 132 of the data determination circuit 16 described later.

In the set pulse generation circuit 14, the voice determination result input from the input terminal 10 is input, the falling time point (time point when the value of the input signal changes from 1 to 0) is detected, and the result is
It outputs to the control pulse generation circuit 13 and the reversible counter 15 described above.

The reversible counter 15 monitors the audio signal by incrementing the content by positive and negative by the control pulses 131 and 133 output from the control pulse generation circuit 13 when the audio determination result output repeats 1 and 0. Furthermore, since the setting pulse 141 is output from the setting pulse generation circuit 14 when the audio signal ends, the output data 161 from the data determination circuit 16 to be described later is set in the reversible counter by the setting pulse 141, and from that value to zero. The time to step to is added as the hangover time.

The data determination circuit 16 outputs the short hangover data input from the input terminal 19 using the output 132 of the control pulse generation circuit 13 and the output 171 of the holding time determination circuit 17, which will be described later, as selection signals. It is determined whether to output the further input data for long hangover or the output (content) 151 of the reversible counter 15 as it is, and output it to the reversible counter 15. Specifically, when the output 171 of the holding time determining circuit 17 is 2, that is, when a long hangover is added, the long hangover data input from the input terminal 20 is selected, and the holding time determining circuit 17 is selected. Output of 17
When 1 is 0 and the output 132 of the control pulse generation circuit 13 is 1, the output 151 of the reversible counter 15 is selected, and when the output 171 of the holding time determination circuit 17 is 0 and the control pulse generation circuit When the output 132 of 13 is 0, the data for short hangover is selected.

The holding time determination circuit 17 outputs the output 151 of the reversible counter 15.
Is compared with a predetermined threshold value input from the input terminal 21, and if the former is larger, 1 is added to add a long hangover, and if not, 0 is set to the control pulse generation circuit 13 and the data determination circuit. Output to 16.

The comparison circuit 18 compares the output 151 of the reversible counter 15 with a predetermined threshold value input from the input terminal 22,
If the former is large, 1 is output, and if not, 0 is output from the terminal 12 as the output 181 of the voice detector.

In order to deepen the understanding further, a description will be given by taking as an example the case where the audio signal including the waveform 30 and the waveform 31 shown in FIG. 3A arrives at the audio detector having the holding time determining circuit of the present invention. . However, the waveforms 32 and 33 shown in FIG. 3 (b) are the outputs of the voice determination unit of the voice detector corresponding to the input signal waveforms 30 and 31, that is, the inputs of the output holding unit, and T ₁ , T ₂ , T ₃ and T ₄ are the rising and falling times of the waveform 32 and the waveform 33, and the time from time T ₁ to T ₂ is assumed to be long enough to add a long hangover. The time from ₃ to T ₄ shall be short enough to add a short hangover, and from time T ₂
Time of up to T ₃ is shorter than the long hangover time.

First, when the waveform 30 arrives, the waveform 32 is output from the voice determination unit and input to the output holding circuit from the input terminal 10, the control pulse generation circuit 13 causes the control pulse to advance the content of the reversible counter 15 to the positive direction. 131 is output, and the contents of the reversible counter 15 increase from time T ₁ to T ₂ . However, if the maximum value of the contents of the reversible counter is fixed, it will peak as shown in (c) of FIG.

Then, at time T ₂ , when the output of the audio determination unit notifies the end of the audio signal (which can be seen by the fall of the waveform 32), the setting pulse 141 output from the setting pulse generation circuit 14 is output and at the same time the holding pulse is held. Output 171 of time determination circuit 17
Becomes 1, the data deciding circuit 16 selects the data for long hangover and outputs it to the reversible counter. Therefore, this data is set in the reversible counter.

After that, when the output of the voice determination unit continues to be 0, the control pulse generating circuit 13 outputs the control pulse 133 for incrementing the content of the reversible counter 15 in the negative direction, and the content of the reversible counter 15 starts from the time T _2. It decreases until T ₃ .

Then, at time T ₃ , when the output of the voice determination unit becomes 1 as shown in the waveform 33, the contents of the reversible counter 15 increase until time T ₄ , as at times T ₁ to T ₂ , and When the end of the audio signal is notified at time T ₄ , even if the output 171 of the holding time determination circuit 17 is 0, if the output of the control pulse generation circuit 13 is held at 1, the data determination circuit 16 Since the output 151 of the reversible counter 15 is selected, the data for short hangover is not selected.

After that, the content of the reversible counter 15 advances negatively by the control pulse 133 output from the control pulse generation circuit 13, and eventually becomes 0.

In this way, the content (output) of the reversible counter 15 becomes the waveform 34 shown in (c) of FIG. 3, and if its output is compared with 0, the waveform 35 shown in (d) of FIG. 3 is obtained. The
This is the output of the voice detector.

Considering the case where a similar signal arrives at a voice detector having an output holding circuit adopting a fixed hangover system, a long hangover is added at time T ₂ shown in (b) of FIG. At the same time, a long hangover is added even at time T ₄ , which leads to an increase in the voice activity rate.

As described above, in the present invention, one set of reversible counters has a role of monitoring the signal duration of the audio signal and a role of realizing the variable hangover system, that is, a role of adding short hangover and long hangover. As a result, the hardware scale can be reduced, and the variable hangover method is used, so reductions in the malfunction time rate and voice operation rate can be expected.

The circuit of FIG. 4 can be used as the control pulse generating circuit 13 used in the present invention, and the input terminals 40, 41, 42, 43, 44, multiplexers 49, 53, 1 sample delay circuit 50, frequency dividing circuit 5 are used.
1, 52, output terminals 45, 46, 47, logical product circuits 48, 54, 55, 56 and logical sum circuit 57. In the AND circuit 48, the setting pulse generation circuit 1 input from the input terminal 40
The output 141 of 4 and the output 171 of the holding time determination circuit 17 input from the input terminal 41 are ANDed, and the result 481 is output as a selection signal of the multiplexer 49 and an input signal on one side. The multiplexer 49 inputs the above-mentioned input signal and the output 501 of the 1-sample delay circuit 50, selects one of them according to the selection signal, and outputs it to the 1-sample delay circuit 50. The output 501 of the 1-sample delay circuit 50 becomes the selection signal of the multiplexer 53 and the selection signal 132 of the data decision circuit 16 at the same time. However, when the output 181 of the comparator 18 input from the input terminal 44 is 0, it is cleared. To be done.

In the multiplexer 53, the output 501 of the one-sample delay circuit 50 is used as a selection signal, and the sampling pulse 511 input from the input terminal 42 and divided by 10 in the frequency dividing circuit 51 or the output 511 of the frequency dividing circuit 51 is further frequency-divided. 52
Either the sampling pulse divided by 4 is selected and output. The logic circuit 54 calculates the logical product of the signal obtained by inverting the voice determination result output input from the input terminal 43 and the output of the multiplexer 53, and outputs the result as the negative step control pulse 133 of the reversible counter from the output terminal 46. Output.

Further, the logical product circuit 55 takes the logical product of the audio determination result output input from the input terminal 43 and the sampling pulse 511 divided by 10 in the frequency dividing circuit 51, and outputs the logical product, while the logical product circuit 56 inputs the logical product. The logical product of the signal obtained by inverting the output 181 of the comparator 18 input from the terminal 44 and the above-described voice determination result output is obtained and output. Then, in the logical sum circuit 57, the logical sum of the outputs of the above logical product circuits 55 and 56 is taken, and the positive step control pulse of the reversible counter is output from the output terminal 72.
It is output as 131.

As the setting pulse generation circuit 14 used in the present invention,
The circuit shown in FIG. 5 can be used and is composed of an input terminal 60, a one-sample delay circuit 62, a logical product circuit 63 and an output terminal 61, and the logical product circuit 63 inverts the voice judgment result output input from the input terminal 60. The logical product of the signal and the output signal of the one-sample delay circuit 62 is calculated, and the result is output from the output terminal 61 as the setting pulse 141. By doing so, the trailing edge of the audio determination result output (output is 1 to 0
It becomes possible to detect the time point (change to) and the setting pulse 141 is output at that time point.

The data determination circuit 16 used in the present invention is the sixth
The circuit shown in the figure can be used and is composed of input terminals 70, 71, 72, 73, 74, multiplexers 76, 77, and output terminal 75. In the multiplexer 76, the output 132 of the control pulse generation circuit 13 input from the input terminal 70 is output. As a selection signal, input terminal 71
Either the output 151 of the reversible counter 15 that is input from the input terminal or the short hangover setting data input from the input terminal 72 is selected.

In the multiplexer 77, the output 171 of the holding time determination circuit 17 input from the input terminal 74 is used as a selection signal, and either the long hangover setting data input from the input terminal 73 or the output 661 of the multiplexer 76 is selected. Is selected and output from the output terminal 75.

By the way, when the selection signal of the multiplexer 49 becomes 1 in the control pulse generating circuit of FIG.
In 9, the output of the AND circuit 48 is selected, in the case of 0, the output 501 of the 1-sample delay circuit 50 is selected, and in the multiplexer 53, the output 501 of the 1-sample delay circuit 50 is 1
The output of the frequency dividing circuit 52 is selected when, and the output 511 of the frequency dividing circuit 51 is selected when 0.

By doing so, when the long hangover is added, the output 481 of the AND circuit 48 becomes 1 and the output 501 of the 1-sample delay circuit 50 becomes 1 after one sampling time. Therefore, from the output terminal 45 of FIG. The output data determination circuit selection signal 132 becomes 1, and the reversible counter negative step control pulse 132 output from the output terminal 46 is synchronized with the sampling pulse divided by 40.

Further, in the multiplexer 76 of the data decision circuit of FIG. 6, when the output 132 of the control pulse generation circuit input from the input terminal 70 is 1, the output 151 of the reversible counter input from the input terminal 71 is selected and set to 0. Sometimes input terminal 7
The short hangover setting data input from 2 is selected, and the multiplexer 77
Then, when the output 171 of the holding time determination circuit input from the input terminal 74 is 1, the long hangover setting data input from the input terminal 73 is selected, and when it is 0, the output 661 of the multiplexer 76 is selected. It has become.

By doing so, the output 171 of the holding time determination circuit becomes 1
When the output 132 of the control pulse generation circuit is 0 or 1, the data for long hangover is always selected, and when the output 171 of the holding time determination circuit is 0,
When the output 132 of the control pulse generation circuit is 1, the output 151 of the reversible counter is selected, and when it is 0, the short hangover setting data is selected and desired data can be selected.

As can be seen from the above, the content of the reversible counter is selected by the data decision circuit when the output of the holding time decision circuit is 0 and the output of the 1-sample delay circuit 50 of FIG. 4 is 1.
This is the case, and corresponds to the case where a signal as shown in FIG. 3 arrives.

(Effects of the Invention) As described above, the output holding circuit according to the present invention is
A role of monitoring the signal duration of the audio signal in a set of reversible counters by using a simple data decision circuit;
By having the role of adding short hangover and long hangover at the same time, it is possible to reduce the hardware scale, and at the same time malfunction while maintaining the ability to prevent unnaturalness caused by cutting or dropping words during conversation. It can be measured whether the time rate or voice activity rate is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a voice detector, FIG. 2 is a block diagram showing an output holding circuit according to the present invention, and FIG.
(A)-(d) is a figure which shows the waveform of each part of FIG. 2, FIG. 4 is a figure which shows a part of FIG. 2, FIG. 5 is a figure which shows the other part of FIG. , FIG. 6 is a view showing another part of FIG. 2. In FIG. 2, 13 is a means for controlling the stepping direction of the reversible counter, 15 is a pair of reversible counters that step forward and negative, 18 is a means for determining the output of the voice detector, and 23. Indicates a means for setting a plurality of data in the reversible counter.

Claims (1)

[Claims] 1. An audio determination unit that determines the presence or absence of an input sampled audio signal, and an output holding unit that holds the output of the audio determination unit for a certain period of time after the audio determination unit notifies the end of the audio signal. In the constituted voice detector, a pair of reversible counters that advance in positive and negative directions, a unit that controls the stepping direction of the reversible counter by the output of the voice determination unit, and the contents of the reversible counter are predetermined. Means for determining the output of the voice detector by comparing with the threshold value, and a plurality of data is set in the reversible counter according to the contents of the reversible counter at the time when the voice determination unit notifies the end of the voice signal. And an output holding circuit for a voice detector, wherein a plurality of different predetermined holding times are set according to the voice duration.