JPH06162067A - Device and method for controlling vector instruction - Google Patents

Abstract

PURPOSE:To execute a vector operation at a high speed by executing only a valid operation without executing an invalid operation, even if an arithmetic inhibiting bit in a vector mask register exists discontinuously. CONSTITUTION:The device consists of an instruction precedent stage for storing only an element and an element number of vector data in which an element value of a vector mask bit instructs to execute an operation in a buffer device 500, in operand vector data designated by an instruction, and an instructions execution stage for reading out the vector data and the element number from the buffer device 500, and writing a result of operation in vector registers 105, 106 in accordance with the element number. Also, in a period in which an instruction register group before by one is executing an instruction execution stage, and instruction precedent control stage of the next instruction register group is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector instruction control method in a data processing apparatus for performing vector operations and a control apparatus therefor, and particularly, in an operation with a mask, an operation permission element in a vector mask is detected, The present invention relates to a vector instruction control device and a control method thereof that can perform processing only on necessary vector elements and eliminate invalid operations by advance control to improve processing performance.

[0002]

2. Description of the Related Art Conventionally, supercomputers have achieved high speed by an arithmetic pipeline system. In order to perform the pipeline processing efficiently, it is necessary to keep the pipe in a clogged state at all times. For that purpose, (a) the program repeats the same operation for a long data series. It is necessary to satisfy the conditions such as including vector calculation (DO loop), having a sufficient data supply capacity for the (b) pipe, and the like. In this way, since vector calculation occupies a major part of the calculation time in large-scale numerical calculation and has the characteristic of being strong in vector calculation, pipeline type scientific and technological computers are called vector computers. . In the case of performing the Bertre operation, the vector elements stored in the vector register are sequentially read out, the vector operation unit performs the operation, and the result is stored in the result vector register. However, of the vector elements stored in the vector register, vector operation mask control is performed so that unnecessary elements are removed by the vector mask stored in the vector mask register. However, in the conventional vector operation mask control,
Even if the operation is suppressed by the vector mask,
The operation was executed, and it was executed so as to suppress only writing of the result.

FIG. 2 is a block diagram of a conventional information processing apparatus for performing vector operation mask control. In FIG. 2, 10
1 is a register for storing the read address, 103 is an incrementer for incrementing the addresses of the vector register and the vector mask register, 105, 10
Reference numerals 6 and 115 are vector registers, 107 is an address register for storing the incremented current address, 110 to 112 and 216 to 218 are delay latches for matching the address and mask elements with the operation time, and 113 is a vector calculator. , 114 is an end detector for detecting the end address to detect the end of the operation, 20
Reference numeral 9 is a vector mask register. In this vector computer, the vector elements held in the vector registers 105 and 106 are transferred to the address register 107.
Sequential reading according to the address in the vector arithmetic unit 1
The result calculated in 13 is stored in the vector register 115. Here, the vector registers 105, 106, 11
It is assumed that the vector operation of A (i) + B (i) = C (i) is being executed during 5 times.

Further detailed operation will be described. When the operation is started, the vector read address register 107 is initialized to "0", so that the 0th data A (0), B (0) of the element is read from the vector registers 105, 106. At the same time, the 0th mask bit is also read from the vector mask register 209. The read data A (0) and B (0) are supplied to the vector calculator 113, where after addition is performed, the data C (0) of the calculation result is stored in the vector register 115. Written. As the write address, the address stored in the address register 107 is input to the vector register 115 via the delay latches 110, 111, 112. That is, the address register 10
The current address stored in 7 becomes the read address of the vector registers 105 and 106, the read address of the vector mask register 209, and the write address of the result vector register 115. In parallel with these operations, the address in the address register 107 is counted up via the register 101 and the incrementer 103 and reset in the address register 107. With this incremented address, the vector register 10
5, 106 to the first data A (1) of the element,
B (1) is read and supplied to the vector calculator 113, and at the same time, the mask bit is also read from the vector mask register 209, and then the calculation result C (1)
Are written into the vector register 115. After that, the same operation is repeatedly executed, the elements in the vector registers 105 and 106 are sequentially processed, and when the end detector 114 detects the processing of the last element, the illustration is omitted via the bus 150. The calculated vector control logic unit is notified of the end of the operation, and the vector operation ends.

The mask bits in the vector mask register 209 have a one-to-one correspondence with the vector elements stored in the vector registers 105 and 106.
When the value of those bits is “1”, the execution of the operation of the corresponding element is permitted, and when the value of these bits is “0”, the execution of the operation of the corresponding element is suppressed. That is, the mask bit "1" means an operation execution bit, and "0" means an operation inhibition bit. The mask bit in the vector mask register 209 is read at the same time when the elements in the vector registers 105 and 106 are read by the address register 107, and acts on the vector register 115 via the delay latches 216 to 218 and the bus 151. Further, the addresses in the address register 107 used for reading these are also the delay latches 110 to 11
2 to the vector register 115. The delay latches 110 to 112 and 216 to 218 are set so that the delay time thereof matches the operation delay time of the vector calculator 113. Therefore, the vector calculator 11
When the calculation result is supplied from 3 to the vector register 115, the address used for reading the vector element for this calculation and the mask bit read corresponding to this element are simultaneously stored in the vector register 115. Will be supplied. As a result, the vector register 1 is read by the read address register 107.
The mask bit of the vector mask register 209, which is read at the same time as the elements in 05 and 106, prohibits the writing of the operation result to the vector register 115 via the bus 151 when the value of the mask bit is "0". Then, when the value of the mask bit is “1”, writing of the operation result to the vector register 115 is permitted.

[0006]

In the conventional mask control method described above, even if the vector mask bit is "0", the operation execution stage runs for the element in which the operation is inhibited, and the operation is executed. Time is wasted. In order to eliminate such waste of calculation time, a vector calculation mask control method disclosed in, for example, Japanese Patent Application Laid-Open No. 58-22446 has been proposed. In this control method, when an operation suppression bit in the vector mask, that is, a bit whose value is' 0 ', is detected, only when a certain number of'0's exist continuously, the operation between them is skipped. Control. That is, for example, when five "0" s are detected, the address incrementer is advanced by five, five vector operations are slid, and the sixth operation is restarted. As a result, it is possible to eliminate waste of calculation time. As described above, the conventional mask control method cannot suppress the arithmetic processing itself when the vector mask bit is “0” in any case, and as a result, the arithmetic time is wasted. was there. Further, even in the method of suppressing the operation when a certain number of vector mask bits are "0", no consideration is given to the case where "0" are discontinuous in the vector mask. Therefore, when there are many discontinuous'0's,
There is a problem that the calculation time is wasted because unnecessary calculation is executed. An object of the present invention is to solve such a conventional problem and execute valid operations only without performing invalid operations even when operation suppression bits in a vector mask register are discontinuous. It is an object of the present invention to provide a vector operation mask control device and a control method capable of processing a vector operation at high speed.

[0007]

In order to achieve the above object, a vector operation mask control device of the present invention is provided with (a) vector data consisting of a plurality of elements and vector mask data are sequentially read out to obtain a vector mask. In a vector instruction control device for calculating vector data according to the element value of the data, a buffer for storing the element of the operand vector data designated by the instruction and the element number prior to the execution step of the instruction. A device and a first address register for designating an address for sequentially storing only an element and an element number of an operand vector data in which an element value of vector mask data instructs execution of an operation And a first address incrementer. Further, (b) a second address register and a second incrementer for reading the operand vector data stored in the buffer device are provided, and an operation is executed using the read operand vector data. It is also characterized. Further, (c) the result of executing the operation using the operand vector data read from the buffer device is written in the vector register according to the element number read from the buffer device. Furthermore, the vector instruction control method of the present invention (d) sequentially reads vector data consisting of a plurality of elements and vector mask data, and calculates the vector data according to the element values of the vector mask data. In the vector instruction control method to be performed, an instruction execution step for sequentially reading the operand vector data and the element number from the buffer device for the previous instruction, executing the operation, and storing the result of the operation in the result register according to the element number. Of the operand vector data specified by the instruction, the vector mask data
It is characterized in that an instruction preceding stage for storing only the element and the element number of the operand vector data in which the element value of the data instructs the execution of the operation in parallel is executed.

[0008]

In the present invention, the vector instruction execution step is executed.
Of the operand vector data specified by the instruction, only the element and the element number of the vector data for which the element value of the vector mask data instructs the execution of the operation prior to To store. That is, an operation invalid in the operation with the mask is excluded by the preceding control. Next, in the instruction execution stage, the vector data and the element number are sequentially read from the buffer device, the operation is executed, and the operation result is written in the vector register according to the element number. As a result, only valid vector operations can be executed, so that vector operations can be processed at high speed. That is, as shown in FIG. 3, assuming that one machine cycle is Tc, and an invalid time for performing an operation of an element whose vector mask bit is '0' is Tα, one vector instruction (n The calculation time for executing the element calculation) is nTc, while the calculation time in the present invention can eliminate n invalid times Tα.
(Tc-Tα). Therefore, when executing a plurality of vector instructions, the operation time can be significantly shortened as compared with the conventional method.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a vector instruction control device showing an embodiment of the present invention. In FIG. 1, reference numeral 1 is an instruction control unit for sequentially outputting instructions such as a decoding instruction, a calculation instruction, a register read instruction, and a write instruction, and 2 is a memory for storing an instruction register group, 3a, 3b, 3c, 103a, 303.
a and 403a are registers for storing read data or addresses, and 103, 303, and 403, respectively.
Is an incrementer for incrementing the address, 500 is a buffer device for storing only valid data by the preceding control, and 500a, 500b, 500c are constituent elements in the buffer device 500, which are vector data A and vector data, respectively. Data B and vector data I
This is an area for storing D. Also, 105, 106, 11
5 is a vector register, 113 is a vector calculator, 5,
Reference numeral 6 is an end detection circuit for detecting the end of the instruction preceding stage and the instruction execution stage, respectively, and 209 is a vector mask register for storing vector mask bits. The portion above the vector registers 105 and 106, the vector mask register 209, and the incrementer 303 is the preceding stage portion of the instruction, and the buffer device 500,
Below the register 403 is an instruction execution stage section. The portion newly installed in the present invention is the buffer device 5
00, the incrementers 303 and 403, and the register 3
03a and 403a, and the end detection circuit 5. That is, in the present invention, since the instruction preceding stage is provided in addition to the conventional vector operation stage, the preceding stage is provided.
Buffer device 500 for storing only valid elements, an incrementer 303 for writing data to the buffer device 500, a register 303a, an element from the buffer device 500, and an arithmetic unit 1
13 and the incrementer 403 and the register 403a for writing the operation result and the instruction preceding step.
The detection circuit 5 for detecting the end of the error is additionally required.

Instructions A, B, and C are sequentially set in the instruction register group storage memory 2, each of which has an OP.
(A), (B) and (C) are instruction parts, VR3 is a field value for storing the vector register number of the operand (3), and VR1 is a field for storing the vector register number of the operand (1) which is the operation result. Field, VR2 is a field that stores the vector register number of operand (2).
Value. First, the operation of the preceding stage of the instruction will be described. When a decoding instruction from the instruction control unit 1 is issued via the signal line 1a, the instructions are sequentially decoded. First, the instruction A is decoded, the value of the field VR2 which is the vector register number of the operand (2) is read out to the signal line 2b and set in the register 3b. Similarly, the field VR which is the vector register number of the operand (3)
The value of 3 is read out to the signal line 2a and set in the register 3a. Similarly, the value of the vector register number VR1 of the operand (1) which is the operation result is read out to the signal line 2c and set in the register 3c. In parallel with this, the register 103 a indicating the read element address of the vector registers 105 and 106, and the buffer device 50.
Initialize '0' of the register 303a indicating the write element address of 0. As a result, the vector registers 105 and 106 and the vector mask register 2
The 0th elements A (0), B (0), and M (0) are read out from 09. A (0), B (0) of the read element
Is the vector data A section 500 of the buffer device 500.
a, B part 500b. In addition, the register 103
The values of a and the register 3c are connected to the vector data ID section 500c of the buffer device 500. That is, the contents stored in the vector data ID portion 500c is V
It is a valid number stored in R1 and the register 103a.

Element M in vector mask register 209
(0) is the buffer device 500 via the signal line 209a.
Connected to. Here, the value of the signal line 209a is "1".
At this time, it works as a storage instruction to the buffer device 500. The signal line 209a also operates as an update permission signal for the register 303a. After this, the vector register 10
Register 10 indicating the read element address of 5,106
3a is incremented by 1 by the incrementer 103, and the next elements VR3 (1), VR2 (1), and VMR (1) are read. After that, by repeatedly executing the above-mentioned operation, only the elements of the vector data for which the calculation is to be executed are sequentially stored in the buffer device 500. The instruction control unit 1
By the operation of the end detection circuit 5, it is known that the last vector element address is detected, and the processing is ended. Since the incrementer 303 sequentially stores only the element and the element number of the vector data whose element value in the vector mask register 209 instructs the execution of the operation in the buffer device 500, the value of the signal line 209a is "1". The address value of the register 309a only when
When the value is "0", the incrementer 303 increments it by "+1" to sequentially increment the address value of the next element. As described above, in the instruction precedent stage, the process of sequentially storing only the elements of the vector data to be operated on from the instruction decoding operation is executed in the buffer device 500. Next, the instruction control unit 1 sequentially advances the instructions for which the preceding stage has been completed to the instruction execution stage. In the instruction execution stage, first, the register 403a indicating the read element address of the buffer device 500 is initialized to "0".

By initializing the register 403a, the vector data A section 500a and the vector data B section 500b, which are constituent elements in the buffer device 500, can be obtained.
More operation operand data A (0), B
(0), the storage address ADR (0) of the calculation result in the vector register is read from the vector data ID section 500c. The data A (0) and the data B (0) are supplied to the vector calculator 113. The calculation result by the calculator 113 is the vector register 11 indicated by ADR (0).
Stored in 5. After that, the register 403a is incremented by "+1" by the incrementer 403. After that, by repeatedly executing the above-described operation, it is possible to execute the operation only for the element for which the vector mask data instructs the operation. When the end detection circuit 6 detects the last vector element address, the instruction control unit 1 ends the instruction execution process. In parallel with the instruction execution stage of this instruction A,
By starting the preceding stage of the instruction B, in the instruction execution stage, it becomes possible to successively execute only the elements for which the vector mask data instructs the operation.

As the instruction register group stored in the memory 2, for example, the database of the resident register in Tokyo is directly stored as the operands VR2, VR3 and VR1. Here, the name, sex, occupation, whether or not a householder is the vector data, and the arithmetic unit is an inequality, addition, subtraction, or the like. On the other hand, as a mask bit stored in the vector mask register 209, in order to create a database of only women among residents, an instruction for creating a vector mask bit is first issued and the original data is created. -It is created by designating the data portion in the database as a female, comparing the comparison results with a vector mask, and storing "1" in the coincident portion. By making the vector mask register 209 thus created and the data base of the resident register into a vector instruction register group, only the vector data in which the mask bit of the vector mask register 209 corresponds to "1" is calculated. Therefore, it is possible to quickly create a database of resident register for women only.

[0014]

As described above, according to the present invention,
In a data processing device that performs vector operations, no matter how the values of the vector mask are arranged, only valid elements are operated without performing invalid operations, so vector operations are executed at high speed. be able to.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a vector instruction control device showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional vector instruction control device.

FIG. 3 is a diagram for explaining the effect of the vector instruction control method of the present invention.

[Explanation of symbols]

1 Instruction Control Unit 2 Instruction Register Group 3a, 3b, 3c, 101, 103a, 403a Registers 110-112, 216-218 Delay Latch 103, 303, 403 Incrementer 500 Buffer Device 500a, 500b, 500c Components of Buffer Device 105 , 106, 115 Vector register 113 Vector calculator 5, 6 End detection circuit 209 Vector mask register

Claims (4)

[Claims] 1. A vector instruction control device for sequentially reading vector data and vector mask data consisting of a plurality of elements and performing an operation of the vector data according to an element value of the vector mask data, Prior to the execution stage, an element of the operand vector data designated by the instruction and a buffer device for storing the number of the element, and an element value of the vector mask data indicate execution of the operation. Vector instruction control characterized by having a first address register and a first address incrementer for designating an address for sequentially storing only an element of operand vector data and the number of the element in the buffer device. apparatus. 2. The vector instruction control device according to claim 1, further comprising a second address register and a second incrementer for reading the operand vector data stored in the buffer device, and reading the operand vector data. And a vector instruction control device for executing an operation using the operand vector data. 3. The vector instruction control device according to claim 1, wherein a result obtained by executing an operation using the operand vector data read from the buffer device is an element number read from the buffer device. A vector instruction controller characterized by writing to a vector register according to the above. 4. A vector instruction control method for sequentially reading vector data composed of a plurality of elements and vector mask data, and calculating the vector data according to the element value of the vector mask data, A period during which an instruction execution stage is executed in which the operand vector data and the element number are sequentially read from the buffer device for the instruction, the operation is executed, and the result of the operation is stored in the result register according to the element number. For the next instruction, among the operand vector data designated by the instruction, the element value of the operand vector data whose element value of the vector mask data instructs execution of the operation and the element of the element A vector instruction control method characterized in that an instruction preceding stage for storing only numbers in a buffer device is executed in parallel.