JPH0583007B2 - - Google Patents

Description

[Detailed description of the invention] (Industrial application field) TECHNICAL FIELD The present invention relates to a double integral type AD converter.

(Prior art) In electronic scales that require high precision, a double integral type A-D converter is used as a converter (hereinafter referred to as an A-D converter) that converts an analog signal into a digital signal. .

As a device in which the unknown input integration time of such an A-D converter can be freely changed by a computer, a configuration as shown in FIG. 10 has been proposed. In the figure, A is a buffer, B is an integrator, C is a comparator, D is a zero-cross detector, E is a flip-flop, F is a counter, and G is a CPU.

Next, the operation of this circuit will be explained using the timing chart shown in FIG.

When the start pulse to start integration is output from the CPU at time _t1 , the counter F is cleared by the output signal inverted by the inverter H, and the switch _S1 is turned on to convert the unknown input voltage V _IN to the buffer A.
input to integrator B via , and start integrating the unknown input voltage [Waveform B]. At the same time, flip-flop E is set and a pulse is output from the Q terminal [waveform C]. Furthermore, this flip-flop E
is configured to be set and reset at the fall of the input pulse from H to L.

The unknown input voltage integration time ends at time t ₂
The start pulse from the CPU turns off [waveform A], turns off switch _S1 , turns on switch _S2 ,
A reference voltage Vref is input to an integrator B via a buffer A. At this time, start counting. Integrator B provides an output in reference voltage inverse integration mode.

By the way, a double-integration type A-D converter is provided with a correction circuit in order to correct the offset of the system including the integrator, but this correction circuit uses the output of the comparator connected to the output side of the integrator Since the configuration is such that negative feedback is provided to the integrator at the previous stage, when the count is stopped at time _t3 and the integrator offset correction mode is entered, the output of the comparator will be in the "H" and "L" states. A repeating oscillation state occurs [waveform E].

When such an oscillation condition occurs, the comparator output cannot be directly input to the flip-flop that controls integration mode switching (the reset and set terminals of the flip-flop may become active at the same time); In the output stage,
A zero-cross detector D consisting of a multivibrator, logic circuit, etc. was provided to output a single pulse at time _t3 , which was input to a flip-flop for controlling mode switching of the integrator [Waveform T].

As a result, flip-flop E is reset, and the output pulse from the Q terminal is input to the CPU as a zero-cross signal [waveform T].

(Problems with the prior art) As described above, the conventional double-integration type A-D converter requires a zero-cross detector with a complicated circuit configuration, which increases the number of parts and increases the cost. .

In addition, in the offset mode, the input level of the integrator is not equivalent to the offset voltage of the preceding stage buffer, so the capacitor Co connected to the other input side of the integrator that charges the offset correction voltage has no buffer. There was a problem in that the offset voltage of the entire system consisting of the oscillator, integrator, and comparator was not charged accurately.

(Object of the invention) The object of the present invention is to solve the problems of the prior art,
To provide a double integration type A-D converter with improved characteristics by having a zero cross detector with a simple circuit configuration and charging the offset voltage of the entire system to a capacitor connected to the input side of the integrator. It is something to do.

(Summary of the Invention) The double integration type AD converter of the present invention is configured as follows. That is, an integrator is connected to the output terminal of the integrator, and the output voltage of the integrator is determined using a predetermined value as a threshold. The output stage includes a comparator with an output transistor whose collector and emitter can each be connected to an external power supply, and an offset correction device in which the comparator output is negatively fed back between the collector of the output transistor and the other terminal of the integrator. Switch turned on in mode and resistor R
0 series circuit and a capacitor C0 connected between the other terminal of the integrator and ground, and the output pulse of the comparator to switch the operation mode of the integrator from integration mode to offset correction mode. It is equipped with a flip-flop and a counter for measuring the inverse integration time, and resets the flip-flop by inverting the output of the comparator at the zero-cross point of the integrator output in the inverse integration mode, and stops the operation of the counter by the reset signal. , the switch is turned on to shift the integrator to the offset correction mode, and the charge voltage of the capacitor of the offset correction circuit is smoothed during the operation of charging the entire offset voltage from the integrator to the comparator to the capacitor C0. As an integrating circuit for
and a capacitor Cc (where Co>>Cc) connected between the collector of the output transistor and the input terminal of the integrator to which the capacitor C0 is connected.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an example in which the double integration type AD converter of the present invention is used in an electronic balance. In this example, the weight signal detected by the load cell J is outputted from the low-pass filter L via the pre-stage amplifier K, and is used as the unknown input voltage of the double-integration type AD converter.

The double integral type A-D converter of the present invention differs from the conventional example shown in FIG. 10 in the following points.

(1) The comparator uses a predetermined value as a threshold to determine the magnitude of the output value of integrator B, and on the output side, a desired external voltage can be connected to the collector and emitter, respectively. A comparator with an open collector connected output transistor is used, and when the voltage at the non-inverter terminal of the comparator is higher than the threshold (ground voltage), the output voltage is +V ₁ , and when it is lower than the threshold, the output voltage is +V 1. becomes −V ₂ .

(2) The offset correction circuit includes a resistor Rc connected between one power supply + _V1 and the collector of the output transistor, and a capacitor C between the collector and the integrator.
Integrating circuit (low-pass filter) consisting of a capacitor Cc connected between the input terminals connected to 0
In addition, the constants of Rc and Cc are set so that the comparator outputs a pulse in the offset correction mode.

(3) In offset correction mode, the input level of the integrator is set to the offset voltage value of the buffer in the previous stage or the ground level, and the offset voltage of the entire system from the buffer in the previous stage to the comparator is , the offset correction voltage connected to the input side of the integrator is charged to a capacitor Co. In addition,
The capacitance of the capacitor is set as Co≫Cc.

Next, the operation of the double integral type A-D converter according to the present invention in the offset correction mode will be explained with reference to the timing chart shown in FIG. In addition, the 10th
Descriptions of operations that are the same as those of the conventional example shown in FIGS. 1 and 11 will be omitted.

When the unknown input voltage input to integrator B is of (+) polarity, the output of the comparator in integration mode is held at + _V1 . Then, at the zero-crossing point of the integrator output, the comparator is inverted and the output becomes approximately _-V2 , which causes the flip-flop E
is reset at the falling edge of the pulse H, a pulse is output from the Q terminal, the operation of the counter F is stopped, the switch _S3 of the offset correction circuit is closed, and the mode shifts to the offset correction mode. When shifting to the offset correction mode, a RoCo integrating circuit is formed where the output of the comparator C is approximately _-V2 , so the potential on the non-inverter terminal side of the integrator begins to gradually drop. After that, when that potential drops even slightly from the potential at the inverter terminal of the integrator, that is, the potential equivalent to the offset voltage of buffer A, the output of integrator B gradually decreases, and as a result, the operational amplifier of comparator C is inverted. The output stage transistor Tr is turned off. Then the current is +V ₁
flows from the side to RoCo via the RcCc circuit. However, since RoCO≫RcCc is set, the potential at the non-inverter terminal of the integrator increases only gradually. Then, when that potential exceeds the potential of the inverter terminal of the integrator even slightly, the integrator output gradually increases again, the transistor Tr in the output stage of the comparator is immediately turned on, and the output of the comparator becomes approximately -V ₂ [Waveform E].

After that, while repeating this operation, the comparator output becomes almost + during the offset correction mode.
It is held at a level between V ₁ and −V ₂ , and the capacitor
The voltage between the terminals of Co is maintained at a value equivalent to the offset voltage of the entire system from buffer A to comparator C.

FIG. 3 is a circuit diagram showing the switching operation of the above embodiment. During the unknown input voltage integration period, switches S ₁ and S ₅ are turned on and switches S ₂ , S ₃ , S ₄ and S ₆ are turned off, as shown in FIG. 3a. Next, during the reference voltage inverse integration period, as shown in Figure 3b, switch _S1 is turned off and switch _S2 is turned on, and the remaining switches _S3 to _S6 are set in the same manner as in Figure 3a. I'll keep it.
During the offset voltage correction period, as shown in Figure 3c, switches S ₁ and S ₂ are turned off, switch S ₄ is turned on to maintain the buffer at ground level, switch S ₅ is turned off, and switch S ₆ is turned on. On, turn on _S3 and activate the offset correction circuit.

FIG. 4 shows the circuit configuration when the unknown input voltage is set to (-) polarity.

In this embodiment, since the output of the comparator in the integration mode is held at the "L" level, an inverter _H3 is added to the output stage of the comparator so that the operating level for the reset terminal of flip-flop E is adjusted to the level of the first embodiment. I'm trying to make it equal to the example.
Note that the switches S ₁ to _{S 6} are shown as electronic switches.

The second embodiment operates almost the same as the first embodiment, but in the time chart of FIG.
The waveforms of parts E and F are different as shown in Figure 5.

The operation of the second embodiment will be explained below.

When the unknown input voltage has (-) polarity, the comparator output in the integral mode is approximately at the _-V2 level. When the inverse integration using the reference voltage is completed, the operational amplifier forming the comparator is inverted, and the transistor Tr in its output stage is turned off.
Then, current flows from the + _V1 side through RcCcCo, and the output level of the comparator gradually increases. Then, when the output exceeds a predetermined value, the output of inverter H is inverted from the "H" level to the "L" level, and at the rising edge, flip-flop E is reset, the counter is stopped, and the offset correction mode is entered. Transition.

When switching to offset correction mode, the new
Since a RoCo integrator circuit is formed, the potential at the non-inverter terminal of the integrator gradually increases due to the output of the comparator held at the "H" level. Then, when that potential exceeds the potential of the inverter terminal of the integrator even slightly, the integrator output gradually increases, which causes the comparator to also invert, and its output becomes approximately -
Becomes _V2 level.

After that, the same operation as in the first embodiment is repeated, and the comparator output is held at approximately the intermediate level between + _V1 and _-V2 , and the voltage across the terminals of the capacitor Co is adjusted to the offset of the entire system. held at voltage.

6 to 9 are circuit diagrams of different embodiments of the present invention, and the connection on the input side of the integrator is changed, but the polarity of the comparator and the configuration of the offset correction circuit are as shown in FIG. 4. This is similar to the second embodiment.

Note that in FIGS. 3, 4, 6 to 9, the comparator is simply represented by the symbol of an ordinary amplifier, but in reality, the symbol shown in FIG. As shown surrounded by the dotted line, an operational amplifier and an open collector output transistor are housed at its output terminal in the form of an IC.

(Effects of the Invention) As described above, according to the present invention, a complicated zero-crossing detector is no longer necessary, a comparator having an open-collector connected transistor is connected to the output stage of the integrator, and an integrating circuit (low-pass Since the offset is corrected by simply adding a filter, the circuit configuration is simplified, the number of parts can be reduced, and costs can be reduced.

In addition, in the offset mode, the input level of the integrator is set to the offset voltage value of the buffers before and after the integrator, or the ground level, and the offset voltage of the entire system from the buffers before and after the integrator to the comparator is controlled by the auto-zero capacitor. Since Co is charged, offset correction can be performed accurately.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a double integral A-D converter of the present invention, FIG. 2 is a timing chart, and FIG. 3 is a main circuit diagram explaining the operation of the first embodiment of the present invention. FIG. 4 is a circuit diagram of a main part explaining the operation of the second embodiment, FIG. 5 is a timing chart of the second embodiment, and FIGS. 6 to 9 are main parts of other embodiments of the present invention. FIG. 10 is a circuit diagram of a conventional example, and FIG. 11 is a timing chart of a conventional example. A... Buffer, B... Integrator, C... Comparator, D...
Zero cross detector, E...Flip-flop, F...
Counter, G...CPU, H, H, H...Inverter,
I...And gate, J...Load cell, K...Pre-stage amplifier, L...Low-pass filter.

Claims (1)

[Claims] 1. An integrator into which either the unknown input voltage or the reference voltage signal is input to one terminal, and the output terminal of the integrator is connected to determine the output voltage of the integrator using a predetermined value as a threshold. The stage includes a comparator having an output transistor whose collector and emitter can each be connected to an external power supply, and an offset correction mode in which the comparator output is negatively fed back between the collector of the output transistor and the other terminal of the integrator. The operating mode of the integrator is changed to integration mode by using an offset correction circuit consisting of a series circuit of resistor R0, a capacitor C0 connected between the other terminal of the integrator and ground, and the output pulse of the comparator. The flip-flop is equipped with a flip-flop that switches from zero to an offset correction mode, and a counter that measures the inverse integration time.The flip-flop is reset by the inversion of the output of the comparator at the zero-cross point of the integrator output in the inverse integration mode, and the counter is activated by the reset signal. At the same time, the switch is turned on to shift the integrator to the offset correction mode, and the offset voltage of the entire offset voltage from the integrator to the comparator is charged to the capacitor C0. As an integrating circuit for smoothing the charge voltage of, a resistor Rc connected between the external power supply and the collector of the output transistor of the comparator, and an input connected to the collector of the output transistor and the capacitor C0 of the integrator. A double integration type A-D converter, characterized in that a capacitor Cc (where Co≫Cc) is connected between the terminals.