JPH05341995A - Instruction control method in processor and processor - Google Patents

Abstract

PURPOSE:To shorten the processing time of instruction sequence by executing a preceding plural machine cycle instruction and succeeding one machine cycle instruction simultaneously without completing the succeeding one machine cycle instruction prior to the preceding plural machine cycle instruction in an instruction control method for a processor which executes an instruction by applying pipeline processing. CONSTITUTION:When the instruction 3 (preceding four machine cycle instruction) and the instruction 4 (succeeding one machine cycle instruction) are executed simultaneously, the arithmetic operation of the instruction 4 is executed at an OE stage, then, the output latch of the OE stage is set in a negate state, and an OW stage for the instruction 4 is set in a waiting state by holding a computed result at the OE stage, and when a machine cycle where the instruction 4 can be completed matching to the completion of the instruction 3 arrives, a held computed result is written.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction control method in a processor that executes instructions by so-called pipeline processing, and a processor that executes instructions by pipeline processing.

[0002]

2. Description of the Related Art In recent years, as shown in the flow of instruction execution in FIG. 11, a processor employing a so-called superscalar system has been put into practical use in which two instructions are simultaneously executed by pipeline processing to improve performance. It has been converted to.

In the figure, DC, AC, Mi, OE, and OW represent pipeline stages, DC is a stage for decoding instructions, AC is a stage for calculating addresses, and Mi is a microprogram. In this example, instruction 1 and instruction 2, instruction 3 and instruction 4, instruction 5 and instruction 5 6 and 6 are being executed simultaneously.

[0004]

A conventional processor adopting such a superscalar system basically assumes that each instruction is executed in one machine cycle.
For example, as shown in FIG. 12, in one machine cycle instruction 1, 2, 4, 5, 6, a multiple machine cycle instruction such as a multiplication instruction or a division instruction, for example, an instruction that is a four machine cycle instruction. If 3 is included,
Instructions 1 and 2 which are 1 machine cycle instructions are executed simultaneously, but instructions 3 and 1 which are 4 machine cycle instructions
The instruction 3 which is a machine cycle instruction is not executed at the same time, the instruction 3 is executed independently, and the instructions 4 and 5 which are one machine cycle instruction are executed at the same time.

Incidentally, in FIG. 12, Mi ₁ , Mi ₂ and M
i ₃ and Mi ₄ are the first, second, _third , and _fourth , respectively.
The second Mi stage, OE ₁ , OE ₂ , OE ₃ , OE ₄ ,
The 1st, 2nd, 3rd and 4th OE stages, OW ₁ , OW ₂ , OW ₃ and OW ₄ respectively mean the 1st, 2nd, 3rd and 4th OW stages. There is.

DCc means that the decoding result at the DC stage has been canceled, and ACc means that the address calculation result at the AC stage has been canceled.

As described above, in the conventional processor which employs the superscalar system, two machine cycle instructions can be executed simultaneously, but a plurality of machine cycle instructions executed in a plurality of preceding machine cycles and a succeeding machine cycle instruction. However, there is a problem in that the performance cannot be improved by that much because it cannot be executed simultaneously with the one machine cycle instruction.

When the preceding plural machine cycle instructions and the succeeding one machine cycle instruction are executed simultaneously, it is avoided that the succeeding one machine cycle instruction precedes the preceding plural machine cycle instruction. There must be.

In view of the above points, the present invention allows a preceding multiple machine cycle instruction and a succeeding one machine cycle instruction to be executed at the same time without completing the preceding one machine cycle instruction earlier than the preceding multiple machine cycle instruction. An object of the present invention is to provide an instruction control method and a processor that can be executed and shorten the processing time of an instruction sequence.

[0010]

According to the instruction control method of the present invention, a preceding plural machine cycle instruction and a succeeding one machine cycle instruction are respectively included in a first instruction execution system and a second instruction execution system.
When the instruction execution system of the second instruction execution system is simultaneously executed, the output latch of the OE stage of the second instruction execution system is negated after the operation of the subsequent one machine cycle instruction is executed in the operation stage of the second instruction execution system. State and hold the operation result for the subsequent one machine cycle instruction
When the machine cycle in which the OW stage of the instruction execution system is placed in a wait state (waiting state) and then the succeeding one machine cycle instruction can be completed in synchronization with the completion of the preceding plurality of machine cycle instructions, The execution of instructions is controlled so that the wait state of the OW stage of the instruction execution system is released and the held operation result is written.

A processor according to the present invention is a processor capable of executing the instruction control method according to the present invention, wherein at least a first instruction execution system and a second instruction execution system are provided and a plurality of preceding machines are provided. When the cycle instruction and the subsequent 1-machine cycle instruction are simultaneously executed in the first instruction execution system and the second instruction execution system, respectively, the 1-machine cycle instruction subsequent to the OE stage of the second instruction execution system After the operation is executed, the output latch of the OE stage of the second instruction execution system is negated,
The operation result of the succeeding one machine cycle instruction is held and the OW stage of the second instruction execution system is set to the wait state, and then the succeeding one machine cycle instruction is completed at the completion of the preceding plural machine cycle instructions. Instruction control for controlling the execution of an instruction so that the wait state of the OW stage of the second instruction execution system is released and the held operation result is written when the machine cycle becomes possible. It is configured by providing means.

[0012]

In the instruction control method according to the present invention, the O of the second instruction execution system for executing the succeeding one machine cycle instruction to be executed simultaneously with the preceding plural machine cycle instructions.
By setting the wait state in the W stage, the preceding one machine cycle instruction and the following one machine cycle instruction can be executed simultaneously without the following one machine cycle instruction being completed before the preceding plurality of machine cycle instructions. The instruction control method according to the present invention can be executed by providing the above-mentioned instruction control means.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 to 10, two instructions are executed simultaneously in one embodiment of a processor according to the present invention, including the contents of one embodiment of an instruction control method according to the present invention. A case will be described as an example.

FIG. 1 is a block diagram showing a main part of an embodiment of a processor according to the present invention.
Reference numeral 2 is an instruction control unit that controls instruction execution, 3 is an instruction execution unit that executes instructions, 4 is a memory control unit that controls access to memory, etc., 5 is control of transmission and reception of information to and from the outside It is a bus control unit.

In the instruction control unit 2, 6 is an instruction queue (instruction buffer) for storing the instructions fetched from the memory, and 7 and 8 are instruction decoders for decoding the instructions stored in the instruction queue 6. is there.

Reference numerals 9 and 10 denote microprogram units for storing microprograms for decomposing and executing the decoded instructions, and 11 denotes a pipeline control unit for controlling pipeline processing.

In the instruction execution section 3, 12 is an address calculation section for calculating an operand address based on the contents of the address section of the instruction, and 13 is a necessary operation according to the microprogram output from the microprogram units 9 and 10. The calculation unit 14 performs the address calculation unit 12
And a register file used as a general-purpose register in the arithmetic unit 13.

In the memory control unit 4, 15 is an instruction access control unit for controlling access to an instruction stored in the memory, and 16 is an operand for controlling access to an operand storing data necessary for executing the instruction. It is an access control unit.

In the bus control unit 5, 17 is an address control unit for controlling the output of an address to the address bus, 18 is a bus monitoring control unit for monitoring the bus and controlling its use, and 19 is for sending and receiving data. This is a data transmission / reception unit.

FIG. 2 is a diagram showing the instruction control unit 2 and the instruction execution unit 3 in more detail. In the instruction control unit 2,
Reference numerals 20 and 21 denote tag storage units that hold instruction read and write destinations for general-purpose registers over pipeline stages.

Further, 9A and 10A are microprogram storage units for storing microprograms, and 9B and 10B are next address storage units for holding next addresses.

Further, among the instructions to be simultaneously executed, 24 is
This is a first pipeline control unit that performs pipeline control on an instruction execution system that executes a preceding instruction, and the instruction decoder 7, the micro program unit 9, and the like are included in the instruction execution system that executes a preceding instruction.

Further, 25 is an instruction to be executed simultaneously.
This is a second pipeline control unit that performs pipeline control on an instruction execution system that executes a subsequent instruction, and the instruction decoder 8, the microprogram unit 10, and the like are included in the instruction execution system that executes the subsequent instruction.

In the instruction executing section 3, 26, 27
Is a constant generation part generated by cutting out a constant (displacement) specified in the address part of the instruction, 28,
Reference numeral 29 is an address adder (AU) used for calculating an operand address.

Further, reference numerals 30 and 31 are immediate generation sections which are generated by cutting out immediates (immediate values) when the address system in the instruction is the immediate address system, and 32 and 33 are ALUs which perform operations necessary for executing the instruction.
(Arithmetic logical operation unit), 34 and 35 are SFT (shifter).

FIG. 3 shows the format of the instruction used in this embodiment. In the figure, OP is an instruction code part, S is an operand size specification part, R is a register specification part, # 1 is an immediate value, disp is a displacement part, n is a positive integer including 0, and 16 × n indicates that the expansion part is variable in 16-bit units.

Therefore, in this embodiment, the instruction decoder 7 is constructed as shown in FIG. 4, and the instruction decoder 8 is also the same. In the figure, 36 and 37 are instruction registers, and 38 to 47 are latches.

Reference numeral 48 is a first instruction decoder which decodes the instruction code at the beginning of the instruction, and 49 is an instruction decoder such as a two-operand instruction or an extended operand instruction (see FIG. 3).
This is a second instruction decoder that decodes the second instruction code when it includes this instruction code.

Reference numeral 50 is a selector, and the selector 50 outputs a micro address, a tag, and a multi-cycle instruction signal. The micro address is supplied to the micro program unit 9, the tag is stored in the tag storage unit 20, and the multi-cycle instruction signal is supplied to the first pipeline control unit 24.

Further, 51 is an addressing decoder for decoding addressing information contained in the instruction, 5
Reference numeral 2 designates a next stage transition request decoder which judges one instruction into individual decodable lengths and successively decodes it.
Is an additional mode decoder for decoding the additional mode.

Further, 54 is an addressing decoder 51.
And the latch 3 based on the output of the additional mode decoder 53.
8 to 47, a selector 50, a next stage transition request decoder 52, an additional mode decoder 53, and the like.

Further, FIG. 5 shows the second pipeline controller 25.
55 is a diagram showing a DC stage control unit 5
6 is an AC stage control unit, 57 is a Mi stage control unit,
Reference numeral 58 is an OE stage control unit, 59 is an OW stage control unit, 60 to 69 are OR circuits, and 70 to 75 are AND circuits.

The DCW factor, ACW factor, MiW factor, and OEW factor are the weight factor for the DC stage, the weight factor for the AC stage, and the weight factor for the AC stage, respectively.
It means the weight factor for the Mi stage and the weight factor for the OE stage.

The DCR factor, ACR factor, MiR factor, and OER factor are the retry (re-execution) factor for the DC stage, the retry factor for the AC stage, the retry factor for the Mi stage, and the OE factor, respectively.
It means the retry factor for the stage.

In addition, DCLE, ACLE, MiLE, O
ELE is a signal for controlling the output latch of the DC stage, a signal for controlling the output latch of the AC stage,
A signal that controls the output latch of the Mi stage and a signal that controls the output latch of the OE stage.

In addition, DCRO, ACRO, MiRO, O
ERO is a signal indicating whether the DC stage is a retry cycle, a signal indicating whether the AC stage is a retry cycle, a signal indicating whether the Mi stage is a retry cycle, and an OE stage, respectively. This is a signal indicating whether or not it is a retry cycle.

Reference numeral 76 is the first pipeline controller 24.
A write stage standby signal (hereinafter referred to as OWW
A first generation pipeline control unit 24 is provided with an OWWAIT signal generation circuit 76 and an OW stage execution instruction signal (hereinafter referred to as OWGO signal) provided in an OW stage control unit described later. The second pipeline control unit 25 has the same configuration except that the configuration of the generation circuit is different.

Here, the DC stage control unit 55, the AC stage control unit 56, the Mi stage control unit 57, the OE stage control unit 58, and the OW stage control unit 59 are, for example,
It is configured as shown in FIG.

In the figure, 77 to 82 are latches, 83 to 85 are OR circuits, 86 and 87 are AND circuits, 88 is an AND circuit having an L active input terminal, 89 is an inverter, and φ ₀ and φ _{1 are also provided.} , Φ ₂ are three of the four-phase clocks, and Vi and VO are valid signals indicating whether the stage is valid or not.

The OWWAIT signal generating circuit 76 provided in the first pipeline controller 24 is constructed as shown in FIG. In the figure, 90 to 94 are D flip-flops, 95 and 96 are AND circuits, 97 is an OR circuit, and 98.
Is an inverter.

The OE of the second pipeline controller 25
In the stage control unit 58, for example, an OWGO signal generation circuit as shown in FIG. 8 is provided. In the figure, 99, 10
0 is a latch, 101 is an AND circuit, 102 and 103 are L
An AND circuit 104 having an active input terminal is an OR circuit.

FIG. 9 is a diagram for explaining the operation of this embodiment. Instructions 1, 2, 4, which are one machine cycle instruction.
5 and 6 and the instruction 3 which is a four machine cycle instruction are shown in the flow processed by this embodiment.

In this embodiment, the instructions 1, 3, 5 are
Instructions 2, 4, 6, which are executed by an instruction execution system controlled by the first pipeline control unit 24, that is, an instruction execution system that executes a preceding instruction among instructions to be executed simultaneously
Is executed by the instruction execution system controlled by the second pipeline control unit 25, that is, the instruction execution system that executes the subsequent instruction among the instructions to be executed simultaneously.

Here, as shown in FIG. 9, the instruction 1 and the instruction 2 are DC → AC → Mi → in the same manner as in the conventional case.
Processing is performed simultaneously by executing each stage in the order of OE → OW (see FIG. 12).

As shown in FIG. 9, the instruction 3 is DC → AC → Mi ₁ → Mi ₂ , OE, as in the conventional case.
₁ → Mi ₃ , OE ₂ , OW ₁ → Mi ₄ , OE ₃ , OW ₂ → O
The stages are executed and processed in the order of E ₄ , OW ₃ → OW ₄ (see FIG. 12).

FIG. 10 is a diagram showing in more detail the flow of pipeline processing for instructions 3 and 4, for instruction 3 DCout (output from decoder 7), Mi address signal (microprogram). Address for accessing unit 9), Miout (output from microprogram unit 9), first OW support signal (O
W ₁ stage instruction signal), Mi end instruction signal (M
signal indicating the end of the i stage), a multi-cycle instruction signal, and an OWWAIT signal.

As for the instruction 4, the OELE signal (signal for controlling the output latch of the OE stage), OEV
O signal (signal indicating whether the OE stage is valid), OWVi signal (signal indicating whether to operate the OW stage), OWVO signal (signal indicating whether the OW stage is valid) , OWGO signals. Note that 105 is a general-purpose register.

Here, in this embodiment, when the instruction 3 is decoded in the DC stage, the instruction 3 is a four-machine cycle instruction, so the multi-cycle instruction signal is asserted, and this is the first pipeline. The signal is supplied to the OWWAIT signal generation circuit 76 of the control unit 24.

For the instruction 3, when the Mi ₁ stage is completed, based on the output thereof, at the OW ₁ stage,
The first OW instruction signal is output and supplied to the OWWAIT signal generation circuit 76.

As a result, the OWWAIT signal generating circuit 76
Outputs an OWWAIT signal, which is supplied to the OE stage controller 58 and the OW stage controller 59 of the second pipeline controller 25 that controls the pipeline processing of the instruction 4.

Here, the instruction 4 executes the DC stage at the same time as the instruction 3, and the respective stages are continuously executed up to the OE stage. As described above, the OWWAIT signal indicates that the second pipeline controller 25 OE stage controller 58
And the OW stage control unit 59, the OE stage control unit 58 of the second pipeline control unit 25.
Sets the OELE signal to the L level, negates the output latch of the OE stage that executed the operation of instruction 4, and
OW about instruction 4 by holding the operation result by 33
Put the stage in a wait state.

After that, for the instruction 3, when the Mi stage becomes the Mi ₄ stage, the Mi end instruction signal is output, and in response to this, the assertion of the multi-cycle instruction signal is canceled at the end of the Mi ₄ stage. , One machine cycle later, the assertion of the OWWAIT signal is also canceled.

In response to this, the OE stage control unit 58 of the second pipeline control unit 25 raises the OELE signal to the H level and releases the negated state of the output latch of the OE stage which has executed the operation for the instruction 4.

Further, the OWG in the OW stage controller 59
The O generation circuit generates an OWGO signal, releases the wait state of the OW stage for the instruction 4, and causes the held operation result of the instruction 4 to be written in the general-purpose register 105.

As described above, in this embodiment, when the preceding four machine cycle instruction, the instruction 3 and the subsequent one machine cycle instruction, the instruction 4, are executed simultaneously, the instruction execution system for executing the instruction 4 is executed. After the operation of the instruction 4 is executed in the OE stage, the output latch of the OE stage is negated, the operation result of the instruction 4 is held and the OW stage of the instruction 4 is put in the wait state, and the completion of the instruction 3 At the time when the machine cycle in which the instruction 4 can be completed in accordance with the above, the wait state of the OW stage for the instruction 4 is released and the operation result held therein is written, Also, the instruction 3 and the instruction 4 can be simultaneously executed without completing the succeeding instruction 4 first.

In the instructions 5 and 6, the DC stage is started in response to the Mi end instruction signal output for the instruction 3, and the stages are simultaneously executed in the order of DC → AC → Mi → OE → OW, and processing is performed. To be done.

[0057]

As described above, according to the instruction control method and the processor of the present invention, the preceding multiple machine cycle instruction can be completed without completing the succeeding one machine cycle instruction earlier than the preceding multiple machine cycle instruction. And the subsequent one machine cycle instruction can be executed at the same time, and the processing time of the instruction sequence can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a diagram showing in more detail an instruction control unit and an instruction execution unit that form an embodiment of the present invention.

FIG. 3 is a diagram showing a format of an instruction used in an embodiment of the present invention.

FIG. 4 is a diagram showing an instruction decoder which constitutes an embodiment of the present invention.

FIG. 5 is a diagram showing a second pipeline control unit that constitutes an embodiment of the present invention.

FIG. 6 is a diagram showing a pipeline stage control unit that constitutes a second pipeline control unit.

FIG. 7 is an OWWAIT provided by the first pipeline control unit.
It is a figure which shows a signal generation circuit.

FIG. 8 is a diagram showing an OWGO signal generation circuit provided in an OW stage control unit of a second pipeline control unit.

FIG. 9 is a diagram for explaining the operation of the embodiment of the present invention.

FIG. 10 is a diagram for explaining the operation of the embodiment of the present invention.

FIG. 11 is a diagram showing a flow when two instructions are simultaneously executed by pipeline processing.

FIG. 12 is a diagram for explaining a problem that a conventional processor adopting a superscalar system has.

[Explanation of symbols]

 1 processor body 2 instruction control unit 3 instruction execution unit 4 memory control unit 5 bus control unit

Claims (3)

[Claims] 1. A method of controlling instructions in a processor for executing instructions by pipeline processing, comprising a first instruction execution system and a second instruction execution for a preceding plural machine cycle instruction and a succeeding one machine cycle instruction, respectively. System, the output latch of the second operation stage of the second instruction execution system is negated after the operation of the subsequent one machine cycle instruction is executed in the second operation stage of the second instruction execution system. State, hold the operation result for the subsequent one machine cycle instruction, and set the operation result writing stage of the second instruction execution system in the standby state, and thereafter, in accordance with the completion of the preceding plurality of machine cycle instructions. When it becomes a machine cycle that can complete the following one machine cycle instruction,
An instruction control method, comprising: controlling the execution of an instruction so that the standby state of the operation result writing stage of the second instruction execution system is released and the held operation result is written. 2. A processor for executing instructions by pipeline processing, which has at least a first instruction execution system and a second instruction execution system, and has a preceding multiple machine cycle instruction and a subsequent one machine cycle. When an instruction and a second instruction execution system are simultaneously executed, respectively, an instruction is executed in the operation stage of the second instruction execution system for the subsequent one machine cycle instruction. After that, the output latch of the operation stage of the second instruction execution system is negated, and the subsequent 1
The operation result write stage of the second instruction execution system is set to a standby state by holding the operation result of the machine cycle, and then the succeeding one machine cycle instruction is completed in synchronization with the completion of the preceding plurality of machine cycle instructions. When it becomes a machine cycle that can be executed, the execution of the instruction is executed so that the waiting state of the operation result writing stage of the second instruction execution system is released and the held operation result is written. A processor having instruction control means for controlling. 3. The instruction control means outputs a multi-cycle instruction signal for instructing multi-cycle output from the first instruction execution system and a first operation result write stage instruction for instructing a first operation result write stage. A predetermined control signal is generated from the signal and a micro program read stage end instruction signal for instructing the end of the micro program read stage, and the predetermined control signal is output to the operation stage of the pipeline control unit of the second instruction execution system. By supplying to the control unit and the operation result writing stage control unit, after the operation for the subsequent one machine cycle instruction is executed in the operation stage of the second instruction execution system, the operation of the second instruction execution system is performed. The output latch of the operation stage is negated, and the operation result for the following one machine cycle instruction is held. Then, the operation result writing stage of the second instruction execution system is placed in a standby state, and then the following one machine cycle instruction can be completed in synchronization with the completion of the preceding plurality of machine cycle instructions. The instruction is controlled so that the standby state of the operation result writing stage of the second instruction execution system is released at this point, and the operation result held therein is written. Processor as described.