JPH05284033A - Sigmadelta modulator - Google Patents

Abstract

PURPOSE:To enable high-accuracy SIGMADELTA modulation over a wider range in comparison with a fixed dither input by inputting dither corresponding to an inputted level. CONSTITUTION:A comparator circuit 4 inputs the output of a second adder circuit 2, defines it as a bit signal after identifying whether it is positive or negative, and delays this outputted bit signal for one clock cycle. Then, a second delay circuit 5 is provided to output the positive or negative full scale value of the input signal corresponding to the bit signal and to impress that value to the second input of a first adder circuit 1, and a dither generating part 7 is provided as a means to apply dither to a third input of the first adder circuit 1. This dither generating part 7 is provided with a sense circuit 6 as a means to fetch the input signal and to generate the dither as the function of the input signal level. It is effective to turn the function to zero near the positive/negative full scale value of the input signal and to turn it to a maximum value near the zero value of the input signal.

Description

Detailed Description of the Invention

[0001]

The present invention is used as a circuit element of an analog / digital conversion circuit or a digital / analog conversion circuit. In particular, it relates to a variable control technique of the amount of dither in a ΣΔ modulator that adds dither to improve the accuracy of an output signal.

[0002]

2. Description of the Related Art A .SIGMA..DELTA. Modulator used as a circuit element of an analog-to-digital conversion circuit or a digital-to-analog conversion circuit has an input level at which pattern noise is generated. A certain amount of dither is input to reduce pattern noise.

FIG. 12 shows a general conventional example. 12
Is a configuration diagram of a conventional example (note that a more detailed description is
Over Sampling Method for A / D and D / A Conversion P4
~ P5J, C Candy and G, C Temes IEEE Press Oversamplin
g DELTA-SIGMA Data Converters Theory Design and Si
mulation).

Next, the relationship between the added dither level and the linearity error will be described with reference to FIGS. 13 to 15 are diagrams showing the relationship among the input level, the linearity error, and the dither level. FIG. 13 shows a state of linearity error when no dither is added, but a peak level of pattern noise is particularly recognized near the input level zero value, and approaches near full scale (hereinafter referred to as FS) at both positive and negative ends. It is recognized that there is a downward trend with

FIG. 14 shows the dither level ± (1/64)
In the example given by FS, the linearity error near the input level zero value is improved. Therefore, it can be inferred that it is more effective to give a larger dither to the linearity error near the input level zero value.

In FIG. 15, the dither level is ± (1/4) F.
This is the result of increasing S. The linearity error near the input level zero value tends to decrease more than that in FIG. 14, but instead the linearity error near ± FS tends to increase.

[0007]

From the above,
The appropriate value of the dither level to be added is not constant with respect to changes in the input level, and is large when the input level is near the zero value.
It can be inferred that it is effective to reduce the size in the vicinity of FS.

The present invention has been made against such a background, and an object thereof is to provide a ΣΔ modulator capable of properly controlling a linearity error even if the input level varies.

[0009]

According to the present invention, there is provided a first addition circuit having an input signal connected to a first input, and a second addition circuit having an output of the first addition circuit connected to a first input. Circuit,
The output of the second adder circuit is connected to the second input of the second adder circuit, and the output of the second adder circuit is used as an input. A comparator circuit for identifying positive / negative as an input and outputting a bit signal, and a bit signal output from the comparator circuit is delayed by one clock cycle, and the positive / negative of the full-scale value of the input signal corresponding to the bit signal ( A second delay circuit for giving + FS or −FS) as an output to the second input of the first adder circuit, and a ΣΔ modulator provided with means for giving dither to the third input of the first adder circuit. In, the means for providing the dither includes means for taking the input signal and generating a dither that is a function of the input signal level.

The function is preferably a function that is zero near the positive and negative full-scale values of the input signal and takes a maximum value near the zero value of the input signal.

[0011]

The sensing section detects the input level and inserts a dither amount preset according to the input level from the dither generation circuit.

The amount of dither to be inserted has a maximum value near the input level zero value and a minimum value (zero) near the positive and negative FS.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of the first embodiment of the present invention.

According to the present invention, a first adder circuit 1 having an input signal connected to a first input, and a second adder circuit 2 having an output of the first adder circuit 1 connected to a first input, The output of the second adder circuit 2 is used as an input, and the output is connected to the second input of the second adder circuit 2 to provide a delay of one clock cycle. A comparator circuit 4 which receives an output as an input and discriminates between positive and negative and outputs a bit signal, and a bit signal output from the comparator circuit 4 is delayed by one clock cycle, and the full scale of the input signal is provided corresponding to the bit signal. A second delay circuit 5 for giving a positive / negative value (+ FS or −FS) to the second input of the first adding circuit 1 as an output, and as a means for applying dither to the third input of the first adding circuit 1. In the ΣΔ modulator equipped with the dither generation unit 7 of The dither generation unit 7 which is a means for obtaining
It is characterized by including a sense circuit 6 as a means for taking in the input signal and generating dither as a function of the level of the input signal.

The function is zero near the positive and negative full-scale values of the input signal and takes a maximum value near the zero value of the input signal.

Next, the operation of the ΣΔ modulator to which dither is added in the first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a block diagram for explaining the operation of the ΣΔ modulator. FIG. 3 is a diagram showing a state of each clock of the ΣΔ modulator. FIG. 4 is a diagram showing a clock and dither.

Since the ΣΔ modulator to which the dither is added in the first embodiment of the present invention is realized by the circuit configuration shown in FIG. 2,
This operation will be described. Note that this circuit operates with the clock shown in FIG. 4, and this clock is called fclk (F clock). The input condition is ± FS = ± 10, input =
6

First, it is assumed that the point B in FIG. 2 when fclk = 0 is "0" as an initial value. C point is "0" for B point
Therefore, the comparison circuit 4 outputs "1" (bit signal). At the point D, since the point C is "1" (bit signal), "-10" (FS value) is output from the second delay circuit 5.

When fclk = 1, "-10" from the second delay circuit 5 and the input "6" are input to the first adder circuit 1 and added, so that the point A is "-". 10 + 6
= -4 ". At the point B, the initial value "0" when fclk = 0 is added to the point "-4" to obtain "0-4 =-".
4 ”. Since the B point is "-4" at the C point, the comparison circuit 4 outputs "0", and thus becomes "0". At point D, the second delay circuit 5 receives "0" from the comparison circuit 4 and is "10".
Is output, it becomes “10”.

When fclk = 2, "10" from the second delay circuit 5 and the input "6" are input to the first addition circuit 1 and added, so that the point A is "10 + 6 =
16 ". Point B is "-4" when fclk = 1
Then, "16" at point A is added and "-4 + 16 = 12"
Becomes Since the B point is "12" at the point C, the comparison circuit 4 outputs "1" and thus becomes "1". The point D becomes "-10" because the second delay circuit 5 receives "1" of the comparison circuit 4 and outputs "-10".

By repeating the above-mentioned operation, FIG.
The states of points A to D up to clk = 7 are shown. Where C
Since the state of the point is output, the output is "1011110.
1 ”. To further stabilize this operation, dither as shown in FIG. 4 is added.

Next, a first embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of the first embodiment of the present invention. The block diagram shown in FIG. 2 is obtained by adding the sense circuit 6 and the dither generation circuit 8 of the first embodiment of the present invention to FIG.
It is a block diagram shown in. The sense circuit 6 receives the input signal and F
An adder 10 for inputting an S value, a subtractor 11 for inputting an input signal and an FS value, the adder 10 and the subtractor 1
This is realized by the multiplexer 12 that inputs 1. This multiplexer 12 outputs either of the two inputs according to the control input.

Next, the relationship between the input level and the dither level will be described with reference to FIGS. 6 to 8 are diagrams showing the relationship between the input level and the dither level. As described above, it is effective to improve the linearity error by increasing the amount of added dither in the vicinity of the input level zero value and decreasing it in the vicinity of ± FS. Since the 12-bit DA converter is used in the first embodiment of the present invention, the input level is ± 20.
There is a setting range of 48 levels, and the dither level is a square wave at a maximum (1/4) FS of 512 levels,
The dither level changes by one level for every four levels of input. FIG. 6 shows the relationship between the input level and the dither level. The dither level is large near the input level zero value and becomes zero near ± 2048, forming a pyramid type. FIG. 7 is a list of this relationship. FIG. 8 shows the result of adding the dither level to the input level as shown in FIGS. 6 and 7 in the first embodiment of the present invention.
It can be seen that the linearity error is kept low over a wide range of input levels.

Next, a second embodiment of the present invention will be described with reference to FIGS. 9 and 10. FIG. 9 is a diagram showing a dither level setting method according to the second embodiment of the present invention. The circuit configuration is the same as that of the first embodiment shown in FIG. In the second embodiment of the present invention, the dither generation circuit 8 includes a decoder. FIG. 10 is a diagram showing the relationship between the input level and the linearity error and dither level according to the second embodiment of the present invention. In the first embodiment of the present invention described above, a pyramid dither level is empirically given as shown in FIG. 6 or 8 from the relationship between the input level and the linearity error. For a bit input, the value of the upper 8 bits or 5 bits is referred to and the dither level is set. A decoder is provided in the dither generation circuit 8 of the block diagram shown in FIG.
The feature is that the upper 8 bits or 5 bits of 12 bits of the input are passed through this decoder to set the dither level. As shown in FIG. 9, the upper 8 bits of the input 12 bits
Set dither level from bit or 5 bits. The dither thus obtained is applied to the input level range "0", "± 409", "± 683", "± 102".
4 ”and“ ± 1230 ”.

The effect of the second embodiment of the present invention is as shown in FIG. 10, and is set by the dither level setting procedure shown in FIG. 9 for the input showing the linearity error distribution as shown in FIG. FIG. 10 (b), which is the dither level
Is given, a good effect of reducing pattern noise as shown in FIG. 10C is obtained.

FIG. 11 is another example showing the relationship between the input level and the linearity error. In this way, various functions can be set in the decoder of the dither generation circuit 8. The relationship between the input level and the applied dither level can be set variously with respect to the input signal as shown in FIG. Also, the dither waveform may be a triangular wave or a ramp wave,
Further, it is also possible to adopt a configuration in which the same effect is produced by changing the cycle instead of the dither level.

[0027]

Since the dither corresponding to the inputted level is inputted, the highly accurate ΣΔ modulation can be performed over a wide range as compared with the fixed dither input.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a ΣΔ modulator according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a state of each unit of each clock of the ΣΔ modulator.

FIG. 4 is a diagram showing a clock and a dither of a ΣΔ modulator.

FIG. 5 is a block diagram of the first embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between an input level and a dither level.

FIG. 7 is a diagram showing a relationship between an input level and a dither level.

FIG. 8 is a diagram showing the results of the first embodiment of the present invention.

FIG. 9 is a diagram showing an input code for inserting dither.

FIG. 10 is a diagram showing a relationship between an input level and a dither level according to the second embodiment of the present invention.

FIG. 11 is a diagram showing a relationship between an input level and a linearity error according to the second embodiment of the present invention.

FIG. 12 is a configuration diagram of a conventional example.

FIG. 13 is a diagram showing a relationship among an input level, a linearity error, and a dither level.

FIG. 14 is a diagram showing a relationship among an input level, a linearity error, and a dither level.

FIG. 15 is a diagram showing a relationship among an input level, a linearity error, and a dither level.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st addition circuit 2 2nd addition circuit 3 1st delay circuit 4 Comparison circuit 5 2nd delay circuit 6 Sense circuit 7 Dither generation part 8 Dither generation circuit 10 Adder 11 Subtractor 12 Multiplexer A- Point D

Claims (2)

[Claims] 1. A first adder circuit having an input signal connected to a first input, a second adder circuit having an output of the first adder circuit connected to a first input, and a second adder circuit. A first delay circuit, which receives the output of the circuit as an input and which is connected to the second input of the second adding circuit to provide a delay of one clock cycle, and an output of the second adding circuit as an input, and distinguishes between positive and negative And a bit signal output from the comparator circuit is delayed by one clock cycle, and the full scale value of the input signal is positive or negative (+ FS or -FS) corresponding to the bit signal. And a second delay circuit for giving to the second input of the first adder circuit as an output, and a ΣΔ modulator provided with means for applying dither to the third input of the first adder circuit, The means for giving the input signal ΣΔ modulator, characterized in that it includes means for generating a is a function of input signal level miso dither. 2. The ΣΔ modulator according to claim 1, wherein the function is zero near a positive / negative full-scale value of the input signal and has a maximum value near a zero value of the input signal.