JPH05275995A - Feedback type pulse width modulating circuit - Google Patents

Abstract

PURPOSE:To provide a feedback type pulse width modulating circuit which obtains the conversion result with the same high precision as conventional without a summing resistance of high precision. CONSTITUTION:A reference voltage generating circuit SV which outputs a square wave reference clock having positively and negatively symmetrical amplitude, a voltage divider RV which divides the voltage of the amplitude of the square wave reference voltage clock into two stages, a switching circuit which switches the output of the voltage divider RV, an integrator IG which integrates the output of the switching circuit, a comparator COP which compares the output of the integrator IG with a reference potential, and a logic circuit LC which drives switching of the switching circuit in accordance with the combination between the output state of the comparator COP and the polarity of the square wave reference voltage clock are provided, and one end (reference potential) of the output of the switching circuit is so connected that the reference potential is equal to an input voltage Ex, and thereby, such control is performed that an average value of the output resulting from addition of the output of the switching circuit and the input voltage in one period is 0, and the output of the comparator COP is taken out as the pulse width modulation signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a feedback pulse width modulation circuit, and more particularly to reduction of high precision addition resistance.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional example of a feedback pulse width modulation circuit. In the figure, Ex is an input voltage, IG is an integrator,
COP is a zero comparator, ± Ec is a square wave clock voltage, ± Es is a positive or negative reference voltage, and the reference voltage ± Es is switched by a switch SW. The input voltage Ex is applied to the resistor R1, the reference voltage ± Es is applied to the resistor R2, and the square wave clock voltage ± Ec is applied to the integrator IG via the resistor R3 and the capacitor C, respectively, and added and integrated. Integrator I
The output eo of G is compared with the zero voltage by the comparator COP, and the switch SW is driven according to the comparison result to switch the reference voltage ± Es. This allows the integrator I
The control operation of this system is performed so that the one-cycle average value of the current flowing into the addition point of G is balanced, and the time axis of the state output of the comparator COP is obtained in proportion to the input voltage Ex. ..

In such a circuit, the input voltage Ex =
0 and Ex> 0, the operation waveforms are shown in (a) and (c) of FIG.
Shown in. (A) is for Ex = 0, and (c) is for Ex> 0. In both figures, ± Es is a reference voltage, Ec is a square wave clock voltage, and eo is an output waveform of the integrator IG. Such a feedback type pulse width modulation circuit is disclosed in, for example, Japanese Patent No. 56.
It is well known in Japanese Patent Application No. 0971, etc. and has excellent linearity and stability, and has been put to practical use in many high-precision measuring instruments such as a digital voltmeter.

Here, in the pulse width modulation circuit shown in FIG. 2, various methods are adopted for generating the positive and negative reference voltages ± Es and switching thereof, but one of the practically used ones is adopted. The schematic circuit is shown in FIG. In the figure, R1
~ R3 is a resistor, IG is an integrator, IV is an inverter, S
Reference numeral 1 is a switch, and (R2 / 2) is a resistor having a resistance value ½ that of the resistor R2. In the circuit, when the switch S1 is turned off, the positive reference voltage + Es is equal to the integrator IG.
In addition, a negative reference voltage -Es is added to the integrator IG when S1 is turned off.

However, in the circuit of FIG. 4, an inverter IV having a gain of -1 is required to generate the negative reference voltage -Es as described above, and the switch S
Since 1 is connected in series to the (R2 / 2) resistor, an error occurs when the on resistance of the switch S1 is at a level that cannot be ignored as compared with (R2 / 2). Furthermore, the circuit also requires a power supply to obtain a square wave clock voltage of ± Ec. In addition, when the entire circuit is to be integrated into an IC by using, for example, C-MOS technology, a high precision resistor R
It is necessary not to use the inverter IV using 4, R5.

In order to solve such a problem, the applicant of the present invention has disclosed in Japanese Patent Application No. 62-178724 (hereinafter referred to as prior invention) that the C-MOS semiconductor is not affected by the on-resistance of the switch. Has applied for a "feedback pulse width modulation circuit" which has a circuit form suitable for realization and has a reference voltage generating means capable of simultaneously generating a square wave clock voltage ± Ec.

FIG. 5 shows a circuit diagram of such a prior invention. In the figure, IG is an integrator, and COP is a zero comparator. The signal source of the input voltage Ex is connected to the integrator IG via the resistor R1, and the output terminal of the integrator IG is connected to the comparator COP. SV is a reference voltage generating circuit for generating a square wave reference voltage clock ± Er having accurate positive and negative symmetrical amplitudes from a single polarity reference voltage Er. In the reference voltage generation circuit SV, Er is a reference voltage source having a single polarity, C is a capacitor, and Sr1 and Sr2 are 2
A changeover switch having two contacts a and b, and S2 is a single throw switch. The switches Sr1, Sr2 and S2 are interlocked with each other. Both ends of the capacitor C are switches Sr.
1 and Sr2 are connected to both ends of the reference voltage source Er via the contact a, and the contact a of the switch Sr1 is connected to the buffer amplifier BA1 via the switch S2.
Is connected to the reference potential point COM.

RV is a voltage dividing resistor, BA2 is a buffer amplifier, R2 is a resistor, and Sa is a changeover switch having contacts a and b. The output terminal of the reference voltage generation circuit SV is connected to the buffer amplifier BA1, and the buffer amplifier BA1
Is connected to the reference potential point COM via the voltage dividing resistor RV.
Is connected to the buffer amplifier BA2 via the contact a of the switch Sa, and the buffer amplifier B2 is connected to the buffer amplifier BA2.
The output terminal of A2 is connected to the input terminal of the integrator IG via the resistor R2. The voltage dividing point of the voltage dividing resistor RV is connected to the contact b of the switch Sa.

LC is a logic circuit. In the logic circuit LC, G1 and G2 are AND gates, G3 is an OR gate,
IV1 is an inverter. The output terminal Q of the comparator COP is connected to one input terminal of the gate G1 and the output terminal Q *.
(* Represents negative logic) is connected to one input terminal of the gate G2. The output terminal of the above-mentioned buffer amplifier BA1 is connected to the other input terminal of the gate G2, and is also connected to the other input terminal of the gate G1 via the inverter IV1. The output terminals of the gates G1 and G2 are connected to the switch Sa via the OR gate G3.

The operation of the pulse width modulation circuit according to the invention of the prior application having such a configuration will be described with reference to the waveform diagrams of FIGS. 3B and 3D. (B) is an operation waveform in the case of Ex = 0 and (D) is Ex> 0. In the following, description will be made mainly using the waveform diagram of (D).

The switch S in the reference voltage generating circuit SV
The duty ratio of r1, Sr2 and S2 is 50%.
It is repeatedly driven by the rectangular wave pulse. This gives T
During the time of / 2 hours (T is a cycle), the reference voltage Er obtains + Er via the switch S2 and the switch Sr.
The capacitor C1 is connected to Er via the contact a of 1 and Sr2 to charge this C. In the next period of T / 2, the switches Sr1 and Sr2 are switched to the contact b to generate −Er by the voltage Er charged in the capacitor C1. In this way, a square wave reference voltage clock ± Er having positive and negative symmetrical amplitudes is obtained. This square wave reference voltage clock becomes a voltage er via the buffer amplifier BA1 and is applied to the contact a of the switch Sa, and is divided into k · er (k is a voltage division ratio) by the voltage dividing resistor RV and is then switched to the switch Sa. Is added to the contact b. Further, this voltage er is applied to the buffer amplifier BA2 and becomes the voltage ea, which is applied to the integrator IG. The switch Sa is connected to the contact b when the output of the OR gate G3 forming the logic circuit LC is "0".

On the other hand, the input voltage Ex shown in (d) is applied to the integrator IG via the resistor R1. The integrator IG adds and integrates the input voltage Ex and the voltage ea obtained via the switch Sa controlled by the logic circuit LC as described below. As a result, the integrator IG outputs the voltage eo having the waveform shown in (b), and this voltage is applied to the comparator COP. The comparator COP compares the integrator output eo with the zero potential, and Q = 1 when eo> 0 and Q * = 1 when eo <0. Here, in (d), (A) at time t1, eo> 0, and the reference voltage generation circuit SV
Assuming that the square wave reference voltage clock generated at 1 is -Er, the output of the AND gate G1 becomes "1", so that the switch Sa is connected to the contact b. As a result, the voltage er becomes -Er and ea becomes -kEr. Since this voltage is applied to the integrator IG via the resistor R2 together with the input voltage Ex, the output of the integrator IG increases in the positive direction. (B) When the square wave reference voltage clock Er is switched from negative to positive at time t2, the outputs of the gates G1 and G2,
Are both "0", the switch Sa is connected to the contact a. As a result, er = + Er, ea = + Er, and the integrator IG adds and integrates + Ex and + Er, and outputs e
o rapidly goes in the negative direction. (C) At time t3, when the integrator output eo crosses 0, the output of the gate G2 becomes "1", and the switch Sa
The contact of is switched to b. As a result, er = + E
r, ea = kEr, and the integrator IG has + Ex and + kE
r and are added and integrated, and the integrator output eo continues to fall gradually. (D) At time t4, the square wave reference voltage clock Er
When is switched from positive to negative, the outputs of the gates G1 and G2 both become "0". As a result, er = -E
r, ea = -Er, which is applied to the integrator IG together with the input voltage Ex.

In this way, the square wave reference voltage clock ± Er, which is obtained from the reference voltage generating circuit SV and has a period of T, is generated.
Is a switch S that can be switched in two stages according to the combination of the polarity of this square wave voltage and the state of the comparator COP.
The step-like reference voltage component e by the switching circuit composed of a
It becomes a and is added and integrated with the input voltage Ex.

Here, as shown in (d), times t1 to t
2 is t1a, time from t2 to t3 is t
1b, time from t3 to t4 is t2a, time from t4
The time until t5 is t2b, and the input resistance R of the integrator IG
When the values of 1 and R2 are equal to each other, the device of FIG. 5 stabilizes the system as in the device of FIG. That is, the following formula is established.

Er * t1b + kEr * t2a-Er * t2b-kEr * t1a + T * Ex = 0 ... (1) Er (t1b-t2b) + kEr (t2a-t1a) =-T * Ex where t1b + t2a = T / 2 t2b + t1a = T / 2, Er {T / 2- (t1a + t1b)}-kEr {T / 2- (t1a + t1b)} = T ・ Ex Also, t1a + t1b = T1 t2a + t2b = T2, Er (T / 2-T1) -kEr (T / 2-T1) = T ・ Ex Er (T / 2-T1) (1-k) = T ・ Ex {Ex / (1-k) Er} = {(T / 2) -T1} / T = {T2- (T / 2)} / T ...
(2) As is apparent from the equation (2), in the pulse width modulation circuit of FIG. 5, the time width of the state output (Q, Q * output) of the comparator COP is obtained in proportion to the input voltage Ex. ..
The status output of this comparator is the pulse width modulation signal PWM
Is taken out as.

[0016]

However, in the circuit of the prior invention of FIG. 5, the input voltage Ex is input to the integrator IG via the input resistor R1, and the stepped reference voltage switched in two steps is input resistance. Since it is configured to input to the integrator IG via R2 and perform addition integration, these input resistances R
Since 1 and R2 are directly related to conversion accuracy, a stable and highly accurate resistance element is required.

The present invention has been made in view of the above problems, and an object thereof is to provide a feedback pulse width capable of obtaining a highly accurate conversion result similar to the conventional one without using a highly accurate addition resistor. It is to provide a modulation circuit.

[0018]

A feedback type pulse width modulation circuit according to the present invention includes a reference voltage generating circuit for outputting a square wave reference voltage clock having positive and negative symmetrical amplitudes, and an amplitude of the square wave reference voltage clock. A voltage divider that divides the voltage in two steps, a switching circuit that switches the output of the voltage divider, an integrator that integrates the output of the switching circuit, a comparator that compares the output of the integrator with a reference potential, and an output of the comparator. A logic circuit for switching and driving the switching circuit according to a combination of a state and a polarity of the square wave reference voltage clock, and connecting one end (reference potential) of the output of the switching circuit to be equal to the input voltage Ex. The output of the switching circuit and the input voltage
It is characterized in that control is performed so that the periodic average value becomes zero, and the output of the comparator is taken out as a pulse width modulation signal.

[0019]

From the switching circuit for switching the output of the voltage divider, the input voltage is added to the square wave reference voltage clock without using the adding resistor and the result is output.

[0020]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a connection diagram of an embodiment of the present invention, and the same parts as those in FIG. 1 is different from FIG. 5 in that the reference voltage generating circuit SV is floated from the reference potential point and the input voltage Ex is added between the reference voltage point and the reference potential point.

That is, the contact b of the switch Sr1, the contact a of the switch Sr2, the end of the voltage dividing resistor RV and the negative side of the reference voltage source Er are connected to the output terminal of the buffer amplifier BA3 to which the input voltage Ex is input. is doing. And
The output of the reference voltage generating circuit SV is added to the buffer amplifier BA2 via the switch Sa, and the buffer amplifier B2
The output terminal of A2 is connected to the input terminal of the integrator IG.

With this structure, the input of the buffer amplifier BA2 is the sum of the input voltage Ex and the ker related to the reference voltage, and the integrator I of the circuit of FIG.
This is the same as adding kEr and Ex in G.
Therefore, the high-precision adding resistance as in the prior invention is not necessary.

The operation except the above-mentioned addition configuration is the same as that of the prior invention of FIG. 5, and the description of those operations will be omitted.

[0024]

According to the present invention described above, it is possible to provide a relatively inexpensive feedback pulse width modulation circuit which can obtain a highly accurate conversion result similar to the conventional one, without using a highly accurate addition resistor.

[Brief description of drawings]

FIG. 1 is a connection diagram of an embodiment of the present invention.

FIG. 2 is a connection diagram of a conventional pulse width modulation circuit.

FIG. 3 is a waveform diagram illustrating the operation of the circuits of FIGS. 2 and 5.

FIG. 4 is a connection diagram of a reference voltage generation circuit portion used in the circuit of FIG.

FIG. 5 is a connection diagram of a feedback pulse width modulation circuit of the invention of the prior application.

[Explanation of symbols]

 SV Reference voltage generation circuit IG Integrator COP Comparator LC Logic circuit

Claims (1)

[Claims] 1. A reference voltage generation circuit that outputs a square wave reference voltage clock having positive and negative symmetrical amplitudes, a voltage divider that divides the amplitude of the square wave reference voltage clock into two stages, and the output of the voltage divider is switched. A switching circuit; an integrator for integrating the output of the switching circuit; a comparator for comparing the output of the integrator with a reference potential; and a comparator for comparing the output state of the comparator and the polarity of the square wave reference voltage clock. A switching circuit, and a logic circuit for driving the switching circuit. By connecting one end (reference potential) of the output of the switching circuit so as to be equal to the input voltage Ex, one of the output of the switching circuit output and the input voltage is added. A feedback type characterized by controlling the period average value to be zero and extracting the output of the comparator as a pulse width modulation signal. Pulse width modulation circuit.