JPH05257122A - Display device - Google Patents

Abstract

PURPOSE:To reduce the power consumption of the device with a display off signal and to prolong the life of liquid crystal by AC constitution by providing a display signal generating means, a power control means, and a display means. CONSTITUTION:While the electric power control means 6 outputs the display off signal for the reduction of the power consumption, the display off signal is sent to a clock generating means 2 or both the display control means 3 and a display signal generating means 5 at the same time. The clock generating means 2 which inputs the display off signal stops supplying a clock signal to the display control means 3 and display signal generating means 5. Further, the display control means 3 and display signal generating means 5 which input the display off signal stop all or some of operations. Further, AC conversion is performed with the display timing signal generated by the display signal generating means 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device in an information processing device including at least an MPU, a display control means, a frame memory, a clock generation means, a display signal generation means, a power management means and a display means.

[0002]

2. Description of the Related Art No conventional display device has a display timing signal generating means inside the display device or a display data signal generating means inside the display device.
Most of the clocks and data did not stop at the time of ff, and most of them changed the clock cycle. In addition, a liquid crystal display device (LCD) equipped with a backlight has a function of turning off the backlight and turning off the display at the same time as represented by the LCD backlight control device of Japanese Patent Application Publication No. 2-216514. There was nothing, and most of them turned off the backlight when there was no key input for a certain period of time.

[0003]

However, the conventional display device has a problem that if the clock and data are stopped, the display device is adversely affected. Also, in the conventional example of the above LCD, the backlight is turned off.
The CD remains on display. For this reason, the conventional display device has a drawback in that data is displayed on a dark screen with the backlight turned off to make it difficult to see the screen and power is wasted because the display is on when it is not used. In addition, in the LCD, the voltage applied to the liquid crystal cell is not changed to AC when the supply of the clock is stopped,
There is a drawback that the life of the liquid crystal cell is extremely shortened.
It is an object of the present invention to solve the above drawbacks, to reduce the power consumption of the device by the display off signal, and to extend the life of the liquid crystal by AC conversion.

[0004]

As shown in FIG. 1, the present invention has means for stopping the timing signal to the display means and means for stopping the data when the power management means outputs the display off signal. The display means internally has a display timing signal input means, a display data signal input means, a display off signal input means, a display timing signal generating means, a display data signal generating means, and a data display. And means.

[0005]

According to the present invention, when the power management means outputs the display off signal in order to reduce the power consumption, the display off signal is sent to the clock generating means at the same time, or the display control means and the display signal generating means. Send to means. Display of
The clock generation means to which the f signal is input stops the supply of the clock signal to the display control means and the display signal generation means.
Further, the display control means and the display signal generating means which have received the display off signal stop all or part of their operations.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the present invention. Reference numeral 1 is a display unit for displaying data.
Reference numeral 2 is a clock generating means for generating a signal, that is, a clock signal (synchronization signal) 21 for synchronization in order to display data on the display device. Reference numeral 3 denotes a display control means for controlling the frame memory, counting addresses for writing data in the frame memory, and writing data in the frame memory. Reference numeral 4 is a frame memory for storing display data. 5
Generates a display data signal 51 from the display data 41 read from the frame memory, and the clock signal 21
Is a display signal generating means for generating a display timing signal 52 for display. Reference numeral 6 is a power management means for transmitting a display off signal 61 in order to reduce power consumption. Reference numeral 7 is an MPU that controls and operates the entire apparatus. An operation for reducing power consumption according to the present invention will be described below with reference to the drawings. FIG. 2 shows the display off signal 6
1 is a diagram showing a means for realizing low power consumption by controlling the display control means 3 and the display signal generating means 5 by 1, and FIG. 3 is a view showing a low power consumption by controlling the clock generating means 2 by the display off signal 61. It is a figure showing the means to do.

FIG. 2 shows a case where the display off signal 61 is inputted to the display control means 3 and the display signal generating means 6. The power management means 6 includes a keyboard, a mouse,
Alternatively, if it is determined that there is no input from another input device and it is not necessary to display the data on the display means, the display is off.
The signal 61 is transmitted.

When the display means 1 is, for example, a liquid crystal display device having a backlight, the backlight is turned off when the display off signal 61 is received, because the power supply for turning on the backlight is cut off. As a result, the power consumed to turn on the backlight is reduced. Upon receiving the display off signal 61, the display control means 3 stops counting the addresses for storing the data in the frame memory and stops writing the data in the frame memory.
Furthermore, the display signal generation means 5 is configured to display the display off signal 61.
When receiving, the supply of the clock signal 21 generated by the clock generating means 2 to the display means 1 is stopped, or the supply of the display data 41 read from the frame memory 4 to the display means 1 is stopped.

FIG. 3 shows a case where the supply of the clock signal 21 to the display control means 3 and the display signal generating means 5 is stopped by the display off signal 61 transmitted from the power management means 6. When the supply of the clock signal 21 is stopped, the display control means 3 stops counting the addresses of the frame memory 4 and writing the data to the frame memory and stops operating. When the supply of the clock signal 21 is stopped, the display signal generating means 5 reads the display data 41 from the frame memory 4, generates and supplies the display data signal 51 to the display means 1, and displays the timing signal for display. 52
The supply of electricity is stopped and the operation stops. Clock signal 21
Supply to the display control means 3 and the display signal generating means 5
By stopping the supply of the power to these means, the means stops operating and consumes less electric power than when the means was operating.

FIG. 4 is a diagram showing the internal structure of the display means 1 shown in FIG. Reference numeral 11 is a display data signal input means for inputting the display data signal 51 transmitted from the display signal generating means 5. The display data signal input means functions as an interface between an external device that supplies the display data signal to the display device and the display device, and when the display off signal 61 is input to the clock generation means 2 shown in FIG. Display of the control means 3 and the display signal generating means 5 of
When the f signal 61 is input, it has a means for detecting that the display data signal is not input and transmitting a display data stop signal 111 as a signal for transmitting the fact to other means. Reference numeral 12 is a display timing signal input means for inputting the display timing signal 52 transmitted from the display signal generating means 5. The display timing signal input means functions as an interface between an external device that supplies the display timing signal to the display device and the display device, and when the display off signal 61 is input to the clock generation means 2 shown in FIG. , A means for detecting that the display timing signal is not input, or all of the display timing signals are input when the display off signal 61 is input to the display control means 3 and the display signal generating means 5. And a means for transmitting the display timing control signal 121 as a signal for detecting the fact that all of them are not input and transmitting this to other means. The display timing control signal includes a display timing full signal indicating that all of the display timing signals have been input and a display timing stop signal indicating that all of the display timing signals have not been input. Also, 13 is
Display off transmitted from the power management means 6 shown in FIG.
A display off signal input means for inputting the signal 61. The display-off signal input means functions as an interface between the power management means 6 and the display device, and when the display-off signal is transmitted from the power management means, the signal is transmitted to each part in the display device to control each part. Is. When the display data signal is supplied to the display data signal input means 11, the reference numeral 14 receives the data and displays the data.
6 is a display data signal generating means for generating a display data signal and passing it to the data display means when the display data signal is not supplied to the display data input means. Whether or not the display data signal is supplied is determined by the display data stop signal transmitted from the display data signal input means. Reference numeral 15 is a display timing signal input means 1
When the display timing signal is supplied to 2,
It is a display timing signal generating means for passing the timing signal to the received data display means 16 and for generating the display timing signal and passing it to the data display means when the display timing signal is not supplied to the display timing input means. Whether all of the display timing signals are supplied is determined by the display timing full signal transmitted from the display timing signal input means,
Whether or not all the display timing signals are supplied is determined by the display timing stop signal transmitted from the display timing signal input means.

FIG. 5 is a diagram showing the internal structure of the display device when the display means shown in FIG. 1 is a liquid crystal display device. The LCD 17 corresponds to the data display means 16 shown in FIG. Reference numeral 18 is a backlight for brightening the LCD 17. The display off signal 61 transmitted from the power management means 6 shown in FIG.
3 is inputted to the display data signal generating means 14, the display timing signal generating means 15 and the backlight 18. In FIG. 5, there are six methods for displaying data on the LCD. This is because the display timing signal input means has three states and the display data signal input means has two states.
By taking one of two states. One of the states is a state in which the display off signal 61 indicates the off level, and includes the display timing signal 52 and the display data signal 51.
All the signals of are input, and by those signals the LCD
The data is displayed on the. This is usually the state when there is input from the keyboard, mouse or other input device. The other five states are display off signal 6
This is the state when 1 indicates an on level. The three states of the display timing signal input means 12 are shown below. One is a state in which all display timing signals necessary for display are input. Normally, the display timing signal 52 necessary for displaying on the LCD is a dot clock signal for synchronizing when sending data to the driver, a horizontal synchronizing signal, a vertical synchronizing signal, and an LCD signal called M signal. It is a signal for alternating current and a signal for resetting a register for scanning line selection. One is
Only some of the display timing signals 52 are input to the display timing signal input means 12. One is a state in which the display timing signal 52 is not input to the display timing signal input means 12.
The two states of the display data signal input means 11 are shown below. One is a state in which the display data signal 51 is input to the display data signal input means 11, and one is a state in which the display data signal 51 is not input to the display data signal input means 11. Above normal status and display off
FIG. 6 shows five states when the signal is on.

In the first state, all of the display timing signals are input to the display timing signal input means, and the display data signal is not input to the display data signal input means. In this state, the display timing signal uses an external signal supplied from the outside of the display means 1, and the display data signal uses the internal signal generated by the display data signal generation means inside the display means 1 for display. Is.

In the second state, a part of the display timing signal is input to the display timing signal input means, and
The display data signal is input to the display data signal input means. In this state, the display timing signal is a part of the external signal supplied from the outside of the display means 1, and the other display timing signal is an internal signal generated by the display timing signal generating means from the part of the external signal. A signal is used, and a display data signal is a state in which display is performed using an external signal supplied from the outside of the display unit 1.

In the third state, a part of the display timing signal is input to the display timing signal input means, and
The display data signal is not input to the display data signal input means. In this state, the display timing signal is a part of the external signal supplied from the outside of the display means 1, and the other display timing signal is an internal signal generated from the part of the external signal by the display timing signal generating means. The display data signal is in a state of being displayed using the internal signal generated by the display data signal generating means inside the display means 1.

In the fourth state, the display timing signal is not input to the display timing signal input means, and the display data signal is input to the display data signal input means. In this state, the display timing signal uses the internal signal generated from the internal oscillator by the display timing signal generating means, and the display data signal uses the external signal supplied from the outside of the display means 1 for display. Is.

The fifth state is a state in which the display timing signal is not input to the display timing signal input means and the display data signal is not input to the display data signal input means. In this state, the display timing signal uses the internal signal generated by the display timing signal generating means from the internal oscillator, and the display data signal uses the internal signal generated by the display data signal generating means inside the display means 1. It is in a state of displaying.

FIG. 7 is a diagram showing the internal structure of the display timing signal generating means 15 shown in FIG. 153
Is an and-gate oscillator switch that switches between activation and deactivation of the oscillator 156. Reference numeral 154 is an and-gate frequency divider switch for switching between input and interruption of the dot clock signal to the frequency divider. Reference numeral 155 is an and gate for switching between input and cutoff of the dot clock signal of the display timing signal 122 supplied from the outside of the display means. Reference numeral 156 is an oscillator for generating a dot clock signal when all of the display timing signals from outside the display means in the fourth and fifth states shown in FIG. 6 are not supplied. Reference numeral 157 is an and gate for switching between input and cutoff of a horizontal synchronizing signal, a vertical synchronizing signal, an AC signal, and a register reset signal for selecting a scanning line in the display timing signal 122 supplied from the outside of the display means. Reference numeral 158 denotes when the horizontal synchronizing signal, the vertical synchronizing signal, the AC signal, and the register reset signal for selecting the scanning line of the display timing signal 122 supplied from the outside of the display means are cut off, that is, in FIG. It is a frequency divider for generating these four signals based on the dot clock signal in the illustrated second, third, fourth, and fifth states. Reference numeral 159 is a gate for taking an OR between a signal supplied from the outside and a signal generated inside.

FIG. 8 shows control signals for the case where all of the input states of the display timing signal to the display timing signal generating means shown in FIG. 7 are input, some of them are input, and no of them are input. It is the figure which showed the state of the switch which switches input and interruption | blocking of the signal from the outside. When all the display timing signals 122 are supplied from the outside, that is, when all of the inputs are present, the display timing full signal indicates H bell and is input. In other states, the display timing full signal indicates L level. When all the display timing signals 122 are not supplied from the outside,
That is, in the state of no input, the display timing stop signal indicates the H level and is input. In other states, the display timing stop signal shows L level.
The oscillator switch 153 is turned on and oscillates only when the display timing stop signal is at the H level.
The dot clock signal switch 155 has a logic opposite state to that of the oscillator switch. The display timing signal switch 157 other than the dot clock signal is turned on only when the display timing full signal is at the H level, and inputs a signal from the outside. The frequency divider input switch 154 is
This shows a state in which the logic is opposite to that of the display timing signal switch.

FIG. 9 is a diagram showing the LCD panel, the drive circuit, and the display data signal generating means. 171 is an LCD
It is a panel. 171a is a switching element composed of a TFT. 171b is a capacitor indicating a liquid crystal cell. Reference numeral 172 is a display data driving unit. 1
Reference numeral 72a is a display data drive circuit, and 172b is a selector for selecting a voltage value applied to the liquid crystal cell. 172c
Is a latch circuit for holding data for one line. 141 is a display data signal output from the display data signal generating means. Reference numeral 173 is a scanning line driving unit, 173a is a scanning line driving circuit, and 173b is a shift register for selecting a scanning line.

Now, consider the operation when the display timing signal or the display data signal is not supplied to the LCD when the power management means 6 shown in FIG. 1 transmits the display off signal 61. In this case, the value of the latch circuit 172c in the display data driving unit 172 is not updated and a constant value is held. Display data drive circuit 172a
Drives the latched display data signal on the screen, so the same data is displayed on the screen.
In addition, the shift register 173 of the scan line driver 173
If the display timing signal is not supplied to b, the register does not shift and the same scan line remains selected. Furthermore, since the display timing signal is not supplied while the voltage value indicated by the display data is being applied to the liquid crystal cell, AC conversion is not performed and a DC voltage is applied. As a result, the life of the liquid crystal cell is extremely shortened. Therefore, when the operation of the logic elements outside the LCD is stopped by the display off signal, or when the clock supply to those logic elements is stopped by the display off signal, the voltage applied to the liquid crystal cell is converted into an alternating voltage. There is a need. Therefore, in the present invention,
As shown in FIG. 8, the display timing signal generating means for alternating current is provided. However, the display timing signal generating means operates during a short time from the transmission of the display off signal until the display means is turned off. After that, the operation is stopped to reduce power consumption. To do. There is an input signal from an input device such as a keyboard or a mouse. When the display off signal is at L level, the display timing signal external to the liquid crystal display device is used to make an alternating current. When the display off signal is not at the H level, the display timing signal generated by the display timing signal generating means in the liquid crystal display device is used for alternating current.

The display data signal generating means 14 shown in FIG.
Is a means provided for avoiding the difficult-to-see state in which the same data is displayed on the screen. This means display o
When the ff signal 132 is input, or when the display data stop signal 111 is input, the display data signal 112 that has been input up to that point is saved in the buffer, and instead is stored in the display data signal generating means. The display off data signal being displayed is transmitted to the display data driver 172. However, this display data signal generating means operates during a short time from the transmission of the display off signal until the display means is brought into the display off state, after which the operation is stopped to reduce power consumption. .. Display off
The data signal is a display data signal that brings the screen to the display off state.

FIG. 10 is a diagram showing a circuit configuration in the display data driving section shown in FIG. Here, it is assumed that there is 3-bit display data for pixels on the screen and 8 gradations are displayed. 174 is a switching element for applying a voltage. The display data signal 141 output from the display data signal generation means is latched by the latch circuit 172c, and the liquid crystal cell 171 is selected by the selector 172b.
The voltage value applied to b is selected. With the above configuration, it is possible to display the value set by the display data generating means regardless of the display data read from the frame memory 4 shown in FIG. Therefore, by setting the display-off data signal in the display data generation means to a value that reduces power consumption, low power consumption can be achieved.

FIG. 11 shows 6 of the display means shown in FIG.
Display off signal 13 shown in FIG. 5 in one of the two states.
1, 132, the display timing control signal 121, that is, the display timing full signal, the display timing stop signal, and the display data control signal 111, that is,
It is a timing chart of a display data stop signal.
When the display off signal is at the L level, both the display timing signal and the display data signal are supplied, which is a normal state. The first to fifth states are displayed o
The ff signal is at the H level, and each is determined by the respective states of the display timing full signal, the display timing stop signal, and the display data stop signal.

[0025]

As described above, according to the present invention, the display o
By providing a means for generating a timing signal and a display data signal for alternating current inside the display device when the ff signal is transmitted, the operation of the display system element can be stopped, and the timing signal and the display signal are displayed on the display device. It is possible to stop the supply of data signals. By making it possible to stop the operation of the display system element, the power consumption of the device can be reduced. In a liquid crystal display device equipped with a backlight, even when the supply of the timing signal to the LCD is stopped and the supply of the display data is stopped, the timing signal and the display data signal are generated inside the display device, so that the alternating current is generated. It is possible to extend the life of the liquid crystal and reduce power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an embodiment for controlling a display control means and a display signal generation means.

FIG. 3 is a diagram showing an embodiment in the case of controlling a clock generating means.

FIG. 4 is a diagram showing an internal structure of a display unit 1 shown in FIG.

5 is a diagram showing an internal structure when the display unit 1 shown in FIG. 1 is a liquid crystal display device.

FIG. 6 is a diagram showing a state of display means 1.

FIG. 7 is a diagram showing an internal configuration of a display timing signal generating means 15.

FIG. 8 is a diagram showing a state of a switch of a display timing generating means.

FIG. 9 is a diagram showing an LCD panel, a drive circuit, and a display data signal generating means.

FIG. 10 is a diagram showing a circuit configuration in a display data driving circuit section.

FIG. 11 is a diagram showing a timing chart of each control signal of the display means.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Display means, 2 ... Clock generation means, 3 ... Display control means, 4 ... Frame memory, 5 ... Display signal generation means, 6 ... Power management means, 7 ... MPU, 11 ... Display data signal input means, 12 ... Display Timing signal input means, 13 ... Display off signal input means, 14 ... Display data signal generation means, 15 ... Display timing signal generation means, 16 ... Data display means, 17 ... LCD, 18 ... Backlight.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G09G 3/20 J 8729-5G 3/36 7319-5G (72) Inventor Tsuji Tateuchi Yokohama City, Kanagawa Prefecture Hitachi, Ltd. Microelectronics Device Development Laboratory, 292 Yoshida-cho, Totsuka-ku (72) Inventor Takao Oba 1 Horiyamashita, Hadano-shi, Kanagawa Hiratsugu Kanagawa factory

Claims (6)

[Claims] 1. An information processing apparatus comprising at least an MPU, a display control means, a frame memory, a clock generation means, a display signal generation means, a power management means and a display means, the display means displaying inside the display means. A display device comprising: a timing signal input means for display, a display data signal input means, a display off signal input means, a timing signal generation means for display, a display data signal generation means, and a data display means. .. 2. The display timing signal input means in the display device according to claim 1 receives the display timing signal generated by the display signal generating means for inputting the clock signal output from the clock generating means, The display data signal input means inside the display device according to claim 1, wherein the display data signal input means receives the display data signal generated by the display signal generating means. The display off signal input means inside the display device according to claim 1 is means for inputting a display off signal generated by the power management means. The display timing signal generating means inside the display device according to claim 1, wherein the display timing signal input means does not receive the display timing signal. When it is detected that, the state at this time the state 1, or, when the display timing signal input means, only a part of the signal of the display timing signal is detected to be entered,
The state at this time is set to state 2, or the above display o
The display data signal generating means in the display device according to claim 1, wherein the display data signal generating means is a means for generating a display timing signal when a display off signal is inputted to the ff signal inputting means. When it is detected that the display data signal is not input, the state at this time is set to state 3, or by means for generating a display data signal when the display off signal is input to the display off signal input means. The data display means according to claim 1, the display data signal input to the display device is displayed on the screen at a timing according to the display timing signal input to the display device, or the display timing signal is displayed. At the timing by the display timing signal generated by the signal generating means,
The display data signal input to the display device is displayed on the screen, or the display data signal generated by the display data signal generating means is displayed on the screen at the timing of the display timing signal input to the display device. Or at the timing of the display timing signal generated by the display timing signal generating means,
A display device comprising means for displaying a display data signal generated by the display data signal generating means on a screen. 3. The display device according to claim 2, wherein in the state 1 according to claim 2, the display off signal output from the power management means is transmitted to the clock generation means,
It is caused by stopping the supply of the clock signal to the display signal generating means, or, in the display signal generating means,
The state caused by transmitting the display-off signal output from the power management unit, wherein the state 2 according to claim 2 is the display-off signal output from the power management unit to the display signal generation unit. In the state 3 of claim 2, the display off signal output from the power management means is transmitted to the clock generation means, and the clock signal to the display control means is transmitted. A display device characterized in that it is caused by a stop of supply, or is caused by transmitting the display off signal outputted from the power management means to the display signal generating means. 4. The display device according to claim 3, further comprising a liquid crystal panel. 5. The display device according to claim 4, further comprising a backlight. 6. The display device according to claim 5, wherein the backlight is turned off by the display off signal output from the power management means.