JPH05204640A - Microprogram control processor - Google Patents

Abstract

PURPOSE:To make it possible to write a program without being conscious of differences in the starting timing of respective operation pipelines and to effectively execute loop instructions by the repeating processing of simple operation. CONSTITUTION:This microprogram control processor is constituted of arithmetic processing circuits 15 to 17 for executing pipeline operations having respectively different starting timing, a horizontal microinstruction register 2 in which instructions relating to the pipeline operations to be executed by respective circuits 15 to 17 are dividedly set up in respective instruction fields 3 to 5, plural delay circuits 6 to 8 connected correspondingly to respective fields 3 to 5 and delaying the starting timing of pipeline operation to be executed by respective circuits 15 to 17, and plural setting registers 9 to 11 connected to respective delay circuits 6 to 8 to previously set up a delay variable corresponding to the starting timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipelined microprogram control processor.

[0002]

2. Description of the Related Art In recent years, a digital signal processing device (hereinafter referred to as a DSP / Digital Signal Proce) that executes at high speed the multiply-accumulate operation that often appears in digital signal processing.
It's called sosor. ) Is used. Also in the field of handling image signals, image signal processing DSPs (image signal processing devices) capable of processing image signals singly have become widespread.

FIG. 4 is a block diagram showing the structure of an image processing DSP. The DSP 41 includes an arithmetic unit 42 dedicated to data calculation and an address generation unit (hereinafter AGU / Address Generatio) dedicated to address calculation.
n Unit).

The control unit 45 controls the AGUs 43a to 43c, the arithmetic unit 42, and the register 46 in accordance with the horizontal micro instruction or the vertical micro instruction stored in the instruction memory 44. The AGUs 43a to 43c calculate the addresses of the external memories 47a to 47c according to the processing program and supply the addresses to the external memories 47a to 47c. The data of the address stored in the external memories 47a to 47c is temporarily held in the register 46. Alternatively,
The calculation is input to the calculation unit 42, and the calculation specified by the program is performed on the data.

Here, the address calculation in the AGUs 43a to 43c and the calculation on the data in the calculation unit 42 are executed in parallel or in a pipeline.

As means for increasing the speed of a processor controlled by a microprogram such as a digital signal processing device,
Conventionally, a pipeline method has been used. In the pipeline structure, instruction issuance and execution time are different, so it is necessary to be aware of that when writing a program.

With the progress of LSI, AGUs 43a to 43
It is possible to incorporate a plurality of processing circuits such as c into one chip and operate them in parallel. In such a micro program control processor, each processing circuit is connected via a register, and the processing itself is pipelined.

In such a micro program control processor, a program must be written taking into consideration not only the time difference between the issuance and execution of an instruction of one processing circuit, but also the difference in execution timing among a plurality of processing circuits.

The pipeline operation will be described with reference to FIG. Assume a 3-stage pipeline processor corresponding to one AGU as shown in FIG. This processor includes registers 51 to 53 and processing circuits A, B, C (5
4 to 56). FIG. 5B shows a timing chart of this processor.

As shown in the figure, d1, d2, d3 are sequentially
Data such as d4 has been input. At time 1, the processing circuit A processes the data of d1 as f _a1 , and the processing circuits B and C do not process it. At time 2, the processing circuit A performs the processing f _{a2 on} the data d2, the processing circuit B performs the processing f _{b1 on} the data d1, and the processing circuit C does not perform the processing.

Further, at time 3, the processing circuit A performs a process called f _{a3 on} the data of d3, and the processing circuit B performs d3.
The processing circuit D performs the processing of f _{b2 on} the data of 2.
Then, the process of f _c1 is performed on the data of d1. Time 4
Then, the processing circuit A performs the processing f _{a4 on} the data d4, the processing circuit B performs the processing f _{b3 on} the data d3, and the processing circuit C performs the processing f _{c2 on} the data d2.
Is performed.

Here, paying attention to one data, for example, d2, the processing performed on the same data d2, f _a2 , f _b2 , and f _c2
The execution timing of is shifted by one clock. Such pipeline processing is generally called an arithmetic pipeline. A series of data d1, d2, d3 ...
Processing (for example, f _a1 , f _a2 , f _a3 , f _a4 ...)
If all are the same, after the pipeline is clogged, that is, after time 3, it is _sufficient to repeat the processing of f _a1 , f _b1 , and f _c1 by the loop instruction, and the execution timing shift during programming. It doesn't have to be taken into consideration.

In recent years, the degree of integration of LSI has become higher and higher, and a processor capable of setting a plurality of arithmetic pipelines can be built in. However, if a plurality of arithmetic pipelines are set, even if each arithmetic pipeline can repeatedly perform arithmetic operations by a loop instruction, etc., if the activation timing of each arithmetic pipeline is different, the regularity of the entire instruction will collapse, and loop instructions, etc. The repeated calculation processing by cannot be used effectively.

This will be described with reference to FIG. A plurality of arithmetic pipelines set are referred to as A, B, and C, respectively. It is assumed that the processing a is repeated in the arithmetic pipeline A, the processing b is repeated in the arithmetic pipeline B, and the processing c is repeated in the arithmetic pipeline C.

If the activation timings of all the pipelines are the same as shown in FIG. 6 (a), it is sufficient to write only one line of a program for processing a, processing b, and processing c and repeat it with a loop instruction. However, when the activation timing of each pipeline is different as shown in FIG. 6B, an extra program is required by the number of steps to compensate for the difference in timing.

That is, from time 1 to time 3, the process a is executed in the pipeline A, and nothing is executed in the pipelines B and C (NOP). Processing a in pipeline A at times 4 and 5
, Pipeline b performs processing b, and pipeline C does nothing (NOP). After time 6, the process a is repeated in the pipeline A, the process b is repeated in the pipeline B, and the process c is repeated in the pipeline C. As described above, after time 6, the loop instruction can be repeatedly used, but from time 1 to 5, the loop instruction cannot be effectively used.

[0017]

As described above, in the conventional micro program control processor, when a plurality of arithmetic pipelines are set, the program becomes very complicated because the activation timing of each arithmetic pipeline is different. .. Further, even in the process of repeating a simple operation, it is necessary to compensate for the deviation of the activation timing of each operation pipeline, so that there is a problem that the loop instruction cannot be effectively used and the program amount increases.

The present invention has been made in view of this point,
The purpose of the present invention is to provide a micro program control processor that can reduce the program amount by effectively using loop instructions and enabling processing by simple repetitive operations even when multiple operation pipelines are set. To do.

[0019]

In order to achieve the above object, the microprogram control processor of the present invention has a plurality of arithmetic processing means for performing pipeline operations with different start timings, and these arithmetic processing means perform the operations. It is composed of a microinstruction in which an instruction relating to a pipeline operation is set, and an activation timing delay means for delaying the activation timing of the pipeline operation performed by each arithmetic processing means.

[0020]

With the above-mentioned structure, the present invention divides the instruction field for each instruction related to the operation pipeline having different activation timing in the horizontal microinstruction, and provides the activation timing delay means for the divided instruction field. When an instruction is executed, the activation timing delay means delays the activation timing for each instruction field, and shifts the instruction execution timing by the difference in the activation timing of each operation pipeline.

When a plurality of arithmetic pipelines are set, the loop instruction can be effectively used so that it can be processed by a simple repetitive operation, and the amount of programs can be reduced.

[0022]

The details of the present invention will be described below with reference to the illustrated embodiments.

First Embodiment FIG. 1 is a block diagram showing the schematic arrangement of a microprogram control processor according to the first embodiment of the present invention.

In FIG. 1, the processor includes an instruction memory 1, an instruction register 2 and instruction fields 3, 4, 3.
5, delay circuits 6, 7, 8 and setting registers 9, 10,
11, an instruction decoder 12, 13, 14 and operation processing circuits 15, 16, 17 (corresponding to A, B, C in FIG. 6).

The instruction memory 1 is a memory in which micro instructions are written. The instruction fields 3 to 5 provided in the instruction register 2 are instruction fields for each of the arithmetic processing circuits 15 to 17. The delay circuits 6 to 8 delay each instruction in the instruction fields 3 to 5 for each instruction field. The setting registers 9 to 11 are registers for presetting the delay amounts of the delay circuits 6 to 8. The arithmetic processing circuits 15 to 17 are arithmetic device groups that perform a series of arithmetic pipeline operations.

When three operation pipelines A, B, and C having different start timings are set as shown in FIG. 6B, processing a, processing b, and processing c are simultaneously performed 1
A row instruction and a loop instruction that repeats the instruction are written in the instruction memory 1. When executing the instruction, the delay circuit 6,
7 and 8 delay each instruction field and shift the instruction execution timing by the difference of the activation timing of each operation pipeline A, B, C.

That is, the instruction for processing a is executed immediately, and the instruction for processing b is executed 3 clocks after the processing a, so that the delay circuits 6 and 7 corresponding to the instruction fields 3 and 4 are executed. Set the delay amount. The delay amount of the delay circuit 8 corresponding to the instruction field 5 is set so that the instruction for performing the process c is executed with a delay of 5 clocks from the process a.

The setting of the delay amounts of the delay circuits 6 to 8 is loaded in the setting registers 9, 10 and 11 in advance. The instructions whose timings have been adjusted by the delay circuits 6, 7 and 8 are decoded by the instruction decoders 12, 13 and 14, respectively, and control the arithmetic processing circuits 15, 16 and 17.

As described above, the instruction fields 3 to 5 divided for each instruction for controlling a plurality of arithmetic pipelines are provided with the delay circuits 6 to 8 for delaying according to the difference in the activation timing of each arithmetic pipeline. As a result, the program can be written without being aware of the difference in the activation timing of the operation pipeline, and the loop instruction is effectively performed in the process of repeating the simple operation.

Second Embodiment In the first embodiment, since there is only one register that sets the delay amount of the delay circuit, when the activation timing of one pipeline changes many times in one program. Must rewrite the contents of the setting register with a load instruction every time the startup timing changes. Therefore, it takes a long time to load. Therefore, in the second embodiment, the delay amount of the activation timing to be delayed is directly described in the horizontal microinstruction, and the delay amount by the delay circuit is determined accordingly.

FIG. 2 shows an example of the horizontal microinstruction in the second embodiment. 21 is an instruction field related to the process a, 22 is a delay amount according to the activation timing of the process a, 2
3 is an instruction field related to the process b, 24 is a delay amount according to the activation timing of the process b, 25 is an instruction field related to the process c, and 26 is a delay amount according to the activation timing of the process c.

Third Embodiment In the second embodiment, when the described delay amount increases, the number of bits representing the delay amount increases, which leads to an increase in the number of horizontal microinstruction bits. Therefore, the change in the startup timing is
When the number of times is limited to a certain number or less, the delay circuit is provided with the setting registers for the number of times and only the setting register is designated in the horizontal microinstruction.

An example of the horizontal micro instruction according to the third embodiment will be described with reference to FIG. Reference numeral 21 indicates an instruction field related to the process a, 22 indicates a register name in which a delay amount according to the activation timing of the process a is set, 23 indicates an instruction field related to the process b, and 24 indicates a delay amount according to the activation timing of the process b. The set register name is designated at 25, the instruction field related to the process c is designated at 25, and the register name at which the delay amount is set according to the activation timing of the process c is designated at 26.

Fourth Embodiment Finally, as a fourth embodiment, an example of using a vertical microinstruction will be described. FIG. 3 shows an example of the vertical microinstruction in the fourth embodiment.

31 is an opcode, 32 is a first operand, 33 is a second operand, 34 is a third operand, 3
Reference numeral 5 represents a delay amount according to the activation timing of one arithmetic pipeline. In the designation of the delay amount in 34, the delay amount itself may be designated as in the second embodiment, or the register name in which the delay amount is set may be designated as in the third embodiment. In the microprogram, as shown in FIG. 3, an operand and a delay amount according to the timing of executing the operand are described.

However, when using the vertical microinstruction,
When executing an instruction, unlike the configuration shown in FIG. 1, the instruction after decoding the micro instruction is delayed by the delay amount specified in the micro instruction and executed.

[0037]

According to the present invention, even if a plurality of operation pipelines each having a different start timing are set, a program can be written without being aware of the difference in the start timing, and a simple operation is repeated. At, the loop instruction is effectively executed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a micro program control processor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing horizontal microinstructions of a microprogram control processor according to second and third embodiments of the present invention.

FIG. 3 is a diagram showing vertical type micro instructions of a microprocessor control processor according to a fourth embodiment of the present invention.

FIG. 4 is a block diagram of a conventional digital signal processing device.

FIG. 5 is a diagram for explaining a pipeline operation of a conventional micro program control processor.

FIG. 6 is a timing chart for explaining the operation of the digital signal processing device.

[Explanation of symbols]

 1 instruction memory 2 instruction register 3-5 instruction field 6-8 delay circuit 9-11 setting register 12-14 instruction decoder 15-17 arithmetic processing circuit

Claims (1)

[Claims] 1. A plurality of arithmetic processing means each performing a pipeline operation with different start timings, and an instruction relating to a pipeline operation performed by these arithmetic processing means are divided and set in an instruction field for each arithmetic processing means. A micro characterized by having a horizontal microinstruction and an activation timing delay means provided corresponding to each of the divided instruction fields and delaying the activation timing of the pipeline operation performed by each arithmetic processing means. Program controlled processor.