JPH0435688U - - Google Patents

Info

Publication number
JPH0435688U
JPH0435688U JP7563390U JP7563390U JPH0435688U JP H0435688 U JPH0435688 U JP H0435688U JP 7563390 U JP7563390 U JP 7563390U JP 7563390 U JP7563390 U JP 7563390U JP H0435688 U JPH0435688 U JP H0435688U
Authority
JP
Japan
Prior art keywords
transformer
oscillator
transistors
input terminals
drive circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7563390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7563390U priority Critical patent/JPH0435688U/ja
Publication of JPH0435688U publication Critical patent/JPH0435688U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案に関するトランス駆動回路の一実
施例を示し、第1図は回路構成図、第2図はトラ
ンジスタのオン、オフのタイミングチヤート、第
3図は他の実施例を示す回路構成図、第4図乃至
第7図は従来例を示し、第4図は回路構成図、第
5図はトランジスタのオン、オフのタイミングチ
ヤート、第6図はトランジスタの立ち上がり、立
ち下がり特性図、第7図は信号とノイズとの関係
説明図である。 主要部分を示す図面の符号の説明、1……トラ
ンス、2……発振器、3……電源、4……ブリツ
ジ回路、Tr1,Tr2,Tr3,Tr4……ト
ランジスタ、a1,a2,a3,a4……ゲート
、5A,5B,5C,5D……回線、R1,R2
,R3,R4……抵抗、5a,5b,5c,5d
……回線、R5a,R5b,R5c,R5d……
抵抗、R5ab,R5cd……抵抗、6,7,8
……インバータ、9A,9B,9C,9D……ダ
イオード。
The drawings show one embodiment of a transformer drive circuit related to the present invention, FIG. 1 is a circuit configuration diagram, FIG. 2 is a transistor on/off timing chart, and FIG. 3 is a circuit configuration diagram showing another embodiment. Figures 4 to 7 show conventional examples, Figure 4 is a circuit configuration diagram, Figure 5 is a transistor on/off timing chart, Figure 6 is a transistor rise and fall characteristic diagram, and Figure 7 is a diagram of the transistor. is an explanatory diagram of the relationship between signals and noise. Explanation of symbols in the drawings showing main parts: 1...transformer, 2...oscillator, 3...power supply, 4...bridge circuit, Tr1, Tr2, Tr3, Tr4...transistor, a1, a2, a3, a4... ...Gate, 5A, 5B, 5C, 5D...Line, R1, R2
, R3, R4...Resistance, 5a, 5b, 5c, 5d
...Line, R5a, R5b, R5c, R5d...
Resistance, R5ab, R5cd...Resistance, 6, 7, 8
...Inverter, 9A, 9B, 9C, 9D...Diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 極性が異なるトランジスタTr1,Tr2同士
及びトランジスタTr3,Tr4同士をブリツジ
接続したブリツジ回路に、発振器から出力される
トランスの駆動信号がトランジスタTr1,Tr
2,Tr3,Tr4の入力端子に入力することに
より、トランスを駆動するトランス駆動回路にお
いて、上記発振器とトランジスタTr1,Tr2
,Tr3,Tr4の各入力端子間とを結ぶ回線の
それぞれにダイオードが互いに逆方向に接続され
発振器及び各入力端子間を結ぶ回線より抵抗値が
小さい回線を並列に接続して構成したことを特徴
とするトランス駆動回路。
The drive signal of the transformer output from the oscillator is transmitted to the bridge circuit in which the transistors Tr1 and Tr2 and the transistors Tr3 and Tr4 with different polarities are bridge-connected.
2. In a transformer drive circuit that drives a transformer by inputting to the input terminals of Tr3 and Tr4, the oscillator and transistors Tr1 and Tr2
, Tr3, Tr4, each of the lines connecting the input terminals has diodes connected in opposite directions to each other, and the line having a resistance value lower than that of the line connecting the oscillator and each input terminal is connected in parallel. Transformer drive circuit.
JP7563390U 1990-07-18 1990-07-18 Pending JPH0435688U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7563390U JPH0435688U (en) 1990-07-18 1990-07-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7563390U JPH0435688U (en) 1990-07-18 1990-07-18

Publications (1)

Publication Number Publication Date
JPH0435688U true JPH0435688U (en) 1992-03-25

Family

ID=31616380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7563390U Pending JPH0435688U (en) 1990-07-18 1990-07-18

Country Status (1)

Country Link
JP (1) JPH0435688U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007325480A (en) * 2006-06-05 2007-12-13 National Institute Of Advanced Industrial & Technology Power integration circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02164280A (en) * 1988-12-19 1990-06-25 Fuji Electric Co Ltd Driving method for insulated gate type bipolar transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02164280A (en) * 1988-12-19 1990-06-25 Fuji Electric Co Ltd Driving method for insulated gate type bipolar transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007325480A (en) * 2006-06-05 2007-12-13 National Institute Of Advanced Industrial & Technology Power integration circuit

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