JPH04314133A - Information processor - Google Patents

Abstract

PURPOSE:To execute the expected processing of a program source at high speed without using such exclusive hardware as to depend on a specified application program. CONSTITUTION:A converting means 2 inputs the program source 1, and converts it into an object 4 for a CPU to be executed in the CPU 7 and the object 3 for an FPGA to be executed in the FPGA 6, and a loading means 5 loads the object 4 for the CPU to the CPU 7, and simultaneously, it loads the object 3 for the FPGA to the FPGA 6. The CPU 7 executes the object 4 for the CPU, but in the process of this processing, it sends necessary data to the FPGA 6 through a connecting means 8, and the FPGA 6 gives the processing determined by the object 3 for the FPGA to this data, and executes the processing to return this result to the CPU 7 through the connecting means 8, and both the units execute the expected processing shown by the program source 1 in cooperation with each other.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an information processing device, and specifically relates to an FPGA (Field Programmer).
The present invention relates to an information processing device that executes a program at high speed using a GateArray.

0002

2. Description of the Related Art Conventionally, in order to improve the execution speed of a program in an information processing apparatus, one of the following methods has been used.

■ Adding dedicated hardware to speed up the processing of a specific application program.

■ Converting a portion of a software program into a microprogram, loading it into control storage, and executing it.

[0005]

[Problem to be Solved by the Invention] Among the above-mentioned conventional methods for speeding up information processing devices, the method (2) of adding dedicated hardware increases the execution speed of the program by the amount of the dedicated hardware. However, since it is necessary to prepare dedicated hardware that depends on a specific program, it has the disadvantage that the device becomes expensive.

[0006] In addition, the method (2) of creating a microprogram does not require dedicated hardware like the method (2), but since microprograms are sequential processes like software programs, it is not possible to speed up that much. I can't hope.

[0007] Therefore, an object of the present invention is to provide information processing that can quickly execute desired processing using a given program source without using dedicated hardware that depends on a specific application program. The goal is to provide equipment.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the information processing device of the present invention includes a CPU, an FPGA,
a connection means for exchanging data between the CPU and the FPGA; and a CPU object that executes a program source on the CPU and an FPGA that executes the program source on the FPGA.
a conversion means for converting the CPU object obtained by the conversion means into a PGA object;
Load the FPGA object into the FP
and loading means for loading into the GA.

[0009]

[Operation] In the information processing apparatus of the present invention, the converting means inputs a program source and converts it into a CPU object to be executed by the CPU and an FPGA object to be executed by the FPGA, and the loading means Objects for FPGA are loaded into the CPU and objects for FPGA are loaded into the FPGA. By this, C
While the PU and FPGA exchange data with each other through the connection means, they execute the CPU object and the FPGA object, respectively, and work together to accomplish the desired processing indicated by the program source.

0010

Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an information processing apparatus according to an embodiment of the present invention includes a CPU 7, an FPGA 6, a connection means 8 for realizing data exchange between the two, and a program source 1 connected to a CPU object 4. and an FPGA object 3, and a loading means 5 that loads the CPU object 4 into the CPU 7 and the FPGA object 3 into the FPGA 6.

In the information processing apparatus having such a configuration, when the program source 1 is given, the conversion means 2 compiles it to generate an object. At this time, the conversion means 2 converts the program source portion of the program source 1 specified by the compile option 10 into the FPGA object 3, and converts the other program source portions into the CPU object 4.

The program source portion to be converted into the FPGA object 3 is, for example, a portion of the program source 1 that particularly requires high-speed processing, or a portion of repetitive processing that requires too much processing time when executed by the CPU 7. This is desirable.

[0014] CPU object 4 by conversion means 2
is generated almost in the same way as a conventional compiler, but
In this embodiment, the intended processing of program source 1 is CP
Because it is executed not only by U7 but also by FPGA6,
Some necessary objects are added to the CPU object 4 along with the division. For example, in order to cause the FPGA 6 to execute processing that was originally performed by the CPU 7, an object is added for processing such as passing processing data to the FPGA 6 through the connection means 8 and receiving the result through the connection means 8.

Furthermore, the generation of the FPGA object 3 by the conversion means 2 involves, for example, first converting the program source part to be converted into a hardware description such as a logical formula, and then converting it based on this hardware description and the configuration information of the FPGA 6. This is done by generating information (mapping information) for causing the FPGA 6 to perform a logical operation that matches the above hardware description. In this case, the mapping information becomes the FPGA object 3. Furthermore, the conversion means 2 is the current FP
Which terminal among the programmable terminals of FPGA 6 is used as an input terminal when executing GA object 3,
Input/output terminal information 11 indicating which terminal is used as an output terminal is generated.

When the conversion means 2 completes the above-mentioned conversion, the loading means 5 transfers the CPU object 4 to the CPU.
7 into a memory (not shown), load the FPGA object 3 into a RAM (not shown) in the FPGA 6,
Start CPU7.

When the CPU 7 is activated, it first reads the input/output terminal information 11 and sets the operation of the connection means 8 through the control line 12. That is, the connection means 8 is, for example, an FPGA.
It has a built-in switch that can arbitrarily change the connection between the signal line connected one-to-one to each terminal of 6 and the signal line connected to the bus of CPU 7. It is possible to perform switching operations according to the situation. Therefore, the CPU 7 inputs and outputs the input/output terminal information 11.
so that the data sent by the CPU 7 itself for the FPGA 6 is input to the input terminal of the FPGA 6 indicated by
The switching device in the connecting means 8 is set by the control line 12 so that the data at the output terminal of the FPGA 6 is input to the CPU 7. By this, FPGA6 and C
Data can be mutually exchanged with the PU 7 via the connection means 8.

Thereafter, the CPU 7 starts executing the CPU object 4. From this point on, the CPU 7 sends necessary data to the FPGA 6 via the connection means 8, and
6 performs the processing specified by the loaded FPGA object 3 on the data, sends the result to the CPU 7 via the connection means 8, and the CPU 7 receives it and continues processing. Both parties cooperate to carry out the intended processing indicated by program source 1.

[0019]

As explained above, in the information processing apparatus of the present invention, repetitive parts of the program source that require a lot of processing time when executed by a CPU, and parts that particularly require high-speed processing are processed using FPGA objects. Because it generates and executes on the FPGA, it has the effect of being able to quickly execute the desired processing using the given program source without using dedicated hardware that depends on a specific application program. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing device according to an embodiment of the present invention.

[Explanation of symbols]

1...Program source 2...Conversion means 3...FPGA object 4...CPU object 5...Loading means 6...FPGA (Field Programmable
Gate Array) 7...CPU 8...Connection means 10...Compile option 11...I/O terminal information 12...Control line

Claims (3)

[Claims] 1. A CPU, an FPGA, and a connection means for exchanging data between the CPU and the FPGA;
a conversion means for converting a program source into a CPU object to be executed by the CPU and an FPGA object to be executed by the FPGA; and loading the CPU object obtained by the conversion means to the CPU;
An information processing device comprising: loading means for loading the FPGA object into the FPGA. 2. The information processing apparatus according to claim 1, wherein the converting means converts a portion of the program source specified by a compile option into an FPGA object. 3. The connection means has a configuration for inputting data outputted from the CPU and destined for the FPGA to an input terminal of the FPGA, and outputting data outputted from an output terminal of the FPGA to the CPU. The information processing device according to claim 1 or 2.