JPH04250709A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To prevent distortion of an output by connecting a constant current transistor (TR) deciding the operating current of a differential amplifier circuit and one conduction channel FET and selecting a gate potential of the FET as a gate potential of the constant current TR or a prescribed potential power supply. CONSTITUTION:The differential amplifier circuit consists of 1st-4th one- conduction channel (N channel) FETs 1, 2, 5 and 10 and 1st and 2nd opposite conduction channel (P-channel) FETs 3,4. A 5th N-channel FET 12 is connected in parallel with a 3rd N-channel FET 5 as a constant current TR in the differential amplifier circuit. Moreover, a gate potential of the 3rd N-channel FET 5 or a low potential power supply line 7 is selected for a gate potential of the 5th N-channel FET 12 by using 1st and 2nd analog switches 13, 14 turned on/off in response to the signal inputted to a 3rd input terminal 16. Thus, the differential amplifier circuit enhancing the drive capability when the operating speed is slow is realized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit implemented in a semiconductor device.

0002

2. Description of the Related Art A conventional differential amplifier circuit includes first to fourth N-channel field effect transistors 30 as shown in FIG.
, 31, 34, 39, and first and second P-channel field effect transistors 32, 33. That is, the first N-channel field effect transistor 30 is
The drain of the first P-channel field effect transistor 32
, and its gate is connected to the first input terminal 35. Second N-channel field effect transistor 3
1 has its drain connected to the drain of the second P-channel field effect transistor 33, and its gate connected to the second input terminal 3.
Connected to 6. Further, the respective sources of the first and second N-channel field effect transistors 30 and 31 are connected to the drain of the third N-channel field effect transistor 34. The third N-channel field effect transistor 34 has its gate connected to the gate and drain of the fourth N-channel field effect transistor 39, and its source connected to the low potential power supply line 38.
is connected to. Further, the first and second P-channel field effect transistors 32 and 33 have their gates connected to each other and then to the drain of the first N-channel field effect transistor 30, and have their respective sources connected to the high potential power supply line 37. is connected to. Fourth N-channel field effect transistor 39
has a drain connected to one end of a constant current source 40, and a source connected to the low potential power line 38. An output terminal 41 is connected to the drain of the second N-channel field effect transistor 31. One end of the load capacitor 42 is connected to the output terminal 41, and the other end is connected to GND.

Next, the operation will be explained. In the N-channel field effect transistor, the drain current can be expressed by equation 1 in the saturation region.

##EQU00001## Similarly, the drain current of a P-channel field effect transistor can be expressed by the formula 2.

[Formula 2] Here, βN and βP are device constants determined by the transistor manufacturing process, gate length, and transistor width. λN and λP are channel modulation coefficients.

On the other hand, the DC amplification factor of the differential amplifier circuit shown in FIG. 5 is expressed by equation 3.

[Equation 3] Here, the second N-channel field effect transistor 3
The mutual conductance of the second P-channel field effect transistor 33 is gm1, the channel conductance is gds1, and the channel conductance of the second P-channel field effect transistor 33 is gds2. The mutual conductance gm2 is expressed by Equation 4 using Equation 1.

[Math 4]

From Equation 4, if the capacitance of the load capacitor 42 is CL, the relationship between the frequency and current at which the gain is 1 is as shown in Equation 5.

[Math 5]

[0006]

Problems to be Solved by the Invention In this conventional differential amplifier circuit, since the current flowing through the circuit is constant, the operating speed of the circuit is limited. Therefore, there is a problem in that the output may be distorted when the input signal frequency becomes high. SUMMARY OF THE INVENTION An object of the present invention is to provide a differential amplifier circuit that can increase drive capability when operating speed is slow.

[0007]

[Means for Solving the Problems] A differential amplifier circuit of the present invention is a differential amplifier circuit comprising first to fourth one-conductivity channel field-effect transistors and first and second opposite-conductivity channel field-effect transistors. The amplifier circuit includes a fifth one-conductivity channel field-effect transistor connected in parallel with the third one-conductivity-channel field-effect transistor as a constant current transistor, and a gate of the fifth one-conductivity channel field-effect transistor and a second one-conductivity channel field-effect transistor. first and second analog switches are provided between the potential power supply line and the gate of the third one-channel field effect transistor, and the first and second analog switches are connected to the third input terminal. The device is configured to be selectively turned on and off by a signal input to the device.

[0008]

[Operation] According to the present invention, the gate potential of the fifth one-conductivity channel field-effect transistor connected in parallel with the third one-conductivity channel field-effect transistor as a constant-current transistor is connected to the second potential power source and the constant-current transistor. By switching to the gate potential of , the drive capability is improved when the operating speed is slow.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention, in which first to fifth N-channel field effect transistors 1, 2, 5,
10 and 12, and first and second P-channel field effect transistors 3 and 4.

First N-channel field effect transistor 1
has a drain connected to the drain of the first P-channel field effect transistor 3, and a gate connected to the first input terminal 8. Second N-channel field effect transistor 2
has a drain connected to the drain of the second P-channel field effect transistor 4 and a gate connected to the second input terminal 9. Further, an output terminal 17 is connected to this drain, and a load capacitor 18 is connected between it and GND. The sources of these first and second N-channel field effect transistors 1, 2 are connected to each other, and these are connected to the third and fifth N-channel field effect transistors.
connected to each drain of the The first and second P-channel field effect transistors 3 and 4 have gates connected to each other and to the drain of the first N-channel field effect transistor 1, and respective sources connected to a high potential power supply line 6. There is. The third N-channel field effect transistor 5 has its gate connected to the gate and drain of the fourth N-channel field effect transistor 10, and its source connected to the low potential power supply line 7. Fourth N-channel field effect transistor 1
0 has its drain connected to one end of the constant current source 11 and its source connected to the low potential power line 7. The fifth N-channel field effect transistor 12 has a source connected to the low potential power supply line 7 and a gate connected to the first and second analog switches 13 and 14.

[0011] The first analog switch 13
The low potential power supply line 7 is connected between the gate of the N-channel field effect transistor 12 and the low potential power supply line 7. The second analog switch 14 is connected between the gate of the fifth N-channel field effect transistor 12 and the gate (drain) of the fourth N-channel field effect transistor 10. These first and second analog switches 13 and 14 are
It is configured as an analog switch that is turned on when the control signal is at the "H" level. The first analog switch 13 is controlled by a signal from a third input terminal 16 through an inverter 15, and the second analog switch 14 is controlled by a direct signal from this third input terminal 16. Ru.

In the above circuit, it is assumed that the gate length and transistor width of the fifth N-channel field effect transistor 12 are the same as those of the third N-channel field effect transistor 5. When the third input terminal 16 is at the "L" level, no current flows through the fifth N-channel field effect transistor 12. At this time, the current flowing through the third N-channel field effect transistor 5 is assumed to be 2I. Let the capacitance value of the load capacitor 18 be CL,
Let fUL be the frequency at which the gain is 1. Next, when the third input terminal 16 is at the "H" level, a current of 2I flows through the fifth N-channel field effect transistor 12. If the frequency at which the gain is 1 at this time is fUH, then the relationship shown in Equation 6 holds true.

[Equation 6] From this relationship, although the gain has decreased, fUH has increased to the square root of 2. Incidentally, the third input terminal 16 is
The frequency characteristics when the signal is set to "level" and "L" level are shown by the chain line and solid line in FIG. 2, respectively.

FIG. 3 is a circuit diagram of an operational amplifier using the differential amplifier circuit of the present invention. That is, a third P-channel field-effect transistor 20 and a sixth N-channel field-effect transistor 21 are newly provided, and the third P-channel field-effect transistor 20 has a gate connected to the gate of the second N-channel field-effect transistor 2. The drain is connected to the differential output terminal 19 connected to the drain, the drain is connected to the output terminal 23, and the source is connected to the high potential power line 6. The sixth N-channel field effect transistor 21 has a drain connected to the output terminal 23, a gate connected to the drain of the fourth N-channel field effect transistor 10, and a source connected to the low potential power supply line 7. . The phase compensation capacitor 22 has one end connected to the differential output terminal 19 and the other end connected to the output terminal 23.

FIG. 4 is a circuit diagram of a second embodiment of the present invention, in which the operational amplifier shown in FIG. 3 is used as the operational amplifier 24, and an error amplifier 25 and a comparator 26 are also used. The operational amplifier 24 has its first input terminal 8 and output terminal 23 connected to a signal output terminal 29 , and its second input terminal 9 connected to a signal input terminal 28 . Further, the positive phase terminal of the error amplifier 25 is connected to the signal terminal 28, and the negative phase terminal is connected to the signal output terminal 29. The positive phase terminal of the comparator 26 is connected to the error amplifier 25.
The reverse phase terminal is connected to the reference voltage source 27,
The output terminal is connected to the third input terminal 16 of the operational amplifier 24.

In this circuit, the operational amplifier 24 forms a signal buffer, and the error amplifier 25 forms the signal input terminal 2.
8 and the signal output terminal 29 is amplified. When the signal input to the signal input terminal 28 becomes faster and the difference from the signal output terminal 29 increases, the output voltage of the error amplifier 25 becomes lower than the voltage value of the reference voltage source 27, and the output of the comparator 26 becomes "H". become the level. As a result, the operating speed of the operational amplifier 24 becomes faster. This embodiment has the feature that the operating limit of the operational amplifier 24 can be detected.

[0016]

As explained above, the present invention connects a fifth one-channel field effect transistor in parallel with a constant current transistor that determines the operating current of a differential amplifier circuit, and Since the potential is switched between the gate potential of the constant current transistor and the second potential power supply, the operating speed of the circuit can be changed, and when the operating speed is slow, the driving capacity is increased to increase the output according to the input signal frequency. This has the effect of preventing distortion.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of a differential amplifier circuit of the present invention.

FIG. 2 is a frequency characteristic diagram of the circuit in FIG. 1;

FIG. 3 is a circuit diagram of an operational amplifier using the differential amplifier circuit of the first embodiment.

FIG. 4 is a block circuit diagram of a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional differential amplifier circuit.

[Explanation of symbols]

1 First N-channel field effect transistor 2 Second N-channel field effect transistor 3 First P-channel field effect transistor 4 Second P-channel field effect transistor 5 Third N-channel field effect transistor 6 High potential power supply line 7 Low potential power supply line 10 Fourth N-channel field effect transistor 11 Constant current source 12 Fifth N-channel field effect transistor 13
First analog switch 14 Second analog switch.

Claims (1)

[Claims] 1. A first one-conducting channel field-effect transistor, the drain of which is connected to the drain of a first reverse-conducting channel field-effect transistor, and the gate of which is connected to a first input terminal; a second one-conducting channel field-effect transistor connected to the drain of the channel field-effect transistor and having a gate connected to a second input terminal; and a drain connected to the sources of the first and second one-conducting channel field-effect transistors. and add the sauce to the second
a third one-conductivity channel field-effect transistor as a constant current transistor connected to the potential power supply line; a gate and a drain connected to the gate of the third one-conductivity channel field-effect transistor; and a source connected to the second potential a fourth one conductivity channel field effect transistor connected to a power supply line, the first and second opposite conductivity channel field effect transistors having respective sources connected to the first potential power supply line and respective gates connected to each other. in the differential amplifier circuit configured such that the third conductive channel field effect transistor is connected to the drain of the first conductive channel field effect transistor, and the output terminal is connected to the drain of the second reverse conductive channel field effect transistor. a fifth one conductive channel field effect transistor connected in parallel with the one conductive channel field effect transistor;
First and second analog switches are provided between the gate of the fifth one-conductivity channel field-effect transistor and the second potential power supply line and the gate of the third one-conductivity channel field-effect transistor, respectively. , these first and second
A differential amplifier circuit characterized in that the analog switch is configured to be selectively turned on and off by a signal input to a third input terminal.