JPH04217869A - Power supply - Google Patents

Abstract

PURPOSE:To reduce the capacity of smoothing capacitor on the input side by suppressing the ripple current on the input side of an inverter. CONSTITUTION:Two power factor improving circuits 6, 6A are connected in parallel on the input side of an inverter and an input voltage Vi is divided through resistors 8, 9. Pulses having periods corresponding to the input voltage detection levels are then delivered, as driving signals D1, D2 having phase difference of 360 deg./2, to the switching elements 3, 3A in the power factor improving circuits 6, 6A from an oscillation circuit 19. Output currents I1, I2 from the power factor improving circuits 6, 6A flow into a smoothing capacitor 7 with rising gradient during H level interval while with lowering gradient during L level interval. Consequently, the input current I function as if it has doubled frequency thus suppressing ripple current.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device having a power factor correction circuit connected to the input side of an inverter.

0002

[Prior Art] Generally, a power supply device inputs a DC voltage and outputs a stable arbitrary voltage, but when the AC power supply voltage is rectified and smoothed using a rectifier diode and a smoothing capacitor and converted to a DC voltage. Even though the AC power supply voltage has a perfect sine waveform, the current flows only during the period when the smoothing capacitor is charged, resulting in a pulse waveform, which causes a drop in the input power factor and becomes a source of high-frequency noise.

A power supply device shown in FIG. 9 has been proposed to prevent such a decrease in the input power factor. This power supply device has a three-phase rectifier circuit 2 that rectifies a three-phase AC power source 1.
A power factor correction circuit 6 consisting of a boost chopper circuit constituted by a switching element 3, an inductance 4, and a diode 5 is connected, and a smoothing capacitor 7 is connected between the output terminals of this power factor correction circuit 6. At the same time, the DC input voltage Vi boosted by the power factor correction circuit 6 and smoothed by the smoothing capacitor 7 is supplied to the first control IC 10 as an input detection voltage divided by the resistors 8 and 9. The control IC 10 outputs a first drive signal D, which is formed so that the input voltage Vi is constant, according to the level of the input detection voltage.
is supplied to the switching element 3 of. The DC input voltage V
i is supplied to an inverter 13 consisting of a transformer 11 and a second switching element 12, and by switching the second switching element 12, the voltage induced in the secondary winding of the transformer 11 is converted by a rectifying and smoothing circuit 14. After rectification and smoothing, a DC output voltage Vo is supplied to the load 15 via output terminals +V and -V. This DC output voltage Vo is the second output detection voltage divided by the resistor 16 and resistor 17.
The control IC 18 supplies the second switching element 12 with a drive signal formed so that the output voltage Vo is constant according to the level of this output detection voltage.

As described above, in the power supply device including the power factor correction circuit 6 on the input side of the inverter 13, the first switching element 3 of the power factor correction circuit 6 is turned on by the drive signal D. At times, electromagnetic energy is accumulated in the inductance 4, and when the first switching element 3 is off, the accumulated electromagnetic energy and the output current from the three-phase rectifier circuit 2 are combined and passed through the diode 5 to the smoothing capacitor 7. By charging the current waveform, the input power factor is improved by bringing the current waveform closer to the AC voltage waveform. In this case, the waveform of the input current I flowing into the smoothing capacitor 7 changes when the drive signal D is turned on, as shown in FIG. There is an upward slope during the off period and a downward slope during the off period.

[0005]

[Problems to be Solved by the Invention] In the above-mentioned prior art, since only one power factor correction circuit 6 is provided, the inductance L of the power factor correction circuit 6 is particularly large in a power supply device with a large current capacity. This causes a problem in that the ripple current increases and a large capacity smoothing capacitor is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply device that can reduce the ripple current generated on the input side of an inverter and reduce the capacity of the smoothing capacitor on the input side.

[0007]

[Means for Solving the Problems] The present invention rectifies the AC power supply voltage using a rectifier circuit, and also includes a power factor correction circuit for switching a switching element to bring the voltage waveform and current waveform of the AC power supply voltage close to each other. In a power supply device that supplies a DC input voltage smoothed by a smoothing capacitor to an inverter, n pieces of the power factor correction circuits are connected in parallel, and a drive signal is supplied to the switching element of each of these power factor correction circuits. The oscillation circuit is 360°/n
A drive signal having a phase difference of 1 is supplied to each switching element.

[0008]

[Operation] With the above configuration, 360°/360° from the oscillation circuit
A drive signal having a phase difference of n is supplied to each switching element, whereby each switching element of the n power factor correction circuits is sequentially driven with a phase difference of 360°/n, and the driving signal of the n power factor correction circuits is sequentially driven with a phase difference of 360°/n. The output currents are combined and flow into the smoothing capacitor.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Note that the same parts as in FIG. 9 are given the same reference numerals, and detailed explanations of the same parts are omitted.

FIGS. 1 to 4 show a first embodiment of the present invention, and as shown in FIG. 1 power factor correction circuit 6, inductance 4
A, a second power factor correction circuit 6A consisting of a diode 5A and a third switching element 3A are connected in parallel,
A drive signal having a phase difference of 360°/2 is supplied from the oscillation circuit 19 built in the control IC 10A to the first and third switching elements 3 and 3A of the first and second power factor correction circuits 6 and 6A. It is now possible to do so. The oscillation circuit 19 is shown in Figure 2.
As shown in FIG. 2, the output signal S1 of the reference signal generation circuit 20, which outputs a pulse with a constant period according to the input detection voltage level, is sent to the clock input terminal CK of the flip-flop 21A and each NAND gate through a voltage-frequency conversion circuit (not shown).
The reference voltage Vcc for driving the flip-flop 21A is supplied to the power supply terminal V of the flip-flop 21A.
cc and is applied to the input terminals J and K via the current limiting resistor 23. Based on the output signal S1 from the reference signal generation circuit 20, output signals S2 and S3 are output from the non-inverting input terminal Q and the inverting input terminal Q' of the flip-flop 21A, respectively, to the NAND gate 22A,
180 from the output terminal of each NAND gate 22A, 22B by being supplied to the other input terminal of 22B.
The drive signals D1 and D2 having a phase difference of .degree. are output.

Next, the operation of the above structure will be explained. When the power is turned on, the power supply voltage from the three-phase AC power supply 1 is rectified by the three-phase rectifier circuit 2, and this rectified voltage is passed through the first and second power factor correction circuits 6, 6A to the smoothing capacitor 7. The voltage output from the inverter 13 is smoothed and then supplied to the load 15 after being rectified and smoothed by the rectification and smoothing circuit 14 . In this case, in the oscillation circuit 19, the input terminals J and K of the flip-flop 21A are both at H level as shown in the time chart of FIG. Stand up and flip flop 21A
At that moment, the output signal S2 from the output terminal Q becomes H level, and the output signal S3 from the output terminal Q becomes L level. This flip-flop 21A holds the states of the output terminals Q and Q' until the output signal S1 from the reference signal generation circuit 20 rises from the L level to the H level again, and this output signal S1 also rises to the H level. The output terminals Q and Q' invert their states at the moment of rising, so each time the output signal S1 rises to H level, the output signals S2 and S
3 are switched to L level or H level while maintaining an inverted state, and are outputted to each NAND gate 22A, 22B. Then, as shown in FIG. 3, during the period when both the output signal S1 and the output signal S2 are at the H level, the drive signal D1 from the NAND gate 22A is at the L level, and the output signal S1
and output signal S3 are both at H level, the NAND game
Since the drive signal D2 from the port 22B becomes L level,
The drive signals D1 and D2 are outputted with a phase difference of 180 degrees according to the output signal S1 from the reference signal generation circuit 20, and are outputted to the switching elements 3 and 3A of the first and second power factor correction circuits 6 and 6A. supplied to

Therefore, as shown in the waveform diagram of FIG.
The on period of the switching element 3, that is, the drive signal D1
During the period when is at H level, the output current I of the first power factor correction circuit 6
1 has an upward slope, and during the off period of the first switching element 3, that is, the period when the drive signal D1 is at L level, the output current I1 has a downward slope. The output current I2 of the second power factor correction circuit 6A has the same shape as the output current I1 and has a phase difference of 180° from the output current I1 due to the operation of the third switching element 3A based on the drive signal D2. Therefore, the input current I flowing into the smoothing capacitor 7 has an upward slope when the drive signals D1 and D2 are at the H level, and has a downward slope when the drive signal D1 or D2 is at the L level. It acts to have twice the frequency, and the ripple current is 1
/2, thereby making it possible to reduce the capacitance of the smoothing capacitor 7, which is particularly effective in a power supply device with a large current capacity.

FIGS. 5 to 8 show a second embodiment of the present invention, in which the same parts as in the first embodiment are given the same reference numerals and detailed explanations of the same parts will be omitted.

In FIG. 5, second, third, and fourth power factor improvement circuits 6A, 6B, and 6C are connected to the first power factor improvement circuit 6.
are connected in parallel, and the oscillation circuit 19A is connected to each switching element 3, 3A, .
Drive signals D1', D2', D with a phase difference of 0°
As shown in FIG. 6, the oscillation circuit 19A is configured to supply signals from the output terminal of the AND gate 22C to the clock input terminal CK of the flip-flop 21B and one of the NAND gates 22E and 22F. An output signal S4 is supplied to the input terminal of the AND gate 22D, and an output signal S5 is supplied from the output terminal of the AND gate 22D to the clock input terminal CK of the flip-flop 21C and one input terminal of each of the NAND gates 22G and 22H. Reference voltage Vc is applied to the power supply terminal Vcc of 21B and 21C.
A reference voltage Vcc is supplied to input terminal J and input terminal K via current limiting resistors 23A and 23B. Then, the output terminal Q of the flip-flop 21B
and each NAND gate 22E from the output terminal Q'.
, 22F are supplied with the output signals S6, S7 to the other input terminals of the NAND gates 22E, 22F to the switching elements 3, 3A of the first and second power factor correction circuits 6, 6A. While outputting the drive signals D1' and D2', the output terminals Q and Q' of the flip-flop 21C are connected to the NAND gates 22G and 22H, respectively.
Supplying output signals S8 and S9 to the other input terminal of
From the output terminals of these NAND gates 22G and 22H, each third
, and are configured to output drive signals D3 and D4 to the switching elements of the fourth power factor correction circuits 6B and 6C.

As shown in the time chart of FIG. 7, the oscillation circuit 19A receives the output signal S from the reference signal generation circuit 20.
18 from AND gates 22C and 22D for every pulse of 1
Output signals S4 and S5 having a phase difference of 0° are applied to the clock input terminal C of each flip-flop 21B and 21C.
K is supplied. This flip-flop 21B, 21C
holds the states of the output terminals Q, Q' until the output signals S4, S5 rise from the L level to the H level, and at the moment the output signals S4, S5 rise to the H level, the output terminals Q, By switching the state of Q', the output signal S
6, S7 and output signals S8, S9 are outputted to each NAND gate 22E, 22F and each NAND gate 22G, 22H while maintaining mutually inverted states. As a result, both the output signals S4 and S6 become H level, the drive signal D1' from the NAND gate 22E becomes L level, and then the output signals S5 and S8 and the output signal S
4, S7, and the output signals S5, S9 sequentially become H level, thereby each NAND gate 22E, 22F, 2
Drive signal D1 '→D3 →D2' from 2G and 22H
→D4 is output with a phase difference of 90°, and the first
- Supplied to the fourth power factor correction circuits 6 to 6C.

Therefore, as shown in the waveform diagram of FIG. 8, the input current I flowing into the smoothing capacitor 7 acts as if it had four times the frequency as compared to the conventional one shown in FIG. The current can also be reduced to 1/4, and the capacity of the smoothing capacitor 7 can also be reduced.

Note that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope of the gist of the present invention. For example, although a step-up chopper circuit is used as the power factor correction circuit, a step-up/down chopper circuit or the like may also be used, and a transistor or the like may be used instead of an FET as the switching element. Furthermore, the inverter can be applied to various types. Furthermore, a single-phase AC power source may be used instead of the three-phase AC power source.

[0018]

Effects of the Invention The present invention rectifies the AC power supply voltage using a rectifier circuit, and also uses a smoothing capacitor via a power factor correction circuit for switching a switching element to bring the voltage waveform and current waveform of the AC power supply voltage close to each other. In a power supply device that supplies a smoothed DC input voltage to an inverter, n power factor correction circuits are connected in parallel, and an oscillation circuit that supplies drive signals to switching elements of each of these power factor correction circuits is 360. A drive signal with a phase difference of °/n is supplied to each switching element, which reduces the ripple current generated on the input side of the inverter and reduces the capacitance of the smoothing capacitor on the input side. We can provide a power supply device that can

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a power supply device showing a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of an oscillation circuit showing a first embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the oscillation circuit according to the first embodiment of the present invention.

FIG. 4 is a waveform diagram of drive signals and current showing the first embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a power supply device showing a second embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of an oscillation circuit showing a second embodiment of the present invention.

FIG. 7 is a time chart showing the operation of an oscillation circuit according to a second embodiment of the present invention.

FIG. 8 is a drive signal and current waveform diagram showing a second embodiment of the present invention.

FIG. 9 is a circuit configuration diagram of a power supply device showing a conventional example.

FIG. 10 is a drive signal and current waveform diagram showing a conventional example.

[Explanation of symbols]

1 Three-phase AC power supply (AC power supply) 2 Three-phase rectifier circuit (rectifier circuit) 3, 3A Switching element 6, 6A, 6B, 6C Power factor correction circuit 7 Smoothing capacitor 19, 19A Oscillator circuit

Claims (1)

[Claims] 1. Direct current that is rectified by a rectifier circuit and smoothed by a smoothing capacitor through a power factor correction circuit for switching a switching element to bring the voltage waveform and current waveform of the AC power source voltage closer together. In the power supply device that supplies input voltage to the inverter,
The n power factor correction circuits are connected in parallel, and an oscillation circuit that supplies a drive signal to the switching elements of each of these power factor correction circuits supplies a drive signal having a phase difference of 360°/n to each switching element. A power supply device characterized in that it is configured to.