JPH03276228A - Microprocessor processing system - Google Patents

Abstract

PURPOSE:To improve the processing speed of a microprocessor with application of the merits of both hard-wires and microprogram systems by generating an instruction in the microprocessor in addition to the instruction given from the outside via software, and setting and executing the instruction in the memory. CONSTITUTION:When an NMI request 2 is accepted from the outside, an NMI control circuit 1 is set and an NMI-SEL signal 3 becomes active. Then a code generating part 6 selects a CALLNN instruction 4b generated previously after a power supply is turned on with the signal 3 which is directly inputted to a selector 4. The instruction 4b is outputted to an instruction register 8. Thus a microprocessor interrupts the processing under execution and carries out an NMI control routine processing. In such a constitution, the merits of both hard-wired and microprogram systems are secured and the processing speed is improved for the microprocessor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a program processing method in a combinator, and particularly to a microprocessor processing method.

(Prior Art) In general, microprocessor processing is performed by hard-wired processing or microprogram processing, and each processing method has the following characteristics. That is, in hard-wired processing, the logic link is configured with l\-ware, so the processing speed is fast. - On the other hand, the microprogram method is ROM
Since processing is executed using a combination of microinstructions stored in the memory, the hardware configuration is simplified.

(Problem to be solved by the invention) However, although hard-wired processing is characterized by high processing speed, it requires its own sequencer for each process, resulting in an increase in hardware and complexity. There was a problem that this led to a decrease in reliability. On the other hand, the microprogram method simplifies the hardware configuration, but has the problem of slowing down the processing speed because it executes processing using a combination of microinstructions.

The present invention was made in view of the above circumstances, and while maintaining the processing speed of the hard-wired system, some processes are executed using a combination of machine language instructions instead of micro-instructions. The purpose of this invention is to realize hardware that has the advantages of both microprogram systems and to provide a microprocessor processing system with improved performance.

[Structure of the Invention] (Means and Effects for Solving the Problems) In order to achieve the above object, the present invention provides a storage means for storing instruction codes of processing to be executed in processing of a microprocessor; a process instruction means for interrupting the process being executed and instructing the next process to be executed in response to a request from the process instruction means; a code generating means for generating in advance an instruction code accompanying the process instructed by the process instruction means; Since the configuration includes code selection means for selecting an instruction code generated by the generation means and storing it in the storage means based on instructions from the processing instruction means, the microprocessor By generating an instruction (aI machine language) internally, setting the instruction in the storage means, and executing the process, it is possible to improve the processing speed by taking advantage of both the hard-wired and microprogram systems.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

As shown in Figure 1, N
The MI control circuit 1 is set by an external NMI request 2 and outputs an NM, l-8EL signal 3. The NMI control circuit 1 coordinates the NMI request 2 and other requests (not shown), and controls the NMI control routine to be executed at an appropriate timing. N M 1 (Non Ma
skable 1netrupt) is an "interrupt that cannot be masked" and is always accepted even if the microprocessor is executing any other processing routine. In the NMI control routine, the contents of the program counter PC (not shown), which holds the address of the next instruction to be executed, are saved in the stack (not shown) and then jumps to a specific address 7NN'. This is equivalent to setting the destination address to "NN" by a CALL "NN" command by a normal external software command. For example, if rZ 80J is adopted as the microprocessor, “0086
B “Jump to address fixedly.

NM]-8EL signal 3 output from NMI control circuit 1
is input directly and via an inverter 5 to a selector 4 composed of a multiplexer. On the other hand, selector 4 contains external program 5 in the normal routine.
A program code 4a, which is an instruction code according to the above, and a CALL "NN" command 4b, which is generated by a code generating section 6 that generates a code corresponding to a CALL "NN" command by an external software command, are input. This code generator 6 is composed of simple hardware such as a switch that can obtain a fixed level, and after the microprocessor is started, it automatically generates a code (machine language) corresponding to the CALL NN" code at a fixed binary level. ) is generated. Each of these input instruction codes is sent to the selector 4.
, the program code 4a is passed through the inverter 7
The MI-8EL signal 3 and the CALL NN'' instruction 4b are selected by logic gates (not shown) by the directly inputted NMI-8EL signal 3, and set in the instruction register 8 that stores the instruction code to be processed next. Ru.

Next, the operation of one embodiment of the present invention having the above configuration will be explained.

Normally, NMI request 2 is not input, so NM
The I-8EL signal 3 becomes inactive, and the NMI-SEL signal 3 input to the selector 4 via the inverter 7 selects the instruction code 4a from the external program 5 and outputs it to the instruction register 8. Therefore, a microprocessor executes instructions according to a program.

On the other hand, when NMI request 2 is received from the outside and is accepted, NMI
Since the MI control circuit 1 is set and the NMI-3EL signal 3 becomes active, the NMI-3EL signal 3 that is directly input to the selector 4
The MI-3EL signal 3 causes the code generator 6 to issue a CALL NN" command 4 which is generated in advance after the power is turned on.
b is selected and output to the instruction register 8. Therefore, the microprocessor interrupts the process currently being executed and N
Executes MI control routine processing. In other words, as an operation to interrupt the process being executed, for example, after saving the contents of the block counter PC, which holds the address of the instruction by the program to be executed next, to the stack,
Specific jump destination address “NN” in Z 80J
Processing corresponding to the processing specified by the address, that is, the CALL “NN” instruction 4b generated by the code generation unit 6
Execute processing based on.

It goes without saying that the present invention is not limited to the above-mentioned embodiments and can be modified in various ways.

[Effects of the Invention] As detailed above, according to the microprocessor processing method of the present invention, the microprocessor processing method includes hardware that generates instructions inside the microprocessor by means of a code generation means, in addition to instructions given by an external program. By executing processing based on instructions, it has the advantages of both hard-wired and microprogram methods, so processing speed can be improved, and the code generation means is composed of simple hardware. Therefore, the circuit configuration is simplified, and reliability is improved and costs are reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. ■...NMI control circuit (processing instruction means), 2...N
MI request, 4... Selector (code selection means), 6... Code generation unit (code generation means), 8... Instruction register (storage means).

Claims (1)

[Claims] In the processing of a microprocessor, a storage means for storing an instruction code of a process to be executed, a process instruction means for interrupting the process being executed in response to an external request and instructing the process to be executed next, and this process instruction. code generating means for generating in advance an instruction code associated with a process instructed by the means; and code selecting means for selecting an instruction code generated by the code generating means and storing it in the storage means based on an instruction from the processing instruction means. A microprocessor processing method characterized by comprising: