JPH0318925A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To shorten the computation time and to attain a high speed operation with an arithmetic circuit by dividing the input data into blocks of smaller bits and carrying out simultaneously the increment arithmetic operations for each block. CONSTITUTION:The input data of 32 bits is divided into 8 blocks of 4 bits respectively, and the incrementers 51 - 58 and selectors 61 - 68 are prepared for each block. The incrementers 51 - 58 perform previously and simultaneously the increment arithmetic operations based on the increment instructions IC by supposing that the carries are given from the lower rank blocks. Then the selectors 61 - 68 perform the increment arithmetic operations in parallel with each other for each block or select simultaneously the data as they are with no increment arithmetic operation based on the selection signals CIN - C28 which are separately obtained and the output of the selectors 61 - 68 are taken out as the output data. As a result, the increment arithmetic operations are carried out simultaneously and in parallel with each other for each block. Thus it is possible to perform the increment arithmetic operations in multi-bit at a high speed.

Description

[Detailed Description of the Invention] [) Overview] Regarding an arithmetic circuit called an incrementer, a high-speed LSI
The purpose is to provide a high-speed arithmetic circuit that can be applied as a component of n-bit data. A calculation means that divides into small m-bit blocks and performs an increment operation in advance for each block, a carry detection means that detects a carry from the lower bits for each block, and an output of the calculation means for each block. and m-bit human input data bypassing the arithmetic means are connected to each other, and selection means for each block selectively selects these based on the output of the carry detection means. The configuration is configured to extract the data of the increment operation from the output of .

[Industrial application field]

The present invention relates to an arithmetic circuit, and more particularly to a circuit that performs numerical calculations, and relates to an arithmetic circuit called an incrementer that performs an operation of adding 1 to the least significant bit of a numerical value.

The increment operation is necessary when, for example, rounding a numerical value or taking two's complement of a numerical value, and is especially frequently used in processors and the like that perform numerical operations.

Here, the rounding process refers to the process of cutting off seven extra numerical bits or adding 1 to the least significant bit of a numerical value so that the result of an operation conforms to a specific numerical formant. For example, this is a process required when converting a high-precision numerical value into a low-precision numerical value. The rounding method is defined, for example, in the IEEE standard.

Further, an operation that takes two's complement is an operation that inverts the bits of a certain numerical value and adds 1 to the least significant bit, which is an increment operation.

[Prior Art] For example, there is a conventional incrementer as shown in FIG.
Half addition n (denoted as HA in the figure) is a 32-bit incrementer constructed by serially arranging bits 1 to 32. In the figure, Al-A32 has 32-bit input data, 0
1 to 032 are 32-bit output data, and CIN is a carry signal, which is used, for example, when 11111 is set and incremented when performing rounding processing. The general terminal relationship of the 1-bit half adder 1 used in FIG. 5 is shown in FIG. 6(a), and its logic circuit is as shown in FIG. 6(b).
, an AND gate 42, a Nandt gate 43, and an inverter 44, and operates as expressed by the following truth table.

That is, when inputs A and B are both l゛, carry C is “
l", and a carry occurs in the most significant digit. S is the addition value (S c + m). In the case of 32-bit increment, the value of the most significant digit is increased by repeating this carry propagation up to 32 times. Determine.

[Problem to be solved by the invention]

However, such a conventional incrementer has the disadvantage that the calculation time increases in proportion to the bit length of the numerical value being handled, since the half adders are simply connected serially.

For example, if it takes 2 ns to calculate the focus half adder, a 32-bit incrementer takes 2 ns.
A computation time of X32=64ns is required.

In recent years, there has been a demand for LSI circuits to operate at high speed, and the bit length of the numerical values they handle tends to become longer. For example, recently the operating frequency is 25M+1z (40n
Numerical calculation processors that handle 64-bit data in s cycles have also been developed.

However, since the incrementer with the conventional configuration is slow, it cannot be used in a high-speed processor as described above.

Therefore, an object of the present invention is to provide a high-speed arithmetic circuit that can be applied as a component of a high-speed LSI.

[Means to solve the problem]

In order to achieve the above object, an arithmetic circuit according to the present invention divides n-bit input data into smaller m-bit blocks in an arithmetic circuit that performs an increment operation of adding 1 to the least significant bit of n-bit data. At the same time, there is a calculation means that performs an increment calculation in advance for each block, a carry detection means that detects a carry from the lower bit for each block, and a circuit that bypasses the output of the calculation means for each block and the calculation means. A selection means for each block is connected to be supplied with m-bit input data and selectively selects them based on the output of the carry detection means, and the data for the increment operation is provided from the output of the selection means. Configure to retrieve.

[Effect]

In the present invention, the arithmetic means performs an increment operation for each block in advance, and the output of the arithmetic means and the m-bit input data bypassing the arithmetic means are selected by the selection means based on the output of the carry detection means. , and the selected output becomes the output result of the increment operation.

Therefore, compared to conventional increment operations in which increment operations are performed serially, each block is divided and increment operations are performed at the same time, reducing the operation time and increasing speed.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 4 are diagrams showing an embodiment of the arithmetic circuit according to the present invention, and are an example of a 32-bit (n=32) incrementer. FIG. 1 is a block diagram of a 32-bit incrementer. In this diagram, the 32-bit incrementer of this embodiment converts 32-bit input data into 4-bit (m-
4) into eight blocks, and each block has 4-bit incrementers 51 to 58 and selectors 61 to 6.
There are 8.

Incrementers (corresponding to calculation means) 51 to 58 are “1”
An increment operation is performed simultaneously for each block based on Lebel's increment instruction IC, and the increment instruction IC is output in advance assuming that, for example, rounding is to be performed to a 32-bit value.

One of the incrementers 51 to 58, for example, the incrementer 51, has the terminal relationship as shown in FIG. 2(a), and its internal circuit includes three half adders 69 as shown in FIG. ~71 and one exclusive or gate 7
2. The reason why the 4th bit is an exclusive OR gate 72 is to obtain a carry signal from the 4th bit using a separate circuit. Therefore, in the circuit shown in FIG. 2(b), the carry signal input from the least significant bit (for example, the signal of ClN-1) is sequentially propagated to the half adders 70 and 71 of the higher digits, and - The output of the 4th bit is obtained from the sive-or gate 72.

On the other hand, selectors (equivalent to i! Sawahira means) 61 to 68 are supplied with the outputs of incrementers 51 to 58, respectively, and four
Data lines are connected so that bit input data is supplied, and one of the selectors 61 to 68, for example, selector 61, has a terminal relationship as shown in FIG. 3(a).
As shown in FIG. 3(b), its internal circuit includes an inverter 80, AND gates 81 to 88, and OR gates 89 to 88.
92. Selector 61 receives selection signal SEL
When SEL is “1”, the output data (incremented data) of the incrementer 51 is selected, and the signal SEL is “1”.
0'', the data that bypasses the incrementer 51 (
Select and output the data (before incrementing) as is. The selection signal SEL is output from the carry detection means 93, and the carry detection means 93, as shown in FIG. It is composed of AND gates 102 to 108 that detect the presence or absence of a carry in the lower half.
The signals are output from the terminals 04 to C32 to the selectors 61 to 68, respectively. In addition, the selection signal terminals 04 to C3 in FIG.
2 are connected to the ClN-C 28 from the lower side in FIG.

In the above configuration, when performing a 32-bit increment operation, first send an increment command IC to activate the incrementers 51 to 58, and assume that there is a carry from the lower block. Perform an increment operation each time. Then,
The carry detection means 93 selects whether or not there is a carry to each block using a separately obtained selection signal, and the selectors 61 to 68 perform an increment operation for each block in parallel or use the data as it is without incrementing. The selection process is performed at the same time, and the selector 61
-68 outputs are taken out as output data.

Therefore, compared to the conventional state in which increment operations are performed serially, in this embodiment, each block is divided and increment operations are performed simultaneously in parallel, so the critical path in this case is the AND gate 94.
, the AND gate 108 part, and the selector 68 part, and the calculation time is about 1 QnS. This is 1/16 to 1/8 of the conventional example, making it extremely fast.

As a result, even if the bit length of the numerical values to be handled increases, the calculation time does not increase proportionally. In particular, although the circuit scale of this embodiment is slightly larger, it is extremely useful when high speed performance is required, and is extremely optimal as a component of a high-speed LSI.

Note that in the above embodiment, 32 bits are divided into 8 blocks of 4 bits each, but this is not limiting. It may also be constructed using four 8-bit 2:1 selectors.

〔Effect of the invention〕

According to the present invention, a multi-focus increment operation can be performed at high speed, and an incrementer that is effective as a component of a high-speed LSI can be obtained.

[Brief explanation of drawings]

1 to 4 are diagrams showing one embodiment of the arithmetic circuit according to the present invention. Fig. 3 is a diagram explaining the selector, Fig. 4 is an l1liil path diagram of the carry detection means, and Fig. 5.6.
The figures show a conventional incrementer, FIG. 5 is its overall block diagram, and FIG. 6 is a diagram explaining its half adder. 51-58... Incrementer (calculation means) 6
1-68...Selector (selection means), 69-7
1... Half Adder 72... Exclusive or Gate, 80.
...Inverter, 81-88... Antogame-1, 89-92.
...OR gate, 93...--digit detection means, 94-108...Ant gate. Figure 94-108: Circuit diagram of carry detection means in an embodiment of the AND gate; Overall block diagram of a conventional incrementer Figure 94-108: Diagram explaining the selector of an embodiment of the 8H2 NOR gate. figure diagram

Claims (1)

[Claims] In an arithmetic circuit that performs an increment operation of adding 1 to the least significant bit of n-bit data, the n-bit input data is divided into smaller m-bit blocks, and each block is an arithmetic means that performs an increment operation in advance, a carry detection means that detects a carry from the lower bit for each block, and an output of the arithmetic means for each block and m-bit input data bypassing the arithmetic means. and selecting means for each block that selectively selects these based on the output of the carry detection means, and is configured to extract data for the increment operation from the output of the selection means. An arithmetic circuit characterized by: