JPH0317899A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To remarkably reduce the test time of a memory by providing mask ROMs of two word lines other than a memory cell, and detecting the defect of a column system by reading out the mask ROM. CONSTITUTION:The mask ROM 31 for defect detection is provided collateral with a memory cell array 11. The contact of transistors TR 211-2, 212-4,... on a first row to drains are taken at every two bit lines, and that of the TRs 212-1, 212-3,... on a second row to the drains are taken as every two another bit lines. Here, a word line (a) on the first row is connected by connecting the gate of each TR on the first row, and a word line (b) on the second row is connected by connecting the gate of the TR on the second row. When the word line (a) is selected, the potential of the word line goes to high potential, low potential,..., and the word line (b) changes in reverse sequence. At such a case, since the potential of the bit line is set at different potential when a bit line 132 is grounded, the defect can be easily detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory having a redundancy circuit.

(Prior art) In recent years, large-capacity memories have been designed to prevent defects from occurring during manufacturing by having redundant cells that can be replaced with normal memory cells other than memory cells that are normally accessed. There is something that can save the cell. Redundant cells for this purpose are often provided in the memory cell array 1 as redundant rows i and redundant columns j, as shown in FIG. For example, if we have 4 rows and 4 columns redundancy, if there are defects shown by the solid lines and crosses in Figure 7(a), these defects will be removed as shown in Figure 7(b). By replacing the row column containing redundant row i and column j, a good product can be obtained. FIG. 8 shows a conventional EPROM, where 11 is a memory cell array and 12 is a memory cell array.
,... are word lines, 13,... are bit lines, 14,
. . . are EPROM cells, and 15, . . . are Y selection transistors. Conventionally, as described above, defective cell detection is carried out by performing an address test on all memories, and detecting defective addresses in the tester's fail memory (Fail memo).
ry), and after the test was completed, we decided which redundancy row and column to replace with.

(Problem to be solved by the invention) However, with this method, it was not possible to judge whether or not relief by redundancy was possible until all addresses had been tested, and it was necessary to test all addresses even if the memory was clearly defective. . Especially EPs that require a long time to write.
In memories such as ROM (ultraviolet erasable FROM),
It was a huge waste of testing time. For this reason, in a memory such as an EPROM that requires a long time to write, for example, if redundancy exists only in rows, writing is performed row by row, and the number of defective rows is counted. There is an improvement method such as ending the test when the number of cases exceeds .
This method cannot be used if Hikorogari Dantanshi is present on both the row and column.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to shorten the time required for a die sort test that involves determining redundancy relief in a memory such as an EPROM that requires a long time to write.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention has a plurality of word lines in addition to the word lines of the memory cell array, and this word line is connected to the gate? The semiconductor memory is characterized in that it includes a mask ROM in which drains of connected transistors are connected to bit lines of the memory cell array. That is, in the present invention, a mask ROM is provided on the bit line of a memory cell array. The defect of the bit line is determined based on whether an output corresponding to a pattern set by a mask can be obtained from the bit line.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a circuit diagram showing the main part of the same embodiment.
Since this is an example of correspondence with the one shown in the figure, corresponding parts will be given the same reference numerals as appropriate and the explanation will be omitted, and the characteristic points will be explained. The feature of this embodiment is that the memory cell array 1
1, a mask ROM31 for defect detection is provided. MOS transistors 21■-2, 21■-. ...,
21,-,2L-a-... has the following configuration. That is, the first row transistor 21■1. 21■1,
...is every other bit line? contact is made with the second row transistors 212-. , 21
■1, . . ., contacts with the drain are made every l bit lines different from the above, and the mask ROM31
The word line a in the first row connects the gates of the transistors in the first row, and the word line a in the second row, @b
The gates of the transistors in the second row are connected together, and the sources of these transistors are grounded. Note that this mask ROM31 has a structure in which cell transistors are provided for every other bit line in each row, but in the actual IC manufacturing structure, each bit line and word line a, All transistors are arranged near each intersection of b, but in the parts where no transistor is drawn at the intersection, there is no contact between the drain and the bit line, and it is the same even if there is no transistor, so the diagram is not shown. This is something that has not been done yet. In FIG. 1, when word line a is selected, if the bit lines are switched from the left, the potential of this bit line will be high level, low level, ? from the left. Low level, low level... howl. This is an EPROM on this word line a.
This is equivalent to connecting the l O l cell, 11' cell, '0' cell, 11' cell, etc., and the output is
I, r1+, tQT, #ll... The opposite is true for word line b.

If there is no defect from the sense amplifier to the end of the bit line, the mask ROM 31 can be read normally as described above. However, if the bit line is short-circuited to the ground midway, as shown in bit line 13■ in the middle of Figure 2 (point 51 in the figure), word line b and bit line l
If you select 3■, data 11' will be output. In addition, as shown in Figure 3, if the bit lines 13■, l3, are short-circuited (point 52 in the figure), when word line a and bit line 13■ are selected, the bit line 131 is connected to the ground by the transistor 2lA2. In order to short to 11'
The data will be read. Similarly, Il+ data is read from bit line ■3■. In other words, the repeating data pattern of r11,10+ cannot be obtained. Furthermore, do you sense the mask ROM 31 as shown in Figure 4? If it is provided at the end opposite to the amplifier, the data on the focus line 132 will always be 10' if the bit line 132 is broken in the middle (point 53 in the figure).

The selection of the mask ROM word line described above may be performed, for example, as shown in FIG. Here, V is placed at address A2. . (V cc + V th or higher)
This test circuit starts operating when address A is supplied. The two word lines a and b are switched. Of course, a circuit in which a dummy pad is provided for switching control is also possible.

As described in the above embodiment, if the mask ROM has two word lines in addition to the original memory cell array, many column-related defects can be detected by reading this. In particular, in EPROMs, defects that cause data 'O' (data written state) to become '1' cannot usually be detected unless non-volatile writing is performed. The invention is valid. By the way, let's think about redundancy. Two word lines are read from the mask ROM using the circuit of the present invention, and the defective memory is stored in some way. If the number of defective power rams is greater than the number of redundancy power rams, the test is terminated here, and the product is determined to be defective as it cannot be repaired. If it can be rescued by column redundancy, replace it with a redundant RAM or mask this column and perform a normal test. By doing so, the memory test time can be significantly shortened.

The present invention is particularly effective for memories that have redundancy in both columns and rows. This is because testing becomes difficult especially when there is redundancy in both columns and rows, so testing is facilitated by easily detecting column system defects.

[Effect of the invention] As explained above, according to the present invention, l\ff'
IM. It is possible to provide a semiconductor memory that has the advantage of being able to significantly reduce compression.

[Brief explanation of the drawing]

? Fig. 1 is a circuit diagram showing an embodiment of the present invention, Figs. 2 to 4 are circuit diagrams showing the defect detection operation of the same circuit, Fig. 5 is a partial detailed circuit diagram of the same circuit, Fig. 6, FIG. 7 is an explanatory diagram of a memory with dundancy, and FIG. 8 is a typical EPROM circuit diagram. 1l...Memory cell array, 13■, Engineering 32...Bit line, 3l...Mask ROM. a, b...Mask R
OM word line.

Claims (4)

[Claims] (1) In addition to word lines of a memory cell array configured by memory cells selected by normal read operations, the memory cell array has multiple word lines, has means for selecting these, and together with these, bit lines that configure the cell array. 1. A semiconductor memory characterized in that it is configured to obtain a specific output corresponding to a selection of a combination of word lines and bit lines by controlling the combination of word lines and bit lines. (2) As a means of obtaining a specific output corresponding to the combination of word lines and bit lines, there is a MOS whose gate is connected to the word line and drain is connected to the bit line at the intersection of the word line and bit line.
2. The semiconductor memory according to claim 1, wherein the transistors are selectively arranged by connecting drains and bit lines. (3) In each of the above word lines, the signals outputted to the outside by selecting this and each bit line are different from each other in physically adjacent bit lines and word lines. Claim 1 or 2
The semiconductor memory described in . (4) The semiconductor memory according to claim 1, wherein the memory cell array is an EPROM cell array.