JPH028554Y2 - - Google Patents
Info
- Publication number
- JPH028554Y2 JPH028554Y2 JP11834783U JP11834783U JPH028554Y2 JP H028554 Y2 JPH028554 Y2 JP H028554Y2 JP 11834783 U JP11834783 U JP 11834783U JP 11834783 U JP11834783 U JP 11834783U JP H028554 Y2 JPH028554 Y2 JP H028554Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- tap
- power supply
- capacitor
- supply circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000004804 winding Methods 0.000 claims description 10
- 238000009499 grossing Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
Description
【考案の詳細な説明】
この考案は電源回路の改良に関し、電源回路に
おけるコンデンサー充電電流の高調波成分による
S/N比の劣化を防止することを目的とするもの
である。[Detailed Description of the Invention] This invention relates to the improvement of a power supply circuit, and its purpose is to prevent deterioration of the S/N ratio due to harmonic components of a capacitor charging current in the power supply circuit.
従来第1図に示すダイオード蓄積電荷吸収コン
デンC1は100KHz以上の電磁板の吸収を目的とす
るものであつた。 Conventionally, the diode accumulated charge absorbing capacitor C1 shown in FIG. 1 was intended to absorb electromagnetic plates of 100 KHz or higher.
なお第1図において1は電源トランス、D1,
D2は順方向及び逆方向ダイオード、C2は平滑コ
ンデンサーであり、端子aに正の直流電圧が、端
子bに負の直流電圧が得られる。 In Fig. 1, 1 is a power transformer, D 1 ,
D 2 is a forward and reverse diode, C 2 is a smoothing capacitor, and a positive DC voltage is obtained at terminal a and a negative DC voltage is obtained at terminal b.
上記構成においてC1は前述のごとく100KHz以
上の電磁波吸収を目的とするものであるが、一方
整流回路(ダイオードD1及びD2)の出力電流波
形はダイオードD1,D2の導通時のみ流れるパル
ス性波形を有するのでオーデイオ周波数帯である
120Hz(入力交流数波数が60Hzの場合)以上の高
周波成分による増幅回路のS/N劣化を抑制する
には効果が充分でなかつた。 In the above configuration, C 1 is intended to absorb electromagnetic waves of 100KHz or higher as mentioned above, but on the other hand, the output current waveform of the rectifier circuit (diodes D 1 and D 2 ) flows only when diodes D 1 and D 2 are conductive. It is an audio frequency band because it has a pulsed waveform.
The effect was not sufficient to suppress S/N deterioration of the amplifier circuit due to high frequency components of 120 Hz (when the input AC wave number is 60 Hz) or higher.
そこで、この考案では電源トランス1の2次巻
線のインダクタンスを利用してコンデンサーとの
フイルター回路を構成することにより、前記整流
電流の高調波成分を除去するものであり、以下実
施例について実に詳しく説明する。 Therefore, in this invention, the harmonic components of the rectified current are removed by constructing a filter circuit with a capacitor using the inductance of the secondary winding of the power transformer 1.Example will be explained in detail below. explain.
第2図はこの考案の第1の実施例回路であつて
1は電源トランス、D1,D2はダイオード、C2は
平滑コンデンサー、aは+直流出力端、bは−直
流出力端である。 Figure 2 shows the first embodiment circuit of this invention, in which 1 is a power transformer, D 1 and D 2 are diodes, C 2 is a smoothing capacitor, a is a + DC output end, and b is a - DC output end. .
電源トランス1の2次巻線1bの中間タツプd
はコンデンサーC2の共通接続端に接続されてい
る。上記構成は第1図に示す従来例と同一構成で
ある。 Intermediate tap d of secondary winding 1b of power transformer 1
is connected to the common connection end of capacitor C 2 . The above configuration is the same as the conventional example shown in FIG.
C3(0.22μF)は2次巻線1bの巻始め端cと中
間タツプd、中間タツプdと巻終り端e間にそれ
ぞれ形成したタツプf・g間に接続したコンデン
サーである。 C 3 (0.22 μF) is a capacitor connected between taps f and g formed between the winding start end c and the intermediate tap d, and between the intermediate tap d and the winding end e, respectively, of the secondary winding 1b.
このような回路構成における等価回路は第4図
に示すごとく電源トランスのインダクタンスとコ
ンデンサーC3によりローパスフイルターが形成
される。なおRは負荷である。 In the equivalent circuit of such a circuit configuration, as shown in FIG. 4, a low-pass filter is formed by the inductance of the power transformer and the capacitor C3 . Note that R is the load.
したがつてローパスフイルターの減衰特性によ
り前記高調波成分が減衰されるようにタツプf、
gの取出し位置及びコンデンサーの値を選定する
ことにより、ノイズを抑制することができる。 Therefore, tap f is applied so that the harmonic components are attenuated by the attenuation characteristics of the low-pass filter.
Noise can be suppressed by selecting the extraction position of g and the value of the capacitor.
第3図は第2の実施例であつてタツプfと中間
タツプd、タツプgと中間タツプdとの間にそれ
ぞれコンデンサーC4(0.47μF)、C4(0.47μF)を接
続した構成で、その等価回路は第5図のごとく示
され、同様の作用によりノイズの抑制効果が得ら
れるものである。 FIG. 3 shows the second embodiment, in which capacitors C 4 (0.47 μF) and C 4 (0.47 μF) are connected between tap f and intermediate tap d, and between tap g and intermediate tap d, respectively. The equivalent circuit is shown in FIG. 5, and a noise suppressing effect can be obtained by the same action.
以上に説明したように、この考案は少なくとも
電源トランスと、整流回路、平滑回路よりなる電
源回路において、前記電源トランスの2次巻線に
タツプを形成し、当該タツプに接続したコンデン
サーと前記2次巻線のインダクタンスとでフイル
ターを構成したことを特徴とするもので、整流電
流の高調波を除去し、増幅器のS/Nを向上せし
める効果を有するものである。 As explained above, in a power supply circuit consisting of at least a power transformer, a rectifier circuit, and a smoothing circuit, a tap is formed in the secondary winding of the power transformer, and a capacitor connected to the tap is connected to the secondary winding. It is characterized by forming a filter with the inductance of the winding, and has the effect of removing harmonics of the rectified current and improving the S/N ratio of the amplifier.
なお、この考案を正及び負の直流電圧が得られ
る電源回路について述べたが、正又は負のみの出
力が得られる電源回路においても適用できること
は明らかである。 Although this invention has been described with respect to a power supply circuit that can obtain positive and negative DC voltages, it is clear that it can also be applied to a power supply circuit that can obtain only positive or negative outputs.
第1図は従来の電源回路の配線図、第2図およ
び第3図はそれぞれこの考案実施例の電源回路の
配線図、第4図及び第5図はそれぞれ第2図およ
び第3図の等価回路図である。
Figure 1 is a wiring diagram of a conventional power supply circuit, Figures 2 and 3 are wiring diagrams of a power supply circuit according to an embodiment of this invention, and Figures 4 and 5 are equivalent to Figures 2 and 3, respectively. It is a circuit diagram.
Claims (1)
を有する電源回路において、前記電源トランスの
2次巻線にタツプを形成し、当該タツプに接続し
たコンデンサーと前記2次巻線のインダクタンス
によるフイルター回路を構成したことを特徴とす
る電源回路。 In a power supply circuit having at least a power transformer, a rectifier circuit, and a smoothing circuit, a tap is formed in the secondary winding of the power transformer, and a filter circuit is formed by a capacitor connected to the tap and the inductance of the secondary winding. A power supply circuit featuring:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11834783U JPS6028488U (en) | 1983-07-28 | 1983-07-28 | power circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11834783U JPS6028488U (en) | 1983-07-28 | 1983-07-28 | power circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6028488U JPS6028488U (en) | 1985-02-26 |
JPH028554Y2 true JPH028554Y2 (en) | 1990-02-28 |
Family
ID=30272053
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11834783U Granted JPS6028488U (en) | 1983-07-28 | 1983-07-28 | power circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6028488U (en) |
-
1983
- 1983-07-28 JP JP11834783U patent/JPS6028488U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6028488U (en) | 1985-02-26 |
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