JPH0284807A - Digital signal processor - Google Patents

Abstract

PURPOSE:To accelerate a product sum processing required for filter operation and to improve processing capacity by constituting a data RAM of a dual board RAM, and providing a bypass signal line which performs the linear transfer of data without interposing a bus between two boards of the data RAM. CONSTITUTION:The data DRAM which stores sampling data, etc., transiently and the data DROM which stores the fixed data of a filter coefficient, etc., are contained in a digital signal processor. Also, a readout board RP and a write board WP are provided at the DRAM, and the address of the board RP is designated by a readout address pointer RAP. Also, the address of the board WP is designated by a write address pointer WAP, and the sampling data X1, etc., read out from the readout RP of the DRAM is supplied to either a multiplier circuit MULT or an arithmetic and logic unit ALU via a Y-BUS. Also, the data is transmitted to the board WP via a bypass signal path BP under the condition that the product sum processing required for the filter operation is performed.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to a digital signal processing device,
For example, the present invention relates to a technique that is particularly effective when used in a digital signal processing device having a product-sum calculation function required to equivalently realize a digital filter.

[Conventional technology]

There is a digital signal processing device that has a product-sum operation function necessary for so-called filter operation and calculation to equivalently realize a digital filter. This digital signal processing device employs a stored program method using microprograms, and uses an infrastructural program R that stores microinstructions.
OM (read-only memory), data ROM and data RAM (random memory) that store calculation data, etc.
Built-in access memory).

Regarding the digital signal processing device having the product-sum operation function, for example, Hitachi Digital Signal Processor () (SP) HO218 published by Hitachi, September 1985.
10 User's Manual 1.

[Problem to be solved by the invention]

FIG. 4 shows a partial block diagram of the digital signal processing device described above.

Further, FIG. 5 shows a processing flow diagram when, for example, a transversal type digital filter is equivalently realized in the digital signal processing device of FIG. 4.

In FIG. 4, sampling data x1 to Xn formed by sampling an input analog signal at a predetermined period and digitally encoding the data are
It is stored in the corresponding address of AM (DRAM).

These sampling data are sampling data
1 is read out sequentially from the data RAM, and the data RO
The multiplication result (product) by the 0 multiplier circuit MυLT is input to the multiplier circuit MULT together with the filter coefficient CI read from the corresponding address of M (DROM), and is further input to the arithmetic logic circuit ALU, and is input to the arithmetic logic circuit ALU.
A and ACCB output signals, that is, the arithmetic logic circuit ALU
is added to the previous addition result (sum).

On the other hand, the sampling data X1 read from the data RAM is stored in a delay register D having a two-stage latch configuration.
After being held for one machine cycle by REG and reading the next sampling data Xi+1,
The address is input to AI+1. As a result, the sampling data Xl-Xn are delayed by substantially one sampling period and sequentially shifted within the data RAM.

In this way, by sequentially inputting the sampling data Xi and the filter coefficient Ck to the multiplier circuit MULT, and sequentially shifting the sampling data X1 within the data RAM, Qn-ΣX1 necessary for the filter operation shown in FIG. -Ci -i product-sum calculation processing is performed to realize an equivalent digital filter.

However, the inventors of the present application have discovered that the digital signal processing device described above has the following problems. That is, in the digital signal processing device described above, the data RAM is constituted by a single baud RAM. Therefore, the sampling data Xl held in the delay register DREG is written to the address Ai÷1 after the read operation of the next sampling data X1+1 is completed. At this time, in the data RAM, read and write operations must be performed in a time-sharing manner within one memory cycle.
This increases the access time as an AM, and limits the speeding up of the machine cycle of the digital signal processing device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital signal processing device that increases the speed of machine cycles.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, the data RAM of the digital signal processing device is configured with a dual-baud RAM, and the data RAM is further configured with a dual-baud RAM.
A bypass signal path is provided between two ports of M for data transfer without going through a bus. Then, in the process of product-sum calculation processing necessary for filter calculation, data RA
The sampling data read from a predetermined address of M is transmitted to the bus and simultaneously written to the next address to be shifted in the data RAM.

[For production]

According to the above-mentioned means, it is possible to simultaneously perform the reading operation of the sampling data necessary for the product-sum operation processing and the write operation necessary for shifting the data in one memory cycle, thereby reducing the machine cycle of the digital signal processing device. It can be made faster.

(Embodiment) FIG. 1 shows a block diagram of an embodiment of a digital signal processing device to which the present invention is applied. The circuit elements constituting each circuit block in the figure are formed on a single semiconductor substrate such as single-crystal silicon, although not particularly limited, by known semiconductor integrated circuit manufacturing techniques.

The digital signal processing device of this embodiment is, although not particularly limited to, a stored program type signal processing device using a microprogram, and its operation is controlled by microinstructions stored in an intra-system ROM (I ROM). be done.

The digital signal processing device of this embodiment also includes, although not limited to, a data RAM (DRAM) that temporarily stores sampling data, etc., and a data ROM (DROM) that stores fixed data such as filter coefficients. In this embodiment, the data RAM is constituted by a dual port RAM, the two ports of which are dedicated as a read port (RP) and a write port (WP), respectively, but not limited thereto. Furthermore, a bypass signal path BP for directly transferring sampling data is provided between the read port RP and the write port WP.

In FIG. 1, the data RAM includes, but is not particularly limited to, a read port RP and a write port WP. Among these, the address of the read port) RP is specified by the read address pointer RAP, and the address of the write port) WP is specified by the write address pointer WAP.
specified by. Although not particularly limited, these address pointers have a count-up function that autonomously increments their contents, and their initial value is set to the data bus D-
Set via Bus.

The sampling data x1 and the like read from the read port RP of the data RAM are supplied to one input terminal of the multiplication circuit MULT or the arithmetic logic circuit ALU via the Y-Bus, although this is not particularly limited. In addition, on the condition that the digital signal processing device performs the product-sum calculation processing necessary for filter calculation, the bypass signal path B
Its write port is communicated to WP via P. Normal write data to the data RAM is supplied to its write port WP via the data bus D-BUS. The read ports (RP) and write ports (WP) of the data RAM can independently and simultaneously execute read operations and write operations to arbitrary addresses, respectively.

The data ROM is constituted by a read-only memory such as a mask ROM, although it is not particularly limited, and its address is specified by a ROM address pointer ROP. R
Like the read address pointer RAP and write address pointer WAP, the OM address pointer ROP has a count-up function that autonomously increments its contents, and its initial value is set via the data bus D-BUS. be done.

The filter coefficient 01 etc. read from the data ROM is
Although not particularly limited, it is supplied to the other input terminal of the multiplication circuit MULT or the arithmetic logic circuit ALυ via the X-Bus.

Although not particularly limited, the Y-BUS also has four
The output terminals of word general-purpose registers GRO-GR3 are coupled. These general-purpose registers GRO-GR3 are used as working registers, and their input terminals are coupled to the data bus D-BUS.

As mentioned above, one input terminal of the multiplication circuit MULT is supplied with the sampling data Xt outputted from the data RAM via the Y-Bus, and the other input terminal is supplied with the X bus - Via BUS,
0 to which filter coefficients Ct etc. output from OM are supplied.
The multiplication circuit MULT performs multiplication processing on these sampling data and filter coefficients, and supplies the result to one input terminal of the arithmetic logic circuit ALU.

As described above, the multiplication result of the multiplication circuit MULT is supplied to one input terminal of the arithmetic logic circuit ALU. Depending on the content of the calculation, read data from the data RAM may be directly supplied to this input terminal. Arithmetic logic circuit A
The other input terminal of the LU is connected via the data bus D-BUS to the accreditor ACCA-, although this is not particularly limited.
The output signal of ACCB is provided. When the sum-of-products calculation process necessary for the filter calculation is performed in the digital signal processing device, the output signals of the space statement generators ACCA and ACCB are the results of the sum-of-products calculations up to the previous time. Depending on the content of the calculation, read data from the data ROM may be directly supplied to the input terminal. The arithmetic logic circuit ALU performs various arithmetic processing such as addition between these two sets of data, and sends the results to the akiminirators ACCA and ACCB.

In other words, the multiplication circuit MULT and the arithmetic logic circuit ALU are
Sampling data X1 and filter coefficients Ct are sequentially output from the data RAM and data ROM, and the results of previous calculations are sequentially fed back from the accumulators ACCA and ACCB, thereby performing a product-sum operation to equivalently realize a digital filter. It has the ability to execute processing in steps.

Although the instruction ROM is not particularly limited, it is configured by a programmable ROM, and its address is:
t1 is determined by the program counter PCC. The program counter PCC has a count amplifier function that autonomously increments its contents, and its initial value is set via the data bus D-Bus.

Microinstructions read from the instruction ROM are supplied to and held in the instruction register IN5R, although not particularly limited thereto. These My First Commands are supplied to the control circuit CTL, and some of them are supplied directly to corresponding circuits of the digital signal processing device.

The control circuit CTL has an instruction register IN5.
By receiving a predetermined portion of microinstructions held in R and decoding it, timing signals required by each circuit of the digital signal processing device are formed. As a result, each circuit of the digital signal processing device executes a predetermined operation according to the microinstruction. The control circuit CTL receives a chip selection signal C supplied as a control signal from the outside.
D, read/write signal R/W and function code signal FO
~F3 etc., control input/output operations for various registers, pointers, etc.

The digital signal processing device inputs and outputs data in parallel to an external device via an input register IR or an output register OR, and also inputs and outputs data to an external device via a serial input register SIR and a serial output register SOR, although it is not particularly limited. It has the function of inputting and outputting data to and from the device serially.

The input register IR is connected to the external bus E-Bu from an external device.
It receives input data supplied in parallel through the data input/output lines DO to D15 and data buffers DBH and DEL of s, holds it, and transmits it to the internal data bus D-Bus. Further, the output register OR receives and holds output data supplied via the internal data bus D-BUS, and also outputs data from the data buffers DBH and DBL and the data input/output lines DO to D15 of the external bus E-BUS. to an external device in parallel. On the other hand, the serial input register 310 is connected to the serial input line Sl of the external bus E-BUS from an external device.
Input data serially supplied via the D-BUS is sequentially captured in accordance with a clock signal (not shown) and transmitted in parallel to an internal data bus D-BUS. Further, the serial output register SOR takes in and holds output data supplied in parallel via the internal data bus D-BUS, and also outputs the output data serially to the serial output line of the external bus E-BUS according to a clock signal (not shown). S
Send from o.

FIG. 3 shows a processing flow diagram of one embodiment of the product-sum operation processing performed when a transversal type digital filter is equivalently realized by the digital signal processing device of FIG. 1. Further, FIG. 2 partially shows a timing diagram of an embodiment in which the above-described sum-of-products calculation process is performed in the digital signal processing device of FIG. 1. According to these figures, an overview and characteristics of the product-sum calculation process of the digital signal processing device of this embodiment will be explained.

In FIG. 3, sampling data input from the input node In every sampling period is shifted via a delay element every sampling period, and becomes sampling data X1 to Xn of each node. These sampling data are multiplied by the corresponding filter coefficients 01 to Cn, and then these multiplication results are sequentially added to obtain the calculation output Q in the sampling period.
n is obtained.

In the digital signal processing device, sampling data X1 to Xn sampled and digitally encoded by an A/D conversion circuit (not shown) are first sequentially stored in corresponding addresses of a data RAM. Filter coefficient 01
~Cn is when manufacturing the digital signal processing device,
It is preset to the corresponding address of the data ROM.

In the digital signal processing device of this embodiment, the direction of processing is sequentially performed from the first stored sampling data Xn to the data RAM and data assigned to the sampling data x1 to Xn and filter coefficients C1 to Cn. The address of the ROM is not particularly limited, but a larger address is given one by one according to the direction of this processing. Therefore, in each calculation step, the sampling data X(AI) read from the address Ai of the data RAM is the filter coefficient C(AI) read from the corresponding address At of the data ROM.
At the same time, the data R
It is written to the address AO-1 immediately before AM and is equivalently delayed. Although this processing direction is different from the processing flow diagram of FIG. 5 above, the obtained results are essentially the same.

The product-sum calculation process in each sampling period is performed using the read address pointer RAP, write address pointer W
It begins by setting initial address values to the AP and ROM address pointers ROP. At this time, read address pointer RAP and ROM address pointer R
The initial address value of OP is logically the same address, and the initial address value of write address pointer WAP is substantially the address immediately before the initial address value set in read address pointer RAP.

As described above, these addresses are counted up autonomously by each address pointer as the product-sum calculation process progresses. This count amplifier processing sequentially updates the addresses of the data RAM and data ROM, and the processing flow shown in FIG. 3 automatically proceeds.

As shown in FIG. 2, the read address pointer R
AP and ROM address pointer ROP count value is A1
, and the value of write address pointer WAP is A1-
1, in the digital signal processing device, the sampling data X (Ak) corresponding to the address Ai is read from the read board ()RP of the data RAM, and is sent to one side of the multiplication circuit MULT via the Y bus Y-BUS. is input to the input terminal of At the same time, the filter coefficient C (Al) is read from the corresponding address of the data ROM, and is sent to the multiplier circuit MULT via the X bus X-BtJS.
is input to the other input terminal of

These sampling data X(At) and filter coefficient C(At) are subjected to multiplication processing by a multiplication circuit MULT, and then the result of the calculation is input to one input terminal of the arithmetic logic circuit ALU.

The contents of the accumulators ACCA and ACCB, that is, the results of the previous product-sum operations are input to the other input terminal of the arithmetic logic circuit ALU. The arithmetic logic circuit ALυ further adds the sampling data X (Ai) of this node, the multiplication result by the filter coefficient C (At), and the result of the previous product-sum operation, and sends the result to the accumulators ACCA and ACCI3 again. input.

On the other hand, the sampling data X (Al) output from the protruding port RP of the data RAM is
At the same time, it is supplied to the multiplier circuit MULT via us.
It is transmitted to the write port WP of the data RAM via the bypass signal path BP. As described above, the write port WP is supplied with the address A1-1 from the write address pointer WAP. Therefore, the sampling data X(Al) is changed to the data R at a predetermined timing.
It is input to AM address Al-1. Needless to say, this write operation is performed in parallel with the read operation of the sampling data X(At) by the read port RP. In other words, sampling data X (AI)
The read operation and the write operation of read sampling data X(AI) to address At-1 are executed simultaneously in one memory cycle of the data RAM.

In this way, the reading operation of sampling data and filter coefficients, their product-sum operation, and the writing operation of the read sampling data to the next address are performed from the previously sampled sampling data Xn to the last sampled data as the address is updated. By sequentially repeating up to the sampled data x1, equivalently, QnmΣxi-ci 1maro! Filter calculations are performed for l sampling periods,
A processing flow equivalent to that of FIG. 3 or FIG. 5 is realized.

The filter calculation shown in the above equation is repeatedly executed at each sampling period, and the signal data formed as a result of the calculation process is sent to the data input/output line Do-D15 of the external bus E-BUS or the serial output terminal SO. output to the outside via.

As a result, the digital signal processing device of this embodiment is
It functions equivalently as, for example, a transversal digital filter.

As described above, the digital signal processing device of this embodiment includes a multiplication circuit MtJLT, an arithmetic logic circuit ALU, a data RAM, and a data ROM, and has a product-sum operation function for equivalently realizing a digital filter. In an embodiment, the data RAM is a dual port) R
configured by AM and has two dedicated ports, namely a read port RP and a write port WP,
In addition, these read port RP and write port
) WP is provided with a bypass signal path BP for directly transferring sampling data without going through an internal bus. For these reasons, in the digital signal processing device of this embodiment, the read operation of the data RAM required for the product-sum calculation process and the write operation of the data RAM required for the shift process of sampling data are performed by the data RAM. They are executed simultaneously in one memory cycle. In other words, in data RAM, the write address decoding process, the read address decoding process, and the read and write operations performed at each port are performed substantially in parallel, and the required time is the same as in the past. This is significantly shortened compared to the case where the data RAM read cycle and write cycle are performed separately. Furthermore, in the case of this embodiment, arithmetic processing is performed sequentially from the sampled data captured first in time, thereby eliminating the need for data holding means such as delay registers, thereby reducing the amount of hardware in the digital signal processing device. It is possible to aim for reductions as well.

As shown in the above embodiment, when the present invention is applied to a digital signal processing device having a product-sum calculation function for filter calculation, the following effects can be obtained. In other words, (1) The data RAM of the digital signal processing device is configured with a dual-port RAM, and a bypass signal path is provided between the two ports of the data RAM to directly transfer data without going through a bus. By performing arithmetic processing on the sampled data in order, the read operation of the sampling data necessary for the product-sum operation processing and the operation of writing the read sampling data to the next address can be executed in a short machine cycle. can get.

(2) In item 11) above, by dedicating the two access ports provided in the RAM as a read port and a write port, the configuration of each port can be simplified and the amount of hardware can be reduced. can get.

(3) According to the above item (1), there is no need to provide a delay register or the like for buffering sampling data, so it is possible to reduce the amount of hardware of the digital signal processing device.

(4) According to the above item (1), the read processing and the write processing of the data RAM can be performed simultaneously within one machine cycle, so that the number of dynamic steps of the digital signal processing device can be reduced.

(5) According to the above item (1), by using a dual-port RAM as the data RAM, it is possible to achieve the effect of speeding up the arithmetic processing other than the product-sum arithmetic processing of the digital signal processing device.

(6) Items (1) to (5) above have the effect of speeding up the product-sum calculation processing necessary for filter calculation, and increasing the processing capacity of the digital signal processing device and reducing its cost. is obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIG. 1, the data RAM of the digital signal processing device has two ports: a read port RP and a write port W.
The bypass signal path BP provided between the read port RP and the write port WP does not need to be dedicated as a port P, and may have three or more access ports. The internal bus configuration of the digital signal processing device, which may be formed by
The write address pointer WAP, which is not limited to this embodiment, can give an address relatively based on the count value of the read address pointer RAP, so for example, it can be replaced with a minus 1 circuit that subtracts 1 from the count value. You can also do that. In FIG. 2, read port RP and write port WP in each memory cycle.
Various embodiments can be considered for the operation timing. In FIG. 3, the address of the data RAM may be assigned a younger address in order from the last sampled data XI, and arithmetic processing may be performed while counting down the address. Letting the count value be At, the count value of the write address pointer WAP will be AI+1. Similar effects can be achieved by using a memory having two access ports and two memory clots instead of a dual port RAM that shares a memory mat as a data RAM having multiple access ports. In this case, each port is limited to reading and writing,
It is necessary to adopt a configuration in which data from two chronologically shifted sampling periods can be simultaneously read and written by performing page restriction that alternately switches the memory cloaks connected to this for each sampling period. Furthermore, the block configuration of the digital signal processing device shown in FIG. 1 can take various embodiments.

In the above explanation, the invention made by the present inventor was mainly applied to a digital signal processing device having a product-sum operation function necessary for filter operation, which is the field of application for which the invention was made, but the invention is limited thereto. (For example, a chip-type codec (CODEC) that includes such a digital signal processing device.
der-Decoder) and modems (MODEMs modems), etc. The present invention is widely applicable to digital signal processing devices having a product-sum operation function that involves at least shift processing, and digital devices including such digital signal processing devices. It can be used.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the data RAM of the digital signal processing device
is configured with a dual-port RAM, and by providing a bypass signal path for direct data transfer between the two ports of the data RAM, it is possible to read out the sampling data necessary for the product-sum calculation process. The write operation of the read sampling data to the adjacent address can be executed simultaneously within one memory cycle without providing a means to hold the sampling data.This speeds up the product-sum operation processing required for filter operation. At the same time, it is possible to improve the processing capacity of the digital signal processing device and reduce its cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a digital signal processing device to which the present invention is applied, FIG. 2 is a timing diagram showing an embodiment of the digital signal processing device of FIG. 1, and FIG. , FIG. 4 is a partial block diagram showing an example of a conventional digital signal processing device, and FIG. FIG. 3 is a processing flow diagram showing an example of filter calculation of the digital signal processing device shown in the figure. DRAM...Data RAM5RP...Read hold, WP...Write port, BP...Bypass signal path, DROM...Data ROM5 lROM...
・Instruction, RAP...Read address pointer, WAP...Write address pointer, R
OP...ROM address pointer, GRO~GR3.
・・General-purpose register, MULT・Multiplication circuit, ALU・
・・Arithmetic logic circuit, ACCA, ACCB・Accumulator, FCC・Program counter, lN5R・
...Instruction register, CT'L...Control circuit, IR...Input register, OR...Output register, DBH, DBL...Data buffer, S, IR...
...Serial input register, SOR...Serial output register, D-BLIS...Data bus, X-BUS
...X bus, Y-BUS...Y bus, E-BUS
...External bus. DREG...Delay register. 41st

Claims (1)

Claims: 1. A digital signal processing device comprising a data RAM having a plurality of access ports. 2. The above data RAM is composed of a dual port RAM, and between one port and the other port, there is a
2. The digital signal processing device according to claim 1, further comprising a bypass signal path for data transfer without going through a bus. 3. One and the other ports of the data RAM are
When a sum-of-products operation is performed to equivalently realize a digital filter in the digital signal processing device,
Each of the ports is used as a read port for outputting sampling data from a predetermined address and a write port for inputting the sampling data output from the address to another address substantially adjacent to the address. 3. The digital signal processing device according to claim 1, wherein the sampling data is transmitted via the bypass signal path.