JPH02126650A - Manufacture of dielectric isolation semiconductor device - Google Patents

Abstract

PURPOSE:To effectively prevent the bottom of an element isolation groove from being side-etched and to obtain a semiconductor device whose isolation breakdown strength is high and whose reliability is high by a method wherein a silicon nitride film is used as an etching mask of the element isolation groove. CONSTITUTION:A silicon nitride film 25 (a second film) of 0.3mum is formed, by a CVD method, on the surface of an active layer of a united substrate; it is patterned and used as an etching mask; an anisotropic etching operation is executed by using an alkaline solution; a V-shaped groove 26, for element isolation use, reaching an oxide film 23 is formed. Then, a p<+> type layer 242 with a depth of about 3mum is formed on side faces of the V-shaped groove 26. Boron glass 27 formed on the side faces of the V-shaped groove 26 is etched and removed by using dilute hydrofluoric acid in such a way that an element- isolation dielectric film (a first insulating film) 23 is not excellent. The silicon nitride film 25 used as the mask is etched and removed by using hot phosphoric acid. Then, a thermal oxidation operation is executed; an oxide film (a third insulating film) 28 of 1mum is formed on the side faces of the V-shaped groove on the surface of the active layer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device using a dielectrically isolated semiconductor substrate obtained by bonding two substrates together.

(Prior Art) Conventionally, pn junction isolation and dielectric isolation have been known as element isolation methods for semiconductor devices. Dielectric separation method is pn
It has the following superior features compared to the junction separation method.

■Low leakage current even when operating at high temperatures.

■No latch-up due to parasitic thyristor.

■The area required for separating high-voltage elements is small.

■There is no need to consider the polarity of voltage application.

■Low parasitic capacitance.

Several methods are known for realizing a dielectric isolation structure. For example, there is a method of directly bonding a silicon substrate with an insulating film sandwiched between them, a method of vapor phase growth of silicon on a sapphire substrate called SO8, a method of depositing an amorphous silicon film on the insulating film and recrystallizing it. A method of etching a part of a silicon substrate to form an oxide film, depositing a polycrystalline silicon film, and polishing from the back side to obtain an island-shaped silicon layer supported by the polycrystalline silicon film.

Among these, direct bonding technology has recently attracted attention as a method that can easily obtain high-quality dielectrically isolated semiconductor substrates.

FIG. 2 shows the manufacturing process of a dielectric isolation substrate using a conventional direct bonding technique. As shown in (a), two silicon wafers 1.2 with mirror-polished surfaces to be bonded are prepared. One wafer 1 has an oxide film 3 on its surface as shown in the figure.
form 4. These two wafers 1 and 2 are directly bonded together to integrate them as shown in FIG. 3(b). Subsequently, the active layer side on which elements are to be formed, in this example the wafer 1 side, is polished to a predetermined thickness as shown in (C).

Next, a masking oxide film 5 is formed on the entire surface of this wafer, and the oxide film in the 7-shaped groove portion to be formed on the wafer 1 on the active layer side is selectively etched (d).

Next, the wafer 1 on the active layer side is selectively etched by anisotropic etching to form a separation groove 6 having a V-shaped cross section and having a depth that reaches the oxide film 4, as shown in FIG. For this,
Each element forming region is separated into islands. Thereafter, in order to further electrically isolate each island-shaped silicon layer, the mask oxide film 5 is removed by etching (f), and then an oxide film 7 is formed as shown in (g). Then, polycrystalline silicon 8 is buried in each isolation groove 6 and the surface is planarized as required to obtain a dielectric isolation substrate as shown in FIG.

Figure 3 shows a p
This shows a state in which an np transistor is formed. When the active layer is p-type, a pnp transistor is obtained by sequentially diffusing an n-type base layer 9 and a p-type emitter layer 10 here. pW at the interface between the island-shaped active layer and the oxide films 4 and 6.
Layers 8t and 8z are formed. These are for collecting the collector current to the collector electrode well, and the bottom p
The mold layer 81 is previously formed on the first substrate 1 before bonding,
The p-type layer 82 in the trench is formed by diffusion after the trench is formed.

However, in a semiconductor device using such a dielectric isolation substrate, conventional methods have the following problems with element isolation characteristics.

This will be explained using FIG. FIG. 4 specifically shows the step of forming the 7-shaped groove after integrating and adjusting the thickness of the active layer in the step of FIG. 2. Figure 4(a)
A thermal oxide film 11 is formed on the active layer, and using this as a mask, the active layer is etched by anisotropic etching.
This is a state in which the groove 5 is formed. Thereafter, as shown in FIG. 3B, impurities are diffused into the groove side surfaces using the oxide i11 as a diffusion mask to form a p+ type layer 88. Thereafter, the oxide film 11 used as a mask is removed by etching, and a high quality oxide film is again formed on the surface of the active layer and the element isolation trench by thermal oxidation. At this time, a hydrofluoric acid-based etching solution is usually used for etching the oxide film, but the oxide film 4 exposed at the bottom of the 7-shaped groove 5 is also etched at the same time, and as shown in FIG. occurs. Thereafter, when an oxide film 6 for element isolation is formed on the side surface of the 7-shaped groove 5, a state as shown in (d) is obtained. In this state where the notch 12 is formed at the bottom of the figure 7 groove, the oxide film thickness at this portion becomes thinner and the isolation withstand voltage becomes insufficient. Further, in the notch 12, the polycrystalline silicon film cannot be completely filled in in the later polycrystalline silicon film filling process, and a cavity is formed.
This causes a decrease in reliability of the device.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor device manufacturing process using a dielectric isolation substrate obtained by adhesive technology, in the lateral element isolation process using the figure 7 groove, it is difficult to improve the breakdown voltage and reliability. There was a problem with sexuality.

An object of the present invention is to provide a method for manufacturing a dielectrically isolated semiconductor device that solves these problems.

[Structure of the invention]

(Means for Solving the Problem) The method of the present invention involves bonding a first semiconductor substrate and a second semiconductor substrate together with a first insulating film (oxide film) serving as an element isolation dielectric film sandwiched therebetween. A second film for an etching mask is formed on the etched semiconductor substrate, and grooves for element isolation are formed using this film by etching).Then, the second film is removed to separate the devices into islands. A feature of the present invention is that a silicon nitride film is used as a second layer used as a mask for one-groove etching when forming desired elements in each active layer.

(Operation) According to the present invention, a silicon nitride film is used as an etching mask for device isolation trenches. When etching to remove the mask after etching the grooves, V
An etchant that does not etch the oxide film at the bottom of the trench can be used.

For example, phosphoric acid. This prevents side etching of the oxide film at the bottom of the trench, and when this trench is filled with polycrystalline silicon, no cavity remains, resulting in a highly reliable dielectrically isolated semiconductor device with sufficient isolation breakdown voltage. be able to.

(Example) The present invention will be explained in detail below.

p-type, resistivity 100Ω, scratches, plane orientation (100), thickness 5
A dielectric isolation substrate was fabricated by direct adhesion using a 00 μm silicon wafer. Prior to bonding, boron ion implantation and annealing were performed on one of the wafers, and an oxide film with a thickness of 1 μm was formed by thermal oxidation.

The specific process of direct adhesion is as follows. First, the wafer to be bonded is heated with H, SO, -H2O, mixed solution, HCl-H
20! After washing with a mixed solution, aqua regia, etc., it is washed with water for about 10 minutes, and dehydrated and dried using a spinner. The wafer that has undergone these treatments is placed in a clean atmosphere of, for example, class 100 or below, and its mirror-polished surfaces are brought into close contact with each other in a state where substantially no foreign matter is present. As a result, the two wafers are bonded with a certain degree of strength.

By heat-treating the bonded substrates in a diffusion furnace or the like, the adhesive strength is increased and the two wafers are completely integrated. Improvement in adhesive strength is observed by heat treatment at about 200° C. or higher. The heat treatment can be carried out in a particularly selected atmosphere of oxygen, nitrogen, hydrogen, inert gas, water vapor, or a mixture thereof. In this example, cleaning is performed quickly,
-H! 0. Mixed liquid and HCL-H! 0. A mixed solution was used, and the heat treatment was carried out at 1100° C. for 2 hours in nitrogen containing a small amount of oxygen.

After forming the dielectric isolation substrate by direct adhesion in this way,
The side that will become the active layer is polished to the required thickness of 50 mm as the active layer.
Adjusted to μm.

The subsequent steps are shown in Figure 1 (Fig.
This will be explained with reference to a) to (e). Reference numeral 21 denotes a first silicon wafer, which after bonding is adjusted to a predetermined thickness required as an active layer as described above.

22 is the second silicon wafer, the first wafer 2
A 1 μm oxide film (first film) by thermal oxidation is placed between 1 and 2.
3 is formed as an element isolation dielectric film. The bottom surface of the first silicon wafer 21 has a p-type layer 24. is formed by diffusion. A silicon nitride film 25 (second film) with a thickness of 0.3 μm is formed on the surface of the active layer of the integrated substrate by the CVD method, and this film is patterned and used as an etching ψ mask, and then etched with an alkaline solution. V-shaped groove 2 for element isolation reaching oxide film 23 through directional etching
6 ((a)). Next, a p-type layer 24 with a depth of approximately 3 μm is formed on the side surface of the V-shaped groove 26 ((b)).
.

The p-type layer 24z is formed, for example, by solid phase diffusion using polycrystalline silicon doped with boron.

At this time, the poron glass 27 formed on the side surface of the 7-shaped groove 26
is an element isolation dielectric film (first insulating film) 23 using dilute hydrofluoric acid.
Remove by etching to prevent corrosion ((C)).

Then, the silicon nitride film 25 used as a mask is removed by etching with hot phosphoric acid ((d)).

Next, thermal oxidation is performed to form a 1 μm oxide film (third insulating film).
28 is formed on the side surface of the V-shaped groove and the surface of the active layer ((e
) ). After this, although not shown, a polycrystalline silicon film is buried in the V-shaped groove 26, and a planarization process is performed as necessary to complete the dielectric isolation substrate. Desired elements are then formed in each of the island-shaped active layers according to a normal process. For example, by sequentially diffusing an NG layer and a p-type layer to form a pnp
Get a transistor.

According to this embodiment, a thin portion of the isolation insulating film is not formed at the bottom of the element isolation groove of the dielectric isolation substrate, and no cavity is left at the bottom of the groove after filling the polycrystalline silicon film as in the conventional case. In the conventional method, the dielectric breakdown voltage between the active layer and the polycrystalline silicon film in the figure 7 groove was 400 V even with a 1 μm oxide film, whereas in the example, a breakdown voltage of 5 oov was obtained. In addition, as a result of cutting and observing the board,
In the substrate according to this example, no cavity was observed within the 7-shaped groove.

In addition to the silicon nitride film, when a metal film that is not eroded by a hydrofluoric acid etchant is used as an etching mask for the element isolation trench, the same effect as that of the silicon nitride film can be obtained.

Although the embodiments of dielectrically separated substrates using direct adhesion have been described above, the present invention is applicable to dielectrically separated substrates using other adhesion methods, such as electrostatic adhesion or spin-on glass adhesion. It is possible to apply it to

〔Effect of the invention〕

As described above, according to the present invention, it is possible to effectively prevent side etching of the bottom of the isolation trench of a dielectric isolation substrate due to adhesive technology, and to obtain a highly reliable semiconductor device with a high isolation breakdown voltage.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are diagrams showing the manufacturing process of a dielectric isolation substrate according to an embodiment of the present invention, and FIGS. 2(a) to (h) are diagrams illustrating the conventional manufacturing process. Figure 3 shows how a transistor is formed on a dielectric isolation substrate, and Figure 4 shows how a transistor is formed on a dielectric isolation substrate.
a) to (d) are diagrams showing main steps for explaining the problems of the conventional method. 21... First silicon wafer, 22... Second silicon wafer, 23... Oxide film (first insulating film)
, 24... p+ type layer, 25... silicon nitride film (second
film), 26... figure 7 groove, 27... boron glass,
28... Oxide film (third film). Agent Patent Attorney Yudo Nori Chika Matsuyama Speed of Light Figure Figure Figure Figure Figure ~ Sai C'J

Claims (2)

[Claims] (1) a first silicon substrate on which a semiconductor element is formed;
A second silicon substrate that holds and serves as a stand is integrated with an oxide film, and the first silicon substrate is separated into a plurality of dielectric parts by grooves extending from the surface of the first silicon substrate to the oxide film. During the manufacturing process of the body isolation substrate, a silicon nitride film is formed on the surface of the first silicon substrate in the step of digging a trench that reaches the oxide film, and the silicon nitride film in the part where the trench is to be dug is selectively removed. A method for manufacturing a dielectrically isolated semiconductor device, characterized by digging a trench that reaches an oxide film by etching using a silicon film as a mask. (2) A first silicon substrate on which a semiconductor element is formed and a second silicon substrate that holds it and serves as a stand are integrated through an oxide film, and the first silicon substrate is connected to the first silicon substrate. A mask film is formed on the surface of the dielectric isolation substrate, which is separated into multiple parts by grooves reaching from the surface to the oxide film, and the patterned mask film is used to selectively etch and diffuse into the dielectric isolation substrate. A method for manufacturing a dielectrically isolated semiconductor device, comprising using silicon nitride as a mask film.