JPH0186725U - - Google Patents

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Publication number
JPH0186725U
JPH0186725U JP18270587U JP18270587U JPH0186725U JP H0186725 U JPH0186725 U JP H0186725U JP 18270587 U JP18270587 U JP 18270587U JP 18270587 U JP18270587 U JP 18270587U JP H0186725 U JPH0186725 U JP H0186725U
Authority
JP
Japan
Prior art keywords
switch
input circuit
digital signal
signal input
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18270587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18270587U priority Critical patent/JPH0186725U/ja
Publication of JPH0186725U publication Critical patent/JPH0186725U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2
図は実施例の動作説明のための波形図、第3図、
第4図及び第5図は従来の回路図である。 2……信号源スイツチ、5……フオトカプラ、
6……交流電源、7……整流回路、10……コン
デンサ、11……抵抗。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a waveform diagram for explaining the operation of the embodiment, FIG.
4 and 5 are conventional circuit diagrams. 2...Signal source switch, 5...Photocoupler,
6... AC power supply, 7... Rectifier circuit, 10... Capacitor, 11... Resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 交流電源から信号源スイツチを介して与えられ
る電圧を整流平滑して該スイツチのオン・オフに
一致するオン・オフ信号を取り込むデイジタル信
号入力回路において、前記スイツチからの電圧を
コンデンサと抵抗の並列回路で限流する構成にし
たことを特徴とするデイジタル信号入力回路。
In a digital signal input circuit that rectifies and smoothes a voltage applied from an AC power supply via a signal source switch and captures an on/off signal that corresponds to the on/off state of the switch, the voltage from the switch is connected to a parallel circuit of a capacitor and a resistor. A digital signal input circuit characterized by having a configuration in which current is limited by .
JP18270587U 1987-11-30 1987-11-30 Pending JPH0186725U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18270587U JPH0186725U (en) 1987-11-30 1987-11-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18270587U JPH0186725U (en) 1987-11-30 1987-11-30

Publications (1)

Publication Number Publication Date
JPH0186725U true JPH0186725U (en) 1989-06-08

Family

ID=31474149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18270587U Pending JPH0186725U (en) 1987-11-30 1987-11-30

Country Status (1)

Country Link
JP (1) JPH0186725U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008136316A (en) * 2006-11-29 2008-06-12 Daikin Ind Ltd Charging device and method for power supply unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008136316A (en) * 2006-11-29 2008-06-12 Daikin Ind Ltd Charging device and method for power supply unit

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