JPH01314445A - Parallel type frame synchronizing system - Google Patents

Abstract

PURPOSE:To execute separation without fail even concerning the high-order group signal of a high speed by detecting a frame synchronizing bit from a separated low-order group signal without considering a channel order and phase synchronization mutual between channels when a high-order group PCM signal is separated to the low-order group signal. CONSTITUTION:The high-order group signal is outputted as the parallel signal of four bits by a serial and parallel converting circuit 1. Then, since the high- order group signal is latched at the transmitting speed of the low-order group signal in a D flip-flop 21, the high-order group signal is separated to the low- order group signal of four channels. When only one of frame synchronizing pattern detecting circuits 31-34 detects a synchronizing bit pattern from the output of the D flip-flop 21 and the output of a D flip-flop 22, which is dislocated from the D flip flop 21 by one bit, the circuit sends a control signal to a channel exchange circuit 4 and phase synchronizing circuits 51-54. The channel exchange circuit 4 knows a signal arranging pattern by this control signal and the channels are rearranged to the regular order. One bit-dislocation between the channels is erased by the phase synchronizing circuits 51-54 and the bit phase synchronization is obtained to a frame format.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a frame synchronization method when separating PCM signals from high-order groups to low-order groups.

[Prior Art] FIG. 3 shows an example of a separation device using a conventionally known frame synchronization method.
This separates the CM signal into four low-order group signals. That is, the high-order group PCM signal enters the serial-to-parallel conversion circuit 21, and the 4 bits in series are converted into parallel signals and output. This conversion circuit 21 operates at a higher-order group transmission rate. The 4-bit signal is monitored by the synchronization code pattern detection section 22, and when a frame synchronization bit string is detected, a control signal is sent to the counter 23. 'The counter 23 sends a frame synchronization pulse to the frame synchronization circuit 24 in accordance with the control signal.

The frame synchronization circuit 24 latches the signal sent from the serial/parallel conversion circuit 21 at a low-order group transmission rate and converts it into 4-channel low-order group signals, but the low-order group signals are arranged in the normal channel order. A phase-adjusted frame synchronization pulse is sent from the counter 23 at the appropriate timing.

[Problems to be Solved by the Invention] However, in conventional devices of this type, the signal output from the serial-to-parallel conversion circuit to the frame synchronization circuit has a high-order group speed. This has the disadvantage that the operating speed cannot follow it.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a parallel frame synchronization system capable of separating high-speed, high-order group signals.

[Means for solving the problem 1] In the parallel frame synchronization method according to the present invention, a higher order group, P
When separating a CM signal into lower order group signals, the channels are This eliminates the bit phase shift between channels by rearranging them in the normal order.

[Function] According to the present invention, since the frame synchronization pattern detection circuit can be operated at the transmission speed of the low-order group signal, it is possible to reliably separate even high-speed high-order group signals.

[Example] Hereinafter, the present invention will be described in detail based on Examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, reference numeral 1 denotes a serial-to-parallel conversion circuit that converts a high-order group PCM signal into a 4-bit parallel signal, and operates at a high-order group transmission rate. 21 is a D flip-flop, which latches the signal sent from the serial/parallel conversion circuit 1 at a low-order group transmission rate. 22 is also a D flip-flop.

31 to 34 are frame synchronization pattern detection circuits, and D
The frame synchronization bit and the array pattern of channels 1 to 4 are detected from the output of the flip-flop 21 and the output of the D flip-flop 22 which is shifted by one bit.

Reference numeral 4 denotes a channel switching circuit, which performs a function of switching the channels in the normal order based on the detection signals from the frame synchronization pattern detection circuits 31 to 34.

Reference numerals 51 to 54 denote phase synchronization circuits, which function to eliminate a 1-bit phase shift between channels and achieve frame synchronization between channels.

According to the embodiment with the above-described configuration, the frame synchronization pattern detection circuits 31 to 34 can be operated at the transmission speed of the low-order group signals, so a high-speed separation device for high-order group signals can be realized. Since the channels are previously separated into lower-order groups, the order of the channels is not fixed.Here, the order of the channels is J ff as shown in FIG.
There are fi types of patterns. However, since the phase shift between each channel is determined by each pattern, this is
It is detected from the outputs of flip-flops 21 and 22.

For example, regarding pattern 3 (see FIG. 2), the low-order group signal #1 latched by the D flip-flop 21. #2. #3. Channels 3, 4, and 1.2 are arranged for #4, respectively. Also, since channel 1.2 is one bit ahead of channel 3.4, the synchronization bit of channel 3.4 is detected at detection point A, and the synchronization bit of channel 1.2 is detected at point B at the same time. Ru. Furthermore, if the synchronization bit pattern is set to an appropriate value (for example, 1100 or ooll), these 4fffiM patterns will not overlap.

The operation of this embodiment shown in FIG. 1 will be described in more detail as follows.

The high-order group signal is output as a 4-bit parallel signal by the serial/parallel conversion circuit 1, but the signal is still bit-shifted at the transmission speed of the high-order group signal. Then, by latching these signals in the D flip-flop 21 at the transmission speed of the low-order group signals, they are separated into four channels of low-order group signals.

However, since frame synchronization is not achieved, the order of the channels is undetermined at this stage. Therefore, as explained earlier, from the output of the D flip-flop 21 and the output of the D flip-flop 22 which is shifted by 1 bit,
The frame synchronization pattern detection circuits 31 to 34 are configured according to the low-order group signal arrangement of the pattern. Each element uses a matching circuit to detect the synchronization pattern.For example, pattern 3 is arranged in the order of channels 3', 4, 1, and 2. In this case, channel 1.2 precedes channel 3.4 by 1 bit. are doing.

Therefore, #1 and #2 are detected from detection point A (output of D flip-flop 21), and #3. #4 detection circuit 33
leading to the synchronization bit pattern of channels 1, 2, 3.4 and #3. #4. #1. Compare the #2 signal to detect whether they match.

If any one of the frame synchronization pattern detection circuits 31 to 34 detects a synchronization bit pattern, that circuit transfers the control signal to the channel switching circuit 4 and the phase synchronization circuits 51 to 54.
Send to. The channel switching circuit 4 learns the signal arrangement pattern from this signal and rearranges the channels in a regular order.

Then, the phase synchronization circuits 51 to 54 delay the signal that is ahead by 1 bit by 1 bit to eliminate a 1-bit shift between channels, thereby achieving bit phase synchronization with respect to the frame format.

[Effects of the Invention °] As explained above, according to the present invention, in the loop that detects a frame synchronization pattern and feeds back the detection result to the frame synchronization circuit, it is possible to operate at the transmission speed of a low-order group signal. It becomes possible to separate high-speed high-order group signals.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a diagram showing the low-order signal arrangement pattern after separation and the detection position of the synchronization bit in each pattern, and Figure 3 is a diagram showing the conventional frame synchronization method. FIG. DESCRIPTION OF SYMBOLS 1... Serial-to-parallel conversion circuit, 2.22... D flip-flop, 4... Channel switching circuit, 31-34... Frame synchronization pattern detection circuit, 51
~54...Phase synchronization circuit. Patent applicant: Sumitomo Electric Industries, Ltd.

Claims (1)

[Claims] 1) When separating high-order group PCM signals into low-order group signals, by detecting frame synchronization bits from the separated low-order group signals without considering the order of channels and mutual phase synchronization between channels, A parallel frame synchronization method characterized by rearranging channels in a regular order and eliminating bit phase shifts between channels.