JPH01167679A - Impedance measuring instrument - Google Patents

Impedance measuring instrument

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Publication number
JPH01167679A
JPH01167679A JP32827687A JP32827687A JPH01167679A JP H01167679 A JPH01167679 A JP H01167679A JP 32827687 A JP32827687 A JP 32827687A JP 32827687 A JP32827687 A JP 32827687A JP H01167679 A JPH01167679 A JP H01167679A
Authority
JP
Japan
Prior art keywords
sine wave
output
converter
numerical
waveform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32827687A
Other languages
Japanese (ja)
Other versions
JP2587970B2 (en
Inventor
Hitoshi Kitayoshi
均 北吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP32827687A priority Critical patent/JP2587970B2/en
Priority to US07/284,352 priority patent/US4947130A/en
Priority to DE88121429T priority patent/DE3880648T2/en
Priority to EP88121429A priority patent/EP0321963B1/en
Publication of JPH01167679A publication Critical patent/JPH01167679A/en
Application granted granted Critical
Publication of JP2587970B2 publication Critical patent/JP2587970B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Measurement Of Resistance Or Impedance (AREA)

Abstract

PURPOSE:To obtain a high speed, highly accurate and low cost device by using a waveform read-out from sinusoidal waveform memory. CONSTITUTION:An output of an oscillator 37 is divided for the frequency by 1/m at a variable frequency divider 38, then a clock of the frequency fs is inputted into a phase accumulator 32. On accumulating the addition of numeric value (n) for every clock, the accumulator 32 outputs a numerical waveform 33 into the terminal 34 and a pulse 36 into the terminal 35 for every over-flow. The numerical waveform 33 is given to the waveform memory 41-43 of a numerical sine wave generating means, then first, second numerical sine wave and the numerical cosine wave are generated in the latches 44-46. The first numerical sine wave is given to a material 53 to be measured through a D/A converter 47, low-pass filter 48, amplifier 49, DC bias 51 and an adder 52. The output current Ix of the material 53 is converted to a voltage Vout by a current voltage converter 54 and given to a multiplication shape D/A converters 55, 56. The multiplication output deriving from the Vout which is outputted from the converters 55, 56 and the second sine wave or the cosine wave is converted to a conductance component Rl and receptance component Im by the integrator 61, 62.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は低周波、超低周波においても被測定物のイン
ピーダンス伝達関数を高速、高精度に測定することがで
きるインピーダンス測定装置に関する。
DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an impedance measuring device that can measure the impedance transfer function of a measured object at high speed and with high precision even at low frequencies and very low frequencies.

「従来の技術」 従来の同期検波方式のインピーダンス測定装置は第4図
に示すように方形波発振器11の端子12より0゛位相
の方形波と、端子13より90°位相の方形波とを出力
し、端子12のO°位相方形波を低域通過濾波器14を
通して正弦波出力とし、増幅器15で増幅した後、被測
定物16へ供給する。被測定物16の電流出力1.を電
流電圧変換器17で電圧信号に変換し、その電圧信号を
同期検波器18.19へそれぞれ供給し、端子12゜1
3よりの方形波と掛算して同期検波を行い、これら同期
検波器18.19の出力を積分器21゜22でそれぞれ
積分して、積分出力R,とIIIとを得、これらをスイ
ッチ23で切替えてAD変換器24へ供給してデジタル
信号に変換する。電流電圧変換器17の帰還抵抗器25
の抵抗値をRとすると、AD変換器24からデジタルの
ベクトル電圧R−1,=R,+j I、が得られる。
"Prior Art" A conventional synchronous detection type impedance measuring device outputs a square wave with a 0° phase from the terminal 12 of the square wave oscillator 11 and a square wave with a 90° phase from the terminal 13, as shown in FIG. Then, the O° phase square wave at the terminal 12 is passed through a low-pass filter 14 to become a sine wave output, amplified by an amplifier 15, and then supplied to an object to be measured 16. Current output of the object to be measured 16 1. is converted into a voltage signal by the current-voltage converter 17, and the voltage signals are supplied to the synchronous detectors 18 and 19, respectively, and the terminals 12゜1
The outputs of these synchronous detectors 18 and 19 are integrated by integrators 21 and 22, respectively, to obtain integral outputs R and III, which are output by switch 23. The signal is switched and supplied to the AD converter 24, where it is converted into a digital signal. Feedback resistor 25 of current-voltage converter 17
Assuming that the resistance value of is R, a digital vector voltage R-1,=R,+j I is obtained from the AD converter 24.

低域通過濾波器14から周波数fcの出力Sitが第5
図Aに示すように得られるとすると、被測定物16、電
流電圧変換器17から第5図Aに示すように歪sty、
 St3・・・が発生する。一方、方形波のスペクトラ
ムは第5図Bに示すように比較的大きい奇数次の高調波
を含む、従って同期検波器18.19では前記量が、高
調波により同期検波され、出力に現れる。つまりこの従
来の測定装置は被測定物16、電流電圧変換器17の歪
が直接測定誤差となる問題があった。
The output Sit of frequency fc from the low-pass filter 14 is the fifth
Assuming that the results are obtained as shown in FIG. 5A, the strain sty, as shown in FIG.
St3... occurs. On the other hand, the spectrum of the square wave includes relatively large odd-order harmonics as shown in FIG. In other words, this conventional measuring device has a problem in that the distortion of the object to be measured 16 and the current-voltage converter 17 directly causes measurement errors.

またインピーダンス測定装置として第6図に示すものが
考えられる。すなわち正弦波発振器26の出力電圧■五
〇を被測定物16へ供給し、被測定物16の電流出力I
つを電流電圧変換器17で電圧信号に変換し、その電圧
信号をAD変換器27でデジタル信号に変換する。その
デジタル信号をフーリエ変換器28でフーリエ変換して
−R1゜と対応したS、を得る。一方、正弦波発振器2
6の出力VいをAD変換器29でデジタル信号に変換し
、そのデジタル信号をフーリエ変換器31でフーリエ変
換してV’sと対応したS、を得る。従ってZ−−■=
、/1.−  R−S−/Sbを求めることができる。
Further, as an impedance measuring device, the one shown in FIG. 6 can be considered. That is, the output voltage of the sine wave oscillator 26 is supplied to the object under test 16, and the current output I of the object under test 16 is
A current-voltage converter 17 converts one into a voltage signal, and an AD converter 27 converts the voltage signal into a digital signal. The digital signal is Fourier-transformed by a Fourier transformer 28 to obtain S corresponding to -R1°. On the other hand, sine wave oscillator 2
6 is converted into a digital signal by an AD converter 29, and the digital signal is Fourier transformed by a Fourier transformer 31 to obtain S corresponding to V's. Therefore Z−−■=
, /1. - R-S-/Sb can be determined.

このインピーダンス測定装置は被測定物16、電流電圧
変換器17の歪の影響を受けないが、へ〇変換器27.
29は波形をデジタル信号に変換するため高速、高精度
が要求され高価になる。またフーリエ変換数値処理が必
要なため高速に実行することが難しい問題があった。
This impedance measuring device is not affected by the distortion of the object to be measured 16 and the current-voltage converter 17;
29 converts a waveform into a digital signal, so high speed and high precision are required, making it expensive. Furthermore, since it requires Fourier transform numerical processing, it is difficult to execute it at high speed.

r問題点を解決するための手段」 この発明によれば少(とも1つの正弦波波形メモリを含
む数値正弦波発生手段がフェーズアキュムレータの出力
で読出され、第1デジタル正弦波、第2デジタル正弦波
、デジタル余弦波を発生する。
According to the present invention, a numerical sine wave generating means including at least one sine wave waveform memory is read out at the output of a phase accumulator and generates a first digital sine wave, a second digital sine wave, and a second digital sine wave. wave, generates a digital cosine wave.

その第1デジタル正弦波はDA変換器でアナログ信号に
変換されて被測定物へ供給される。被測定物の出力と第
2デジタル正弦波とが第1乗算形OA変換器で掛算され
、被測定物の出力とデジタル余弦波とが第2乗鼻形DA
変換器で掛算される。第1乗算形DA変換器、第2乗鼻
形DA変換器の各出力は第1積分器、第2積分器でそれ
ぞれ正弦波周期の整数倍の区間積分される。
The first digital sine wave is converted into an analog signal by a DA converter and supplied to the object under test. The output of the object to be measured and the second digital sine wave are multiplied by the first multiplier type OA converter, and the output of the object to be measured and the digital cosine wave are multiplied by the second multiplier type OA converter.
Multiplied by converter. The respective outputs of the first multiplier type DA converter and the second multiplier type DA converter are integrated over an interval of an integer multiple of the sine wave period by the first integrator and the second integrator, respectively.

「実施例」 第1図はこの発明の実施例を示す。この発明ではフェー
ズアキュムレータ32が設けられる。フェーズアキュム
レータ32は与えられた数値nをクロックごとに累加算
し、数値波形33を端子34に出力し、内部の累加算器
のオーバーフローごとに端子35にパルス36を出力す
る0発振器37の出力が可変分周器38でm分の1に分
周され、周波数r1のクロックがアキュムレータ32に
入力される。
"Embodiment" FIG. 1 shows an embodiment of the present invention. In this invention a phase accumulator 32 is provided. The phase accumulator 32 accumulates a given numerical value n every clock, outputs a numerical waveform 33 to a terminal 34, and outputs a pulse 36 to a terminal 35 every time the internal accumulator overflows. The frequency is divided by m by the variable frequency divider 38, and the clock having the frequency r1 is input to the accumulator 32.

アキュムレータ32の端子34の出力33は数値正弦波
発生手段39へ出力される。数値正弦波発生手段39は
この例では第1正弦波波形メモリ41、第2正弦波波形
メモリ42、余弦波波形メモリ43を備え、これらメモ
リ41,42.43は端子34からの数値をアドレスと
して読出されてクロックによりラッチ回路44,45.
46に格納される。
The output 33 of the terminal 34 of the accumulator 32 is output to numerical sine wave generating means 39. In this example, the numerical sine wave generating means 39 includes a first sine wave waveform memory 41, a second sine wave waveform memory 42, and a cosine waveform memory 43, and these memories 41, 42, and 43 use the numerical value from the terminal 34 as an address. The latch circuits 44, 45 .
46.

ラッチ回路44の出力はDA変換器47でアナログ信号
に変換され、そのアナログ信号は低域通過ろ波器48を
通され、必要に応じて増幅器49で増幅され、更に必要
に応じて端子51からの直流バイアスが加算器52で加
算され、その加算出力ViMが被測定物53へ供給され
る。被測定物53の出力電流I8は電流電圧変換器54
で電圧出力vl、llLに変換される。
The output of the latch circuit 44 is converted into an analog signal by a DA converter 47, and the analog signal is passed through a low-pass filter 48, amplified by an amplifier 49 as necessary, and further outputted from a terminal 51 as necessary. DC biases are added by an adder 52, and the added output ViM is supplied to the device under test 53. The output current I8 of the object to be measured 53 is transferred to the current-voltage converter 54.
are converted into voltage outputs vl and llL.

この電圧出力■。□は第1.第2乗算形DA変換器55
.56にそれぞれ基準電圧として供給される。第1.第
2乗算形DA変換器55.56のデータ入力端子にはラ
ッチ回路45.46の各出力が供給される。第1.第2
乗算形DA変換器55゜56のデータ入力端子にはラッ
チ回路45.46の各出力が供給される。第1.第2乗
算形DA変換器55.56の出力はそれぞれスイッチ5
7゜58を通じて第1.第2積分器61.62へ供給さ
れる。第1.第2積分器61.62の出力は切替スイッ
チ63を通じ7AD変換器64へ供給される。
This voltage output ■. □ is the first. Second multiplication type DA converter 55
.. 56 as reference voltages. 1st. Each output of the latch circuit 45.46 is supplied to the data input terminal of the second multiplier type DA converter 55.56. 1st. Second
The respective outputs of latch circuits 45 and 46 are supplied to data input terminals of multiplier type DA converters 55 and 56. 1st. The outputs of the second multiplication type DA converters 55 and 56 are respectively connected to the switches 5 and 5.
1st through 7°58. It is fed to a second integrator 61,62. 1st. The outputs of the second integrators 61 and 62 are supplied to the 7AD converter 64 through the changeover switch 63.

フェーズアキュムレータ32の端子35のパルスはサイ
クルカウンタ65で計数され、カウンタ65の出力66
により第1.第2積分器61.62のリセットスイッチ
67.68が短時間オンとされて第1.第2積分器61
.62がリセットされる。そのリセット後の所定期間に
/f、(fcはパルス36の周波数、kは整数)、スイ
ッチ57゜58はカウンタ65の出力69で第1.第2
乗算形1)A変換器55.56の出力側を第1.第2積
分器61.62に接続する。出力69の後縁からリセッ
トパルス66の直前までの間に、第1.第2積分器61
.62の出力がAD変換器64でそれぞれディジタル値
に変換される。
The pulses at terminal 35 of phase accumulator 32 are counted by cycle counter 65 and output 66 of counter 65
According to the 1st. The reset switch 67.68 of the second integrator 61.62 is turned on for a short time so that the reset switch 67.68 of the second integrator 61.62 is turned on for a short time. Second integrator 61
.. 62 is reset. During a predetermined period after the reset, /f (fc is the frequency of the pulse 36, k is an integer), the switch 57.58 switches the output 69 of the counter 65 to the first .f. Second
Multiplying type 1) Connect the output side of the A converter 55, 56 to the first. Connected to second integrator 61,62. Between the trailing edge of the output 69 and just before the reset pulse 66, the first . Second integrator 61
.. The outputs of 62 are each converted into digital values by an AD converter 64.

第1.第2乗算形DA変換器55.56の各出力は、 V、、、(t)Sin(ωt> Vout(t)Cos(ωt) となり、ω=2πfcs第2πfcs分器61゜62の
各出力は、 とそれぞれなる。tz −tl−に7/fc、つまりV
 outがフーリエ変換された出力R,,!、が得られ
る。この観測される出力R,+j1.は被測定物53を
流れる電流1.に比例する。
1st. The outputs of the second multiplier DA converters 55 and 56 are V, , (t)Sin(ωt>Vout(t)Cos(ωt), and ω=2πfcs.The outputs of the 2nd πfcs divider 61 and 62 are as follows. , respectively. tz -tl- has 7/fc, that is, V
Output R,,! out is Fourier transformed. , is obtained. This observed output R, +j1. is the current 1. flowing through the object to be measured 53. is proportional to.

Vout = RI * = J + J I mRは
電流電圧変換器54の帰還抵抗器71の抵抗値である。
Vout = RI * = J + J I mR is the resistance value of the feedback resistor 71 of the current-voltage converter 54.

従って被測定物53のインピーダンスZXは R,+j’l。Therefore, the impedance ZX of the object to be measured 53 is R, +j'l.

で求まる。V i nは被測定物53に加える正弦波振
幅、冴は測定システムの補正ベクトルである。
It can be found by V in is the amplitude of the sine wave applied to the object to be measured 53, and V is the correction vector of the measurement system.

v0□を検波する信号、つまりラッチ回路45゜46の
出力のスペクトラムは第5図Cに示すようになる。測定
対象スペクトルS1と一致したスペクトルSb+は検波
に有効な成分となる。スペクトルS。、S、3・・・被
測定物53、電流電圧変換器54の歪スペクトルと一致
したものであり、測定誤差と成るが、一般に極く微少、
1/1000以下であるため影響は少ない。スペクトル
S CI r  S C!はmf。
The spectrum of the signal detecting v0□, that is, the output of the latch circuit 45°46, is as shown in FIG. 5C. The spectrum Sb+ that matches the measurement target spectrum S1 becomes an effective component for detection. Spectrum S. , S, 3... This matches the distortion spectrum of the object to be measured 53 and the current-voltage converter 54, resulting in a measurement error, but it is generally extremely small.
Since it is less than 1/1000, the influence is small. Spectrum S CI r SC! is mf.

±fc (m=1.2.・・・)で発生するサンプル不
要スペクトルである。r、/rCを非整数、例えば10
.24に選択すれば、このスペクトルは被測定物53、
電流電圧変換器54の歪スペクトルと一致しないため、
測定誤差とはならない。積分区間1、−1.を1/f、
の整数倍でかつ1/f、の整数倍例えば40 o7rc
=4096/r、に選択されない場合は、スペクトルS
C1+  scz成分はフーリエ変換切り取り誤差とし
て観測される。この誤差は積分区間Ltt+=に/fc
で選択される整数k及びf、/fcに反比例して減少す
るため、例えばf、 /fc=10.24 、k= 1
0で切り取り誤差は0.1%以下である。
This is a sample-free spectrum generated at ±fc (m=1.2...). r, /rC is a non-integer, for example 10
.. 24, this spectrum corresponds to the object to be measured 53,
Since it does not match the distortion spectrum of the current-voltage converter 54,
This is not a measurement error. Integral interval 1, -1. 1/f,
and an integer multiple of 1/f, e.g. 40 o7rc
=4096/r, if not selected, the spectrum S
The C1+scz component is observed as a Fourier transform truncation error. This error is in the integral interval Ltt+=/fc
For example, f, /fc=10.24, k=1
0, the cutting error is 0.1% or less.

第1図において電流電圧変換器54の替りに電圧電圧変
換器を用いれば被測定物53の伝達関数を測定すること
ができる。
If a voltage-voltage converter is used in place of the current-voltage converter 54 in FIG. 1, the transfer function of the object to be measured 53 can be measured.

第1図中の数値正弦波発生手段39としては第2図に示
すように構成してもよい。つまりフェーズアキュムレー
タ32の出力をフェーズシフタ72へ供給し、0°出力
と90°出力とを第3図aに示すように交互に出力し、
これら出力により正弦波波形メモリ73が読出され、つ
まり正弦波波形メモリ73から0°の正弦波とこれより
90°進んだ正弦波、つまり余弦波とが交互に読出され
る。
The numerical sine wave generating means 39 in FIG. 1 may be constructed as shown in FIG. 2. That is, the output of the phase accumulator 32 is supplied to the phase shifter 72, and the 0° output and the 90° output are alternately outputted as shown in FIG. 3a.
These outputs read out the sine wave waveform memory 73, that is, a 0° sine wave and a 90° sine wave, that is, a cosine wave, are alternately read out from the sine wave waveform memory 73.

余弦波が読出された時に、第3図すのパルスによりラッ
チ回路74にラッチされ、正弦波が読出された時に第3
図Cのパルスによりラッチ回路75にラッチされると共
にラッチ回路74の出力がラッチ回路76にラッチされ
る。ラッチ回路75の出力はDA変換器47及び第1乗
算形DA変換器55へ供給され、ラッチ回路76の出力
は第2乗算形DA変換器56へ供給される。
When the cosine wave is read out, it is latched in the latch circuit 74 by the pulse shown in Figure 3, and when the sine wave is read out, the third
The output of the latch circuit 74 is latched by the latch circuit 75 by the pulse shown in FIG. C, and the output of the latch circuit 74 is latched by the latch circuit 76. The output of the latch circuit 75 is supplied to the DA converter 47 and the first multiplication type DA converter 55, and the output of the latch circuit 76 is supplied to the second multiplication type DA converter 56.

第1図中の第1積分器61の出力R,は被測定インピー
ダンスZ、のコンダクタンス成分でアリ、第2積分器6
2の出力I7はリセブタンス成分であり、これらR,,
1,をオシロスコープで直接観測してもよい。
The output R of the first integrator 61 in FIG. 1 is the conductance component of the impedance to be measured Z.
The output I7 of 2 is a resbutance component, and these R, ,
1, may be directly observed with an oscilloscope.

「発明の効果」 以上述べたようにこの発明においては高速、高精度のA
D変換器を使用しないため、第6図に示したものと比較
して、安価に構成することができる。デジタルフーリエ
変換数値処理を必要とせず高速度に動作する。被測定物
や電流電圧変換器の歪の影響を受けないため高精度の測
定が可能である。更に第4図に示した従来のものにおい
ては測定周波数を変化させるには低域通過ろ波器14の
通過特性をも変更させる必要があり、周波数を可変とす
ることは困難であるが、この発明においては周波数を変
化させても第5図C中のスペクトルS C1+ sci
はわずかじか変化しないため、これを除去するためのる
波器のろ波特性を可変とする必要がなく、容易に測定周
波数fcを変化させることができる。
“Effects of the Invention” As stated above, this invention provides high-speed, high-precision A
Since no D converter is used, the structure can be constructed at a lower cost than that shown in FIG. Digital Fourier transform Operates at high speed without requiring numerical processing. Highly accurate measurement is possible because it is not affected by distortion of the object to be measured or the current-voltage converter. Furthermore, in the conventional device shown in FIG. 4, it is necessary to change the pass characteristics of the low-pass filter 14 in order to change the measurement frequency, and it is difficult to make the frequency variable. In the invention, even if the frequency is changed, the spectrum S C1+ sci in FIG.
Since there is only a slight change in fc, there is no need to vary the filtering characteristics of the filter for removing this, and the measurement frequency fc can be easily changed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の実施例を示すブロック図、第2図は
その数値正弦波発生手段の変形例を示すブロック図、第
3図はその動作の説明に供する波形図、第4図は従来の
インピーダンス測定装置を示すブロック図、第5図はこ
の発明の説明に供するためのスペクトラムを示す図、第
6図は従来の他のインピーダンス測定装置を示すブロッ
ク図である。 特許出願人:株式会社アトパンテスト
Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing a modification of the numerical sine wave generating means, Fig. 3 is a waveform diagram for explaining its operation, and Fig. 4 is a conventional one. FIG. 5 is a diagram showing a spectrum for explaining the present invention, and FIG. 6 is a block diagram showing another conventional impedance measuring device. Patent applicant: Atopan Test Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] (1)フェーズアキュムレータと、 少くとも1つの正弦波波形メモリを含み、上記フェーズ
アキュムレータの出力で読出され、第1デジタル正弦波
と、第2デジタル正弦波と、デジタル余弦波とを発生す
る数値正弦波発生手段と、上記第1デジタル正弦波をア
ナログ信号に変換して被測定物へ供給するDA変換器と
、 上記被測定物の出力と上記第2デジタル正弦波とを掛算
する第1乗算形DA変換器と、 上記被測定物の出力と上記デジタル余弦波とを掛算する
第2乗算形DA変換器と、 上記第1乗算形DA変換器の出力を正弦波周期の整数倍
の区間積分する第1積分器と、 上記第2乗算形DA変換器の出力を正弦波周期の整数倍
の区間積分する第2積分器とを具備するインピーダンス
測定装置。
(1) A numerical sine waveform comprising a phase accumulator and at least one sine wave waveform memory, read out at the output of the phase accumulator to generate a first digital sine wave, a second digital sine wave, and a digital cosine wave. a wave generating means, a DA converter that converts the first digital sine wave into an analog signal and supplies it to the object to be measured, and a first multiplier that multiplies the output of the object to be measured and the second digital sine wave. a DA converter; a second multiplication type DA converter that multiplies the output of the object to be measured by the digital cosine wave; and a second multiplication type DA converter that integrates the output of the first multiplication type DA converter over an interval of an integral multiple of the sine wave period. An impedance measuring device comprising: a first integrator; and a second integrator that integrates the output of the second multiplier type DA converter over an integral multiple of the sine wave period.
JP32827687A 1987-12-23 1987-12-23 Impedance measuring device Expired - Lifetime JP2587970B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP32827687A JP2587970B2 (en) 1987-12-23 1987-12-23 Impedance measuring device
US07/284,352 US4947130A (en) 1987-12-23 1988-12-14 Impedance measuring apparatus
DE88121429T DE3880648T2 (en) 1987-12-23 1988-12-21 Impedance meter.
EP88121429A EP0321963B1 (en) 1987-12-23 1988-12-21 Impedance measuring apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32827687A JP2587970B2 (en) 1987-12-23 1987-12-23 Impedance measuring device

Publications (2)

Publication Number Publication Date
JPH01167679A true JPH01167679A (en) 1989-07-03
JP2587970B2 JP2587970B2 (en) 1997-03-05

Family

ID=18208415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32827687A Expired - Lifetime JP2587970B2 (en) 1987-12-23 1987-12-23 Impedance measuring device

Country Status (1)

Country Link
JP (1) JP2587970B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014104188A1 (en) * 2012-12-27 2014-07-03 学校法人早稲田大学 Electrochemical analysis device and electrochemical system
CN104781679A (en) * 2012-12-03 2015-07-15 三菱电机株式会社 Voltage detection device
JP2018036205A (en) * 2016-09-01 2018-03-08 日置電機株式会社 Impedance measurement device and impedance measurement method
CN110058164A (en) * 2019-05-14 2019-07-26 重庆西南集成电路设计有限责任公司 The self-powered online internal resistance test device of battery

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104781679A (en) * 2012-12-03 2015-07-15 三菱电机株式会社 Voltage detection device
WO2014104188A1 (en) * 2012-12-27 2014-07-03 学校法人早稲田大学 Electrochemical analysis device and electrochemical system
US9977059B2 (en) 2012-12-27 2018-05-22 Waseda University Electrochemical analysis apparatus and electrochemical system
JP2018036205A (en) * 2016-09-01 2018-03-08 日置電機株式会社 Impedance measurement device and impedance measurement method
CN110058164A (en) * 2019-05-14 2019-07-26 重庆西南集成电路设计有限责任公司 The self-powered online internal resistance test device of battery
CN110058164B (en) * 2019-05-14 2021-06-11 重庆西南集成电路设计有限责任公司 Battery self-powered online internal resistance tester

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