JPH01116730A - Digital signal processor - Google Patents

Abstract

PURPOSE:To flexibly and easily configure a high-speed signal processing system by specifying uniquely a computing element action to various operations, combining a function code and a control code corresponding to this and composing a microinstruction code. CONSTITUTION:The title device has 5-stage structure to which a stage to read data out of a data memory to an instruction executing pipe line stage and input the data to a computing element 106 and a stage to output data from the computing element 106 and write them into the data memory or execute an accumulation or a data rounding by using an accumulator in the computing element are added, a barrel shifter, a multiplier, an arithmetic and logic unit are arranged in the same row in the computing element 106 corresponding to an execution stage in the 5 stages, a barrel shifter for regularizing is connected in the next step corresponding to a writing/accumulation stage and the output of this is made into an input to an adder for rounding/accumulation or the output of the computing element. Thus, a digital signal processing processor whose device configuration is rich in flexibility and simple can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing processor that performs arithmetic processing mainly on signal sequences.

[Conventional technology]

Figure 1 shows the conventional digital signal processing processor D88P1 (4810-1) shown in the 1986 IEICE National Conference Symposium (4810-1).
Digital 5peech 81gnalPro
In Figure 9, (1) is a program counter PC with a built-in stack for controlling instruction addresses, (21 is an instruction mask ROM that stores microinstructions, and +31 is this instruction mask). The instruction register RO0 (4), which inputs IcI words input from the ROM+21 or the outside, every machine cycle, is an instruction register that inputs only the bit fields that need to be decoded in the microinstructions input to the instruction register RO+31. IRI, +5) is this instruction register R? An instruction decoder (6) decodes the microinstructions input to the P-Bu8.141, and a program bus P-Bu8. (71 is this program buff,
The immediate value (18-bit width) in the microinstruction output from P-Bus (6) is input, and the data bus D-Bu
(8) is an 18-bit wide data bus D-13us used for internal transfer of data associated with calculations, and (9) is a program bus P-Bug that outputs data memory address mode instructions. (Register AM input from 61, [11 is a 4W x 16-bit wide register AD that holds address pointer information used for indirect address generation, full is a 3-bit wide page register PR that specifies the page of external data memory, ff2
is a 9-bit wide address calculator AAU that can generate up to three addresses at the same time, +13 is an address register AR
O, f141 is address ll register ARI, 115 is address register A12, 118 is address selector R
AS, (171 is the loop counter Do, (J bar is the status register 8R that displays the operating mode and status of the processor, α is the serial port Sxa/''1
, a DMA control unit that directly transfers data between Son/l (to) and external data memory, 1211 is an address register AR that holds a 12-bit wide address to be output to the external data memory, and 1211 is a capacity of 512W x 1a bit. Dual port internal data memory 2, P-RAM, which can read and write two types of data at the same time, @ is a register that holds operand input data, D P O, ■
is a register DI' that holds calculation input data.1. The gradient is the multiplier i51FMPL that performs floating point multiplication in 12E6-bit format, and @ is the multiplier FMPL.
) 4) The register P that holds the result, @ is the selector, ■
is a selector, and (to) is a floating-point arithmetic logical operation 1 that mainly performs floating-point operations in 12E6 bin format.
FALU, @ is this floating point arithmetic logic operation 15FAL
4WX18 which holds the output of U (to) and uses it for accumulation etc.
Bit accumulator AaaO~AOC! 3. ω is a data register DR connected to the data bus D-Bus (8) for the purpose of temporarily holding read/write data to the external data memory, and On is a read/write control circuit for the external data memory R/W Cont. , e
33 is a serial port 10 that performs full-duplex 2-channel serial data transfer with an external device.
/1, 800/1, @ is interrupt control circuit engineering nt.

Cont, , (to) is the external data memory bus control circuit Bu80ont, , (to) is the clock YfiI control circuit CL K Cant, +(
) is a selector.

FIG. 8 is a time chart illustrating the microinstruction execution sequence of the digital signal processing processor DB8P1 shown in FIG. 7;

The main feature is cycle timing consisting of four-phase clocks.

0υ is the fetch stage timing indicating the stage of the address output of the program counter PO11) and the microinstruction input to the instruction register I RQ +31, and the book is the instruction register R1t.
4) is the decode stage timing when the instruction decoder (5) decodes the microinstruction input to the instruction decoder (5). 3 is the timing for updating the address calculator AAtT (12) in the decode stage; @4 is the floating point multiplication! PM P L + 241 09 is the timing when the floating point arithmetic and logic unit FALσ (to) performs the operation, and the third is the data bus D-Bus.
The timing at which data is transferred between registers via (8) is the timing at which data is read/written to the external data memory via the data register DRI31.

FIG. 9 is a diagram showing the structure of a microinstruction consisting of 32 bits per word classified into four groups of the digital signal processing processor DE18P1 shown in FIG. Sequence instructions to control, (
51) Status register 8R (lη, address calculation WAAU [12, DMA control unit (mode command indicating Ig mode setting/initial value setting).

(52) is an arithmetic instruction that mainly controls execution on the floating point arithmetic and logic unit FALU@ and associated parallel data transfer, and (55) is a load instruction that executes an immediate value load to any register or data memory.

Next, the operation will be explained. Hereinafter, for the sake of simplicity, the abbreviations used in the above description will be used for the names of each part.

First, the overall general operation will be explained based on FIG. This signal processing processor uses P-Bus (6) and D-arm θ
(8) has a separate configuration, micro-instruction input to the engineering RO (31), micro-instruction transfer via P-Bus (61), micro-instruction decoding by the instruction decoder (5), and D-Bus (8). ),
IPMPL+241. Instructions such as FALUfi are executed in parallel by pipeline processing. Here, D-Bus (8), 2 P-R
All execution units including A M (211) are register-based, that is, all inputs and outputs are connected to registers.The access timing to this register is such that the output is output at the leading edge of the machine cycle. , the register is set at the trailing edge of the machine cycle.In other words, the data actually processed is not the content set in the register by the same microinstruction, but the content set in the register by one or more previous microinstructions. Become.

This is called a delayed operation, and by separating each section in the arithmetic unit with registers, it is possible to operate each section in parallel. For example, FMPLQ4 always performs a floating point multiplication once per machine cycle in this processor. When inputting calculation data here, first use the previous microinstruction: opocc, npt
Set the data to @.

It is set to P (c) by one or more subsequent microinstructions.
.

Obtain the multiplication result by extracting the contents. Until this content is extracted, DPOI2'3. DPI (To), P (
5) Since the data is retained by 1, a single multiplication that would normally require 9 multiplications for data input, 3 data outputs, and 3 microinstructions becomes 9 equivalently 1 microinstruction when processing is performed continuously. It can be processed once.

In DEII9P1, FMPL24 and FAI+U (to) are connected via P (to), and FALU (to) is connected to AC! G
o~ACC3 is configured so that the contents of P2!2 can be accumulated.

This is Louis Eichirm's I! f
A paper published in the December 20, 1919 issue of electronics “Packing signal proc”
essor onto a single digit
alboa (similar to the multiplier-accumulator pair shown in 1″).

Filtering* FI T (Faat Four
This is for executing one term of the sum-of-products operation in one machine cycle, which is often used in the butterfly operation of the IER Transform.

For example, the sum of products follows the following formula.

In this processor, the sum of products of one term is DPO@.

Data input to DPI (c), multiplication by IFMPLG4).

FAI, UF4) m is set to P (to) and requires 3 microinstructions for the nine multiplication results and the accumulation of ACOO to AC3C5@. Of course, when processing is performed continuously, it is possible to equivalently implement the sum of products of one term once per one microinstruction. Naturally, in order to execute the sum of products of one term once per microinstruction in this way, two input data corresponding to ail bi in the above formula must be input to the DP for each microinstruction.
It is necessary to input to E@ and DPI (c). Therefore, these two input data can be supplied by the 2P-RAM 211VC.

In order to avoid bus contention for D-Bus t8), 2P
-The data read from RAM 211 is D-Bu
Provides a path for direct transfer to the DPO (2'3.DPI (to)) without going through the
In order to specify the address of 2 input data of 211, AAt7
(IJ is ARO (13).

AR1114), 9 output via AR21L51
Means for selecting and outputting two of the focus width address data is provided. This 0AAUu3 is 2P-RAMCJII
It is configured such that a maximum of three addresses can be specified simultaneously only in the case of two input data addresses from DRC3f) and one output data address to external data memory via AR. Each address specification is all.

AA It is possible to update L other A
Ri4. AR21Li is only capable of simple increment. AAUα2 is capable of address calculation only in 9-pin natural binary format, and when specifying a 12-bit external data memory address, PRl is added to these 9 bits.
Together with the 3-pin memory page designation specified by ll, the total is 12 bits.

10,000, IFMPLt241. FALU(2) is 12E6
To perform operations in the normalized floating point format of 2P-
RAMell, DPO ■, DPI (ha), P (ha),
Accg~AOO3@, DIt311. D-B
uat8), B work (7) are all 18 bits wide and 9fi
, IFALU(to) requires a special operation mode to use a special address initial value. For this reason, A
RO (1ken, AR1tl lump.

There is no data compatibility between the operation result data set in AR2d, AR2 and Aca(1 to AOC3(2)).

The DMA control unit +11 has a total of 2 channels of full duplex serial data 10 ports S 0/1. Data transfer between input/output data of soO/Ni3 and external data memory is executed independently of microinstructions. D-Bus (8) and AR (21) are used for data transfer by the DMA control unit (19).

Since DRC3G is used, there is a risk that this internal resource will conflict with the microinstruction operation controlled by the instruction decoder (5).

In order to avoid this, the instruction decoder (5) is paused for 6 machine cycles for each word during data transfer by the DMA control unit α9.

Stops actions caused by microinstructions.

Above f: In summary, DBSP1 can execute the following operations in parallel within one microinstruction when executing a microinstruction.

■ Up to three types of 9-bit address operations using AAU03.

■ 12E6 floating point multiplication by FMPLeJ4 ■ 12FX6 floating point operation by FALU(2).

■ 2P-RAMc! 11 and D -Hue (81,D
Data transfer between external data memories via RFI.

■ 2 channels full duplex serial interface 10 ports S 0
/1. Son/ICR and D-Hue (8) IDRC
DMA data transfer between external data memories via 31.

Next, the microinstruction execution timing of DBSP1 will be explained based on FIG. DBSPl machine cycle +41 divides one machine cycle into four, fcPO~
It operates according to the four-phase timing of P3, and the cycle time of one machine cycle is nominally 50 naec, which is fast. Therefore, the instruction mask R within one machine cycle
Reading of microinstructions from OM+21, decoding of microinstructions by instruction decoder (5),
FMPLCI! 41. In reality, it is difficult to perform the three operations of executing instructions using internal resources such as FAI and U (To). Therefore.

In the DB8P1, these three stages are each divided into stages of one machine cycle each, forming a three-stage pipeline to realize high-speed operation. The following is performed at each stage of this three-stage pipeline.

■ Microinstruction address output by fetch stage 0υ pc(1) and microinstruction reading from instruction mask ROM +2). and,
Engineering! t O (to 31, Mike is a command set.

■ Decode stage (to) Microinstruction transfer from Engineering RO (3) to Engineering It 1 (41) and microinstruction decoding by instruction decoder (5) K. And setting of program control mode.

Microinstruction transfer from RO(31 to p-bus (6) and AM+91.MUD(AAtT via In)
l12O address calculation.

■ Execution stage (goods), Lord, ■, (4ηFMPLH,
Data calculation using F'ALU@.

D-Bus (Data transfer via 81r. External data memory access via AR (25°DR), etc.

From this K, DB8P1 requires three machine cycles to execute one microinstruction. However, the pipeline method enables equivalent execution of one microinstruction per machine cycle. Therefore, the instruction mask ROM +2
) There is a delay of two machine cycles from the time the microinstruction is read from the microinstruction to the time the instruction is actually executed. In order to completely prevent timing conflicts in internal resources, internal buses are designated as P-Bus +6) and D-Bus.
(8), and along with this, the instruction mask ROM +
This is the reason why the configuration in which the 2) and 2P-RAM (2]) are separated is adopted. However, in the case of a one-branch instruction, etc., the actual branching occurs at the decoding stage (■), so at that point, the
The microinstruction being set to O(3) will be executed. Namely.

The instruction written after the branch instruction will be executed unconditionally. To avoid this, DBSPl automatically changes the next instruction to NOP (no operation) while a branch instruction is being executed. Although this function is aimed at simplifying the microinstruction description, branching operations result in a loss of one machine cycle, and the
Indirect branching using uθ(8) results in a loss of two machine cycles. Generally speaking, by considering the initial order of instruction descriptions, about 80% of unconditional branches will not cause any problems even if the next instruction is executed, and the above loss can be avoided, but DSI9P
1, this is not possible.

Next, the DB8P10 microinstruction set will be explained based on FIG. The set of microinstructions consists of only four types: sequence, mode, operation, and load instructions.

Sequence instructions control branches, loops, and subroutine calls, and are mainly responsible for instructions to the PC 111. The mode command is A A U T17J selector 1
1.1,0(lη, EIRQI, DMA control unit fiIK
This is an instruction to set the initial value and mode for the . The load instruction is an instruction for loading an immediate value (18-bit width) into a register connected to the D-Bus (13) via the B bus (7). In the above microinstructions, the resource to be operated on remains constant depending on the instruction operation. - On the other hand, regarding arithmetic instructions, it is necessary to directly specify all of the internal resources that can operate in parallel. Therefore, the bit length of the arithmetic instruction is the largest (jj), and the DB8P1 uses horizontal microinstructions with a width of 32 bits. FMP here
LC! 41 is a free run and does not give direct instructions using the above-mentioned busy command. The operation specification for the IP A L UfJK is performed by directly instructing the IP A L UfJK with a command.

■ Absolute value 1x1 ■ Sign correlation Sign (Y)・X ■ Addition X+Y ■ Subtraction X-Y ■ Maximum value MAX (X, Y) ■ Minimum value M engineering N (X, ri) ■ Fixed → floating conversion IPL T (X) ■ Floating → fixed conversion? Engineering X (X) ■ Shift R1, I+1 ~ L8 ■ Logic A
ND, OR, EOR, NO? ■ Mantissa addition XM +
YM ■Exponent subtraction xl -xE The problem here is that the DI38P1 is based on floating point arithmetic, and when performing logic/address arithmetic, it is a fixed point arithmetic. As mentioned above, there is no compatibility between the two. For example, when specifying a memory address due to busy calculation results, it is necessary to execute the instruction (2) in FALU (to). Also.

In general signal processing, floating point data input/output is rarely performed, so each data input/output is
It is necessary to execute instructions and perform data conversion.

The next problem is that bits are always truncated when normalizing floating point data.

Since the signal processing processor has finite calculation precision, it naturally involves calculation errors. However, if this is handled only by truncating bits, and considering the case where the operation result always takes an absolute value, it will be smaller than the true value, and the error will not be randomized. This can be easily reduced to a negligible amount by enlarging the operation word length, but there is a limit to this since ordinary signal processing processors are required to operate at high speed.

Such problems cannot be ignored, especially in image signal processing that performs AE-R type digital filter (cyclic type) and inter-frame processing, and in D8EIP1, it is necessary to round (round off) the processing result using logical operation instructions, etc. . Furthermore, in general signal processing algorithms, calculation accuracy is often specified in various ways for each unit of processing, and the accuracy does not necessarily match the calculation word length of the signal processing processor. In this case, the format conversion of the calculation data is performed using the FALUI 21 for each unit process.

The next problem is that the operations that can be processed at high speed in the DB8P1 are limited to the above-mentioned sum-of-products operations. This is FPT, which is a typical old signal processing algorithm.
The F-engine R filter is required to process at high speed, for example, the one expressed by the following equation.

Σ　1a1-'b1　l Such operations cannot be supported by DB8P1.

Since it is necessary to decompose and process everything into a single four arithmetic operations, three separate operations must be performed to calculate one term. At this time, if the result of the above equation is calculated for each term, 3×3=9 instructions will be required for each 61 terms due to the delay, and the processing multiplicity will be extremely reduced. Of course, by using 2P-RAM+211 to save intermediate results, it is possible to increase the degree of multiplicity by classifying it as differential ten-square accumulation, but this makes it difficult to effectively utilize the limited data memory space. Unable to process data.

For example, consider a case where a binary tree search as shown in FIG. 10 is performed. Here, the input vector A is set on the 2P-RAM+211, and the reference vector B structured in a book shape is arranged in the external data memory as shown in FIG. 11 at each node numbered in FIG. It is assumed that

The evaluation function representing the degree of approximation between input vector A and reference vector B is the sum of absolute differences Σ1a1-bit=1 (A=(ai + (12) r"'+ aN) +
B = (bl + b2 + '', +bs)), and the one with the minimum result is selected in binary form at each stage, and finally the reference vector with the highest degree of approximation is obtained. When the reference vector B of each stage is the current node number n.

The degree of approximation is determined between the two reference vectors B of nodes 2n+1 and 2n+2, and from the result, the node number of the reference vector to be compared in the next stage is calculated. Perform this process on DB8P1
If implemented using , the following number of instruction steps is required.

・Conversion of input data N+2 steps 111 Vector evaluation value calculation 9B+2 steps ・Rounding the evaluation value Approximately 3 steps ・Comparison of evaluation values 4 steps ・About 9 steps for calculating the reference vector address of the next node This is required to calculate the evaluation value Assuming that the ideal value of the Nutep is 2N Nutep, the number of steps is approximately 9 times that of the case where conversion of addresses and input data is not required.

Furthermore, in the case of such processing, the same processing does not occur consecutively, so it is necessary to always be aware of the context of the instructions. For this reason, it is clear that not only the processing efficiency is significantly degraded, but also the program creation becomes extremely complicated, which also poses a problem in terms of the number of man-hours required for software development.

[Problem that the invention seeks to solve]

Since the conventional digital signal processing processor is configured as described above, it has the following problems, for example.

It is necessary to always be aware of the context of commands when creating a program, and processing efficiency cannot be improved unless the same command is executed consecutively.

- Address and data formats are not compatible, and when performing a table lookup, etc., it is necessary to perform format conversion for each data item.

- Since the arithmetic unit only performs sum-of-products, the efficiency of other calculations is extremely poor and programming becomes complicated.

- It is difficult to control the precision of data calculations, and rounding cannot be performed automatically.

・Read all 2-input/1-output operations from data memory at the same time/-! F-inclusion cannot be performed, and efficiency is extremely degraded, for example, in processing vector data.

- Indirect address mode cannot be specified immediately in an instruction;
It is necessary to interrupt processing every time the address mode is changed.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a digital signal processing processor that is highly flexible and easy to implement, and that achieves the following points.

・Efficiency does not decrease even in processing with few repetitions of the same operation without being aware of the context of instructions.

・Compatible with address and data 7omants and performs high-speed search.

- Processes not only sum of products but also other advanced processing at high speed.

To efficiently control calculation accuracy during φ data calculation by a simple means.

・High-speed input/output of vector data to arithmetic units.

- Highly flexible addressing method.

[Means for solving problems]

The digital signal processing processor according to the present invention includes a stage for reading data from a data memory and inputting data to an arithmetic unit in an instruction execution pipeline stage, and a stage for outputting data from the arithmetic unit and writing it to the data memory. Accumulation using an accumulator has a 5-stage configuration including a stage for data rounding, and a barrel shifter, multiplier, and arithmetic logic unit are placed in the same line in the arithmetic unit corresponding to the execution stage of the 52 stages. These next-stage busy normalization barrel shifters are connected in correspondence with the write/accumulation stage, and the output is used as an input to the rounding/accumulation adder or as an output of the arithmetic unit, and is also used as an internal data memory. consists of a 2-port memory on two sides, one readout port on each side is connected to the two input buses of the corresponding arithmetic unit, and the other read/write port is connected to the output bus or one output bus of the unit. An address generation unit that is connected to the DMA transfer bus and generates 2-input 1-output data memory addresses for the arithmetic unit in parallel two-dimensionally corresponding to the instruction execution stage, and a DMA transfer unit between the internal data memory and the external data memory. A MA IJ control section for two-dimensional data transfer using a bus is provided, and the data formats of the address generation section, DMAIJ control section, and arithmetic section are compatible.

Further, the digital signal processing processor according to the present invention uniquely specifies the operation of the arithmetic unit for nine various operations, and the function code corresponding to this and the normalization barrel shifter;
A microinstruction code is constructed by combining two sources and one destination control code for input and one output.

[Effect]

The instruction execution pipeline stage according to the present invention substantially eliminates the need to write microinstructions in consideration of delayed operations, and enables highly efficient processing even when the same instruction is not repeatedly processed.

The calculation section in this invention is a sum of products and a sum of absolute differences.

The calculation of one term of the sum of squared differences, data digit adjustment, and rounding processing are equivalently executed in one machine cycle. Furthermore, the internal data memory and bus structure in this invention performs two-input/one-way data transfer to the calculation unit in parallel with the calculation, and by combining this with an address generator that generates two-dimensional addresses, To efficiently process calculations on sivector data.

By making the data format of the address generator in the present invention compatible with the data format of the arithmetic unit, data conversion becomes unnecessary in processing such as table lookup and dictionary reference.

The DMA control unit in this invention performs internal calculations and parallel input/output of two-dimensional data from an external data memory, effectively reducing the processing time required for inputting/outputting calculation data.

Finally, the microinstruction set in this invention is an internal one.
1/Vl By uniquely specifying the combination of resource operations, the complexity of program description is eliminated.

Number of data digits, 8 and source for each microinstruction.

By specifying the destination address generation formula, it is possible to directly control the digit v4 arrangement of complex data operations and the scanning method of various data memories. Therefore, it is possible to minimize the need to consider the context of commands, simplify program description, and facilitate writing in striped language (for example, C language).

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram schematically showing a digital signal processing processor according to the present invention, and in FIG. 9, (1
00) is an external program bus for connection to an external expansion microinstruction memory, and (101) is an internally implemented writable instruction memory wcs.

(102) is a sequence control unit that inputs microinstructions read from the external program bus (100) or writable instruction memory W (! B (101), and performs predetermined operation control in the instruction execution pipeline; 10
3) is an address generation unit that generates 2 input/1 output addresses for the data memory in parallel, and (104) has a width of 24 pits each for transferring this 2 input/1 output data in parallel. Three internal data buses (105) are the three internal data buses (104)
) is an external data memory E/F unit that selects one of them and connects it to the external data bus (111), and (106) is an arithmetic unit that is connected to the three internal data buses (104) and performs a predetermined calculation. , (107) has one read port and one
Equipped with a book read/write port and an internal data bus (1
04) is connected to the internal data memory MO.

(108) is similarly an internal data memory Ml, (109)
is a DMA control unit uniquely equipped with an external data memory address generator and an internal data memory address generator.

(110) is an external data bus (111) and internal data memory M O (107) or internal data memory M 1
(108), a DMA bus that performs DMA transfer between
(111) is an external data bus connected to the external extended data memory IJK, (112) is a sequence control unit (1
02) is a reset terminal for inputting a reset signal from the outside, and (113) is an interrupt terminal for inputting an interrupt control signal from the outside.

FIG. 2 is a block diagram showing an example of the configuration of the arithmetic unit (106) in FIG. 1. In FIG. 9, (120) is 3
An X-bus that transfers operand data in the book's internal data bus (104), a Y-bus (121) that similarly transfers operation data, a 2-bus (122) that similarly transfers output data, (123) is a 24-bit word length barrel shifter B-8FT that shifts/rotates input data by a predetermined number of bits in one machine cycle.

(-124) is a 24-bit word length arithmetic and logic unit ALU that performs a predetermined arithmetic and logic operation or calculates the absolute difference value in one machine cycle, and (125) performs 24-bit multiplication in one machine cycle. Multiplication i5MPY which outputs the bit result, (126) is arithmetic logic unit A
The data pipeline register DPRO (127) is a barrel system for temporarily holding the output of the amount of L U (124) and outputting it to the square input port of the 0 multiplier MPY (125) to calculate the difference square. 7riB-8IF
Selects one of the 24-bit outputs of the arithmetic and logic unit ALU (124) to select one of the 24-bit outputs of the T (123), and selects one of the 24-bit outputs of the arithmetic logic unit ALU (124), and selects one of the 24-bit outputs of the arithmetic logic unit ALU (124),
129), (12B) is a data pipeline register DPR2, (129) which temporarily holds the 4T bit output of multiplication a MPY (125).
) is a multiplexer (data pipeline register D P R1 that temporarily holds the 24-bit output of 12υ, (
150) is the data pipeline register DPR1
Select and input either the 24-bit data from (129) or the 41-bit data from data pipeline register DPR2 (128), '/! Normalization barrel shifter N-8FT (151
) is this normalization barrel shifter N-Elν'I' (1
30) O24-bit output, (152) is the 24-bit accumulation output from working register wr (135), (133) is the accumulation/rounding adder AU, (1
54) is the 24-bit result output of this accumulation/rounding adder AU (153), and (135) is the 24-bit x 8
Word-structured working register Wr, (156
) is the flag output of the arithmetic logic operation l5ALU, (15
7) is a flag check circuit that performs a condition test on this flag output (136), and (158) is a 24×1 bit condition test shift register tcsr that sequentially stores the 1-bit truth/false judgment result that is the output of this flag check circuit.
, (139) is the normalization barrel shifter N-8F
This is a 1-bit carry that outputs the most significant bit shifted out as is when the L8B direction, that is, right shift is instructed at T (150).

FIG. 3 is a diagram explaining the relationship between the internal data memory and the internal data bus of the digital signal processing processor shown in FIG.
107) 24-bit data from the read port of
A demultiplexer (141) outputs 24-bit data from the read port of the internal data memory M1 (108) to one of the X-bus (120) and the Y-bus (121). (121
) Demultiplexer that outputs to one side.

(142) is the 2-bus (122) or DMA bus 2 (
A multiplexer (143) selects one of the write data of the 2-bus (110) and outputs it to the read/write port of the internal data memory MO (107).
122) or a multiplexer for selecting one of the write data on the DMA bus (110) and outputting it to the read/write port of the internal data memory M1 (108);
(144) is the write address D address (147) and DM
The internal data memory address air address (148) from the A control unit (109) is transferred to the internal data memory M O (107).
) or the read/write port of the internal data memory M 1 (108). (145) is the read port address of the internal data memory M 1 (107). S is
O air address (14t5) is internal data memory M1
S1 address which is the read port address of (108), (147) is the internal data memory M O (107)
The write address (148) for the internal data memory M1 (108) is the ``DMA bus (110).
) is an air address that is an internal data memory address corresponding to the data transferred from the address.

FIG. 4 is a diagram illustrating the configuration of the address generation section (103) in FIG. (151) is a 24-bit x 4-word address register AR, and (152) is a 12-bit x 4-word index modification register I.
X R, (153) is the address register A R (151
) and the data input/output bus of the X-bus (120), (1
54) is the index modification register I
) and the data input/output bus of the x-bus (120), (1
55) is a 24-bit word length address adder, (15
+5) is address generation i1A G with 3 independent systems
U, (157) is a write address pipeline register DAPR3 which delays a 24-bit write address by one machine cycle. Similarly, (158) is a write address pipeline register DAPR4.

FIG. 5 is a diagram explaining the instruction execution pipeline consisting of five stages of the digital signal processing processor shown in FIG. 1. (160) is a machine cycle consisting of four phases, (161) is a stage, ,
(162) is the decode stage, and (165) is the address update timing in the second half of the decode stage.

(164) is a read stage, and (165) is an execution stage.

(, 166) is the normalization timing in the first half of the write/accumulate stage, and (167) is the write/accumulate stage.

FIG. 6 is a diagram showing a part of an example of a microinstruction set of the digital signal processing processor shown in FIG. 1. In FIG. Source operation instruction, (1
75) is 2 Saone operation instructions, and (17) is a source instruction code.

(175) is the destination instruction code, (1
7(S) is the source 0 instruction code, and (177) is the source 1 instruction code.

Next, the operation will be explained. Hereinafter, the abbreviations used in the above description will be used for the names of each part.

First, the overall general operation will be explained with reference to FIG.

The digital signal processing processor according to the present invention has a program bus (100) and a data bus (104) as in the conventional example.
has a separate configuration, and a sequence control unit (102)
Microinstruction input to the arithmetic unit (106) via the data bus (104), data input/output to the arithmetic unit (106), address generation unit (1
Parallel generation of 2 input I11 output data addresses by 03), internal data memory M O (107), Ml (1
08) or external data memory accesses (105) are executed in parallel by microinstructions. Furthermore, the internal data memories M O (107) and M 1 (1
08) and the external data memory/F (105). Here, each execution unit is a regina tabe, similar to the conventional example. Since most instructions in this processor do not require delayed operation, a data input/output stage is included in the instruction execution pipeline. Therefore, if we consider the case where addition is performed in the arithmetic unit (106), for example, 6 inputs.

The addition instruction, including the output, can be executed using one microinstruction. Therefore, even a program that combines various operations can equivalently execute one microinstruction in one machine cycle.

However, the instruction execution result can be used after three instruction steps corresponding to the difference in the number of stages from the read stage of the next instruction. In this processor, most of the operations whose results need to be used immediately, including the meaning of avoiding loss due to this, are performed as compound operations, and are handled by one instruction.

Therefore, this loss does not occur in most programs. The data word length and format of the arithmetic unit (input and address generation unit (103)) are the same and are completely compatible.

Therefore, in processing such as table lookup and dictionary reference, calculation results can be directly converted into data memory addresses.

Next, the function of the calculation section (106) will be explained based on FIG. B-B'IP T (125), A r, +
U (124) and MPY (125) can all operate in one machine cycle, and operate in the execution stage of the instruction execution pipeline stage. In the next stage, the write/accumulate stage, N-8F T (15
Adjust the number of digits in 0) and output the result (1!11) to the 2-bus (122) and write it to the data memory, or
Contents (15) of vrr (135) by AU (135)
2) and perform accumulation or rounding and write the result (154) again.
(155) Can be set. Here, D
PRI (129) and DPR2 (128) are registers that transfer results to the next stage. With this configuration, for example, a compound operation is executed as follows.

Sum of products: MPY (125) → DPR2 (128) → N-
8IFT (150) → AU (155) → Wr (155) Sum of absolute differences: ALU (124) - eMUX (127
) → DPR1 (129) → N-8FT (150) → At
e (155) → Wr (155) Difference square phase: ALU (124) → DPRO (126)
→MPY(125)→DPR2(12B)→N-EIF
Regarding the sum of squared differences T(150)→AU(155)→Wr(155), a delay operation is performed using D P RO(126). However, this command is only used consecutively in most cases, and 69. This problem can be ignored.

When rounding is performed using one processor, the following procedure is used.

1: Carry (159) In other words, the most significant bit of the data shifted out by B-8FT (150) is a carry, and AU (1
Rounding processing can be performed by executing carry addition in step 55). Therefore, the output light as a result of rounding is wr(155
).

Next, the flag check circuit (157) runs Ar, +σ(1
24), the result of the comparison operation is 7 lags (156), and a 1-pinto flag indicating whether 1 condition is satisfied is output according to the condition code specified by the microinstruction.

tcsr (158) in sequence. For example, when determining the maximum and minimum data values for two inputs, a history of which one was selected can be stored. This tCar(15
The content set in B) viewed horizontally from MOB to LSB corresponds to the index code in binary tree search.

The configuration of the internal data memory will be explained based on FIG. M
O(107) and M 1 (108) are each 2
It is a 2-bot RAM with 4 pits x 512 words, and when outputting 2 input data to the calculation section (106) in parallel, M
O(107), M1(108) read port output is set L//Y(140), (141)
By x-ba, K (120) Y-++ Hanu (
121). At this time, the addresses are so address (145), M O (107), and S1 address (
145) is output to M 1 (108). Furthermore, when both the source and destination data memories are targeted, as in vector addition, ie, 7+7→, 2-bars, E (122) to M U X (142) to M
M O (107) to M 1 through UX (145)
Data is written from the read/write port of (108). That is, no bus contention occurs regarding internal operations.

The structure of the address generation section (concave 9) will be explained based on FIG.
Three systems of A and G, each responsible for generator and D address generation.
Consists of U (156). Each AGU is equipped with a 24-pin x 4-word AR (151) and a 12-bit x 4-word AR (152).9. AR(
Two-dimensional address generation is possible by performing a combination of additions of three terms: 151), X X R (152), and displanemen (1, 50) using address addition 6 (iss).

Note that the operation of A
3 (157), 2 by DA, PH1 (158)
It is delayed by machine cycles and output from AGU (15<S). A R (151).

X X R (152) is each kX-bar, 2 (120)
K connected.

The data format is compatible with the arithmetic unit (106). Therefore, for example, when performing a table lookup, data is directly transferred from Wr (155) to AR (151) via the X-bus (120), and then sent directly to S
Address addition may be performed using the O address (145) to the S1 address (146).

The instruction execution pipeline of this processor will be explained based on FIG. The instruction execution pipeline consists of five stages for each instruction.

■ Fetch stage (161) Program counter output and 1-word (48-bit width) microinstruction read.

■ Decode stage Microinstruction decode (162) and address addition (165) - ■ Read stage (164) Source data such as data memory or register 2 (X-P, 2 (120), Y-B, K (121) ).

■ Execution stage (165) B-8FT (125), ALU (124), M
Calculation by PY(125).

■ Normalization (166) and A by write/accumulation stage N-8FT (150)
Round/accumulate or 2-bus (by TT (155)
122) to the data memory via ATT (155) or 2 in the write/accumulate stage of
- Timing of data writing via bus (122) (
167) means that the output of A U (155) is W
This is because there is an exclusive relationship in which when only r (155) is set and 2-bus (122) is used, AU (155) is not used.

By executing instructions according to the above sequence, it is almost unnecessary to create a program that takes complicated delays into consideration, and it is possible to create an efficient microprogram even using a high-level language compiler.

The microinstructions of this processor are as shown in FIG. 6, for example, and are all 1-word horizontal instruction sets with a word length of 48 bits. This instruction set does not instruct internal resources that can operate simultaneously in parallel, but uses function codes that define combinations of resource operations at each stage in response to instructions. This simplifies the writing of microinstructions.

This instruction set can be broadly divided into load (170), branch (170), and branch (170).
71), 1 Saone operation (172), 2 Saone operation (175), corresponding to 0 function code, source code (174) for controlling source denutation,
The denutainment code (175), source 0 code (176), and source 1 code (177) are set. Each of these codes becomes an addressing instruction code for the corresponding AGIT (156) in the address generator (105) when the data memory is targeted. This identification is done by a resource code. With this instruction set, for example, it is possible to switch the addressing mode, change the settings of the normalization shift value, etc. for each calculation instruction, and even when programming complex signal processing algorithms, it is possible to write them with minimal loss.

For example, when executing the binary tree search shown in FIG. 10 as in the conventional example, with one processor, the calculation of the degree of proximity can be programmed as follows.

ap N (aubaa aco, scl, wrz) N
Repeat SCO: Input vector address control 8ei: Reference vector address control Wrz: Working register designation The number of machine cycles required for this is N+1 cycles, and if you repeat this twice, you will be able to get close to the reference vector in direction O1 and direction 1. The following is required. The process of determining the node number of the first stage by determining the next busyness or the next highest node number can be described as follows.

cmp*gs wro, wrl Compare and set the result to tcsr, (158) op ap mvr WF2, ar12 Since there are 7 instructions in total, the number of machine cycles required per stage is 2N+9 machine cycles. It is clear that this is a highly efficient process that almost matches the ideal value, and the program is also simple.

In the above embodiment, the word length is 16 MW (24 pinto) in a 24-bit address space, but other word lengths and data formats may be used.

Also, in the above embodiment, binary tree search was explained, but
Other signal processing algorithms also produce the same effect as the above embodiment.

It is clear that the detailed specifications of the above embodiments are irrelevant to the essence of the present invention and do not limit the content of the present invention.

〔Effect of the invention〕

As described above, according to the present invention, a digital signal processing processor can be highly adapted, and therefore a high-speed signal processing system can be configured flexibly and easily. be satisfied.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital signal processing processor according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of the arithmetic unit in FIG. 1, and FIG. 3 is a diagram showing the internal data in FIG. 1. FIG. 3 is a diagram illustrating a memory configuration. FIG. 4 is a diagram showing the configuration of the address generation section in FIG. 1, and FIG. 5 is a diagram explaining the instruction execution timing of the digital signal processing processor shown in FIG. 1. 6 is a diagram showing an example of a microinstruction set of the digital signal processing processor shown in FIG. 1, FIG. 7 is a block diagram showing the configuration of DS8P1, which is an example of a conventional digital signal processing processor, and FIG. is a diagram explaining the instruction execution timing of this DB8P1, and Figure S is a diagram explaining the instruction execution timing of this DB8P1.
10 is a diagram illustrating the operation of binary tree search, and FIG. 11 is a diagram illustrating an example of the arrangement of reference vectors in the data memory in FIG. 10. (100) is the program bus, (101) is WaS
. (102) is a sequence control section, (105) is an address generation section, (104) is a data bus, (10
5) is in the external data memory/IF, (106) is the calculation unit, and (107) is MO. (108) is Ml, (109) is the DMA control unit, (
110) is an IBM bus, (111) is an external data bus, (120) is an X-bax, (12 is a Y-ba,
, (122) is 2-bus. (125) is B-8IPT, (12 is ALU, (
125) is MPY, (126) is DPRO, (127
) is MUX. (128) is I) PH1, (129) is DPRI, (
150) is N-8IFT, (155) is AU, (1
55) is drunkenness, (159) is "?-?lJ, (14)
0) is DMX, (141) is DMX. (142) is M U! , (145) is M U! ,
(144) is 2-2 selector, (145) is SO
addressnu, (14t5) is s1 address; x, (
147) is D7 dollar l/7. (148) is Airdrain, (150) is Dayne Plainement, (15
1) is AR, (152) is I X R, (155) is A
Ota Kapanu from the X-bus (120) to R (151), (154) is the input/output Panu from the X-bus (120) to E 156) is AGU. (157) is DAPFj3. (158) is D A P
R4, (160) is machine cycle, (161)
is fetch timing. (162) is the decode timing, (165) is the address update timing, and (164) is the read timing. (165) is execution timing, (166) is normalization timing, (IS7) is write/accumulate/
rounding timing. (170) is a load instruction, (171) is a branch instruction,
(172)゛ is an example of one Saone operation instruction, (1
75) is an example of a 2-Saone operation instruction, (174) is a Saone code, (175) is a denutation code, and (176) is a Soak 0 code. (177) is the source 1 code. In Figure 1, the same reference numerals indicate the same or corresponding parts.

Claims (13)

[Claims] (1) An instruction memory in which microinstructions that define various internal operations are written in advance; an instruction reading unit that reads out the microinstructions from the instruction memory every machine cycle via a program bus; step 1
a sequence control unit that executes one word of the microinstruction every machine cycle by dividing the pipeline into a five-stage pipeline for reading instructions, decoding data, reading operations, writing data, or accumulating each machine cycle; and the five-stage pipeline. a plurality of data input buses for transferring two input data corresponding to a binary operation in parallel in the data read stage in the middle, and a plurality of data input buses in the two stages of operation execution data writing or accumulation in the five-stage pipeline; an arithmetic unit that performs various single operations or compound operations on two input data transferred from the arithmetic unit; a plurality of working registers that store the arithmetic results of the arithmetic unit and are capable of reading data from the data input bus; Selecting one or more data output buses for transferring the output data of the arithmetic unit in the data write/accumulation stage of the stage pipeline, and selecting one of the working register or the data output bus for the output of the arithmetic unit. It has an output control unit that outputs data, a read-only port, and a read/write port. Data can be read or written from both ports at the same time, and the data corresponding to each term of a binary operation and its operation results can be read individually and in blocks. a read control unit that selects one or more of the read-only ports of the plurality of two-port memories and reads input data from the plurality of two-port memories to the data input bus; Any one of multiple 2-port memory read/write ports
a write control unit that selects one or more of the data input buses and writes the calculation result; a write control unit that selects one or more of the plurality of data input buses and reads data from an external data memory; and one of the data output buses that selects one or more of the data input buses or an external data memory connection unit for writing data from a plurality of the data memories into the data memory, and the external data memory connection unit for selecting one or more of the read/write ports in the plurality of two-port memories and connecting the external data memory connection unit to the external data memory connection unit. a direct memory transfer bus separate from a data input bus and a data output bus;
a direct memory transfer control unit that inputs and outputs data between the external data memory connection unit and the two-port memory in units of blocks, independently of internal calculations by the sequence control unit, via the direct memory transfer bus; an external data memory contention control unit that arbitrates connection contention between the external data memory connection unit due to a data input bus, a data output bus, and a direct memory transfer bus; A plurality of address registers and index modification registers are each provided, and read and write addresses for the two-port memory or external data memory are generated in parallel for at least two inputs and one output data for the arithmetic unit in the decoding stage of the five-stage pipeline. An address generation section consisting of a plurality of address generators and a corresponding one of the two-port memory or external data memory connection section are selected according to the read and write addresses outputted from the address generation section, and the five-stage pipe is connected to the five-stage pipe. It is equipped with an address selection instruction unit that instructs a data memory address in synchronization with the read and write stages in the line, and a plurality of transfer address control registers that similarly perform data input/output via the data input bus and control the data transfer range. A digital signal processing processor comprising: a direct memory transfer address generation section that generates in parallel both the two-port memory address used for direct memory transfer and an address for an external data memory connection. (2) In the calculation section and address generation section, the data input/output word length and data format in the calculation section and the word length and data format of the address register and address operation in the address generation section are unified, and the calculation data is used as an address as is. 2. The digital signal processing processor according to claim 1, wherein the digital signal processing processor is capable of performing the following operations. (3) In the arithmetic unit, the data is inputted from the data input unit, and the input data can be shifted or rotated by an arbitrary number of bits in one machine cycle, and the result can be logically operated on other input data, as well as a 2-input barrel shifter. An arithmetic logic unit that can perform at least addition, subtraction, and absolute difference calculation on data in one machine cycle, and similarly performs multiplication on two input data and square operation on one input data in one machine cycle. a multiplier, a register that selects and temporarily holds any one of the arithmetic result output of the barrel shifter, arithmetic logic unit, and multiplier; A normalization barrel shifter that adjusts the number of data digits by shifting a predetermined number of bits, and the output of this normalization barrel shifter and one of the plurality of working registers are selected and accumulated in at most 1/2 machine cycle. and a data output section that transfers the output of the normalization barrel shifter to the data output bus in at most 1/2 machine cycle when the adder is not used, In the execution stage, any one of the barrel shifter, the arithmetic logic unit, and the multiplier is operated to execute various arithmetic and logic operations and absolute difference calculations, and in the execution stage, the result of calculating the difference in the arithmetic logic unit is calculated. 1
The difference is squared in one machine cycle by holding it in the time register and performing squaring in the multiplier, and the result of the execution stage is sent to the normalization barrel shifter in the data writing or accumulation stage in the five-stage pipeline. If accumulation is to be performed after adjusting the number of digits, the adder is used to accumulate the data, and if not, the data is directly output to the data output bus. Claim 1, characterized in that a computation or a complex computation such as a sum of products, a sum of absolute differences, a sum of squared differences, etc. is executed.
The digital signal processing processor described in . (4) In each address generator in the address generation section, write an initial value for address generation from the data input bus to the address register, write an index modification value from the data input bus to the index modification register, and After adding the relative address change amount instructed by the microinstruction to the address register, the content of the address register is updated by the result, and at the same time, this is set as a data memory address. , Claim 1 is characterized in that two-dimensional or various address instructions are realized by a combination of a plurality of micro-instructions by sequentially instructing the address generation mode for each micro-instruction to each of the address generators. The digital signal processing processor described in . (5) In the direct memory transfer control unit and the direct memory transfer address generation unit, the address instruction for the external data memory connection unit is specified in a two-dimensional data address space of m rows by n columns (m and n are positive integers). The configuration is such that rectangular portions of k rows and l columns (k and l are positive integers) are sequentially designated, and addresses for the plurality of 2-port memories are designated in ascending order from an arbitrary starting address, and the highest order among these addresses is designated in ascending order. 2-dimensional data transfer between an external data memory and the 2-port memory by configuring the 2-port memory to select one of the 2-port memories by having one or more bits located at , and when starting this direct memory transfer, the transfer direction and the number of data to be transferred are instructed by a microinstruction, and when finishing, the direct memory transfer control section sends an instruction to the sequence control section to complete the transfer. The digital signal processing processor according to claim 1, wherein the digital signal processing processor performs data input/output with an external data memory and internal arithmetic processing in parallel in units of rectangular blocks of k rows and l columns. . (6) When performing conditional branching in the sequence control unit,
A plurality of conditions are stored in a register in advance, and an instruction memory address to be branched when the condition is satisfied is stored in advance in a register corresponding to the condition, and the plurality of conditions are checked in parallel under instructions from a microinstruction. , branches to the instruction memory address in the register corresponding to the condition with the highest priority among those for which the conditions are met, and if all conditions are not met, branches to the instruction memory address in the register corresponding to this. Claim 1 is characterized in that by doing so, branching based on multiple conditions can be realized with one microinstruction.
The digital signal processing processor described in . (7) The sequence control unit includes a loop counter and a repeat counter capable of inputting initial values and outputting contents from the data input bus, and when a repeat is instructed by a microinstruction, the contents of the repeat counter are , subtract 1 for each microinstruction and execute the same microinstruction repeatedly until it becomes zero, and if a loop is instructed by a microinstruction, subtract 1 from the contents of the loop counter, and if it is not zero, Branch to the instruction memory address specified by the microinstruction, and if it is zero, do not branch and terminate the loop operation to execute a single microinstruction or multiple microinstructions a predetermined number of times. The digital signal processing processor according to claim 1, wherein the digital signal processing processor is repeatedly executed. (8) In the external data memory connection section, the external data memory is divided into two parts using the address set in advance by a microinstruction as a boundary, and when one of the two parts is to be addressed, one
It is a high-speed memory that completes reading/writing in a machine cycle, and when addressing the other side, reading/writing from outside is required.
The digital signal processing processor according to claim 1, characterized in that the low-speed memory waits until a write completion signal is detected. (9) The instruction memory has a configuration in which part or all of the instruction memory can be rewritten, and microprograms corresponding to functional processing can be written from an external device to this rewritable instruction memory to perform complex and various types of processing. 2. The digital signal processing processor according to claim 1, wherein the microprogram is realized by the same processor, and when the microprogram is not executed, the microprogram is written autonomously from an externally provided read-only memory. (10) In the microinstruction, a function code that uniquely defines the operation of each stage in the five-stage pipeline corresponding to the type of operation, and an address generation mode of the address generation unit in the address generation unit are specified for each microinstruction. at least 2
Input specification codes and output specification codes that individually specify input/1 output or 1 input/1 output data memory correspondence, and resource specification codes that specify whether the data input/output target is data memory or register. , characterized in that a microinstruction set is formed by a combination of the number of shift bits of the normalization barrel shifter in the arithmetic unit, and a test condition code, immediate value data, and holding condition code that are instructed depending on the type of operation. A digital signal processing processor according to claim 1. (11) Arbitrarily allocate an address for communication between processors in the external data memory address, and provide an external first-in/first-out memory or 2-port memory for communication at this address to connect the same processor or other processors. 2. The digital signal processing processor according to claim 1, wherein high-speed and complicated processing is realized by a plurality of processors. (12) In the normalization barrel shifter and adder in the arithmetic unit, when adjusting the number of digits by shifting toward the least significant bit in the normalization barrel shifter, the data corresponding to the number of shifted bits from the least significant bit is truncated as a result of the shift. A mode is provided in which the most significant bit of the data is set as a carry or borrow bit, and the adder performs addition with carry or borrow on the working register or zero data to perform accumulation with data rounding or data rounding operation. , wherein whether or not to use this mode is instructed by mode setting for the adder or direct control by microinstructions. Digital signal processing processor. (13) In the arithmetic logic unit in the arithmetic unit, when comparing the magnitude of two input data or inspecting a specific bit in the input data, the comparison result inspection conditions specified in the microinstruction (e.g. (2 input data are equal, etc.) is established, and the test results are sequentially stored from one direction of the shift register for each microinstruction,
The contents of this shift register viewed from the horizontal direction are read from the data input bus, and the multiple judgment results obtained by executing the microinstruction multiple times are used as a search history code in tree search or for branching operations under multiple conditions. A digital signal processing processor according to claim 1 or 3.