JP7413906B2 - Inverter and rectifier circuit - Google Patents

Description

The present invention relates to an inverter and a rectifier circuit.

The conventional half-bridge inverter shown in FIG. 7 has a DC power supply Vi connected to a series circuit of a second capacitor C2 and a first capacitor C1, and a series circuit of a second switching element Q2 and a first switching element Q1. are connected in parallel. A series circuit of an inductance Lo and a capacitor Co is connected between a connection point between the second capacitor C2 and the first capacitor C1 and a connection point between the second switching element Q2 and the first switching element Q1. . Both ends of the capacitor Co are connected to the output terminal of the inverter.

Next, the operation of the inverter will be explained. The switching elements Q1 and Q2 are switched by gate drive signals Vgs1 and Vgs2 from a control circuit (not shown). As shown in FIG. 8, the gate drive signals Vgs1 and Vgs2 are generated from the gate control PWM signals Vgs1' and Vgs2' of the switching elements Q1 and Q2. A carrier frequency that determines the switching frequency is generated as a triangular waveform, and a commercial frequency sine wave is generated as the target output voltage waveform. This sine wave compares the output voltage Vo with a reference sine wave, and the difference is amplified and fed back to adjust the amplitude of the target sine wave. As shown in FIG. 8, the target sine wave and the triangular waveform of the carrier frequency are compared by a PWM comparator (not shown) to generate gate drive signals Vgs1' and Vgs2'. Vgs1' and Vgs2' are symmetrical waveforms whose phases differ by 180°.

As shown in FIG. 9, the gate drive signals Vgs1 and Vgs2 of switching elements Q1 and Q2 are slightly adjusted to Vgs1' and Vgs2' at the end of waveform generation so that switching element Q1 and switching element Q2 are not turned on at the same time. A dead time is provided in which both are turned off.

By driving the switching elements Q1 and Q2 with such a gate drive signal, the output voltage Vo has a voltage of -1/1 on the L side of the output Vo when the PWM duty of the switching element Q1 is 100%, with the N side as a reference. 2Vi is output, and when the PWM duty is 50%, 0V is output to the L side of the output Vo when the N side is referenced, and when the PWM duty is 0%, 1/2Vi is output to the L side of the output Vo when the N side is used as the reference. Output. That is, a sine wave voltage can be output as the output voltage Vo using the PWM signal. For example, if the output voltage is AC100V, the peak voltage is 100V*√2=141V, so a DC power supply Vi of twice that value, 282V or more, is required.

Further, as shown in FIG. 10, the full-bridge inverter includes a DC power supply Vi, a series circuit of a fourth switching element Q4 and a third switching element Q3, a series circuit of a second switching element Q2 and a first switching element A series circuit of element Q1 is connected. A series circuit of an inductance Lo and a capacitor Co is connected between a connection point between the fourth switching element Q4 and the third switching element Q3 and a connection point between the second switching element Q2 and the first switching element Q1. ing. Both ends of the capacitor Co are connected to the output terminal of the inverter.

In this case, switching elements Q1, Q2, Q3, and Q4 are controlled by gate drive signals Vgs1, Vgs2, Vgs3, and Vgs4 from a control circuit (not shown). These gate drive signals Vgs1, Vgs2, Vgs3, Vgs4 have a duty of 50% synchronized with the gate control PWM signals Vgs1', Vgs2' of switching elements Q1, Q2 and the output commercial frequency of switching elements Q3, Q4, respectively. It is generated from control signals Vgs3' and Vgs4' whose phases differ by 180°.

One generates a triangular waveform as the carrier frequency that determines the switching frequency, and the other generates a commercial frequency sine wave as the target output voltage waveform. This sine wave compares the output voltage Vo with a reference sine wave, and the difference is amplified and fed back to adjust the amplitude of the target sine wave. The target sine wave is determined by comparing the triangular waveform of the carrier frequency on the positive side when the third switching element Q3 is on, and on the negative side when the fourth switching element Q4 is on, using a PWM comparator (not shown), and generates the gate drive. Generate signals Vgs1' and Vgs2'.

As shown in FIG. 9, the gate drive signals Vgs1 and Vgs2 of the switching elements Q1 and Q2 are set to Vgs1' and Vgs2' at the end of waveform generation so that the switching elements Q1 and Q2 are not turned on at the same time. A dead time is provided in which both are turned off.

Here, when the target sine wave is on the positive side, the gate drive signal Vgs3' of the third switching element Q3 is generated at H level, and when the target sine wave is on the negative side, the gate drive signal Vgs4 of the fourth switching element Q4 is generated. 'H is generated. Furthermore, if the output voltage is AC100V, the peak voltage is 100V*√2=141V, so a DC power supply Vi of 141V or higher is required.

Further, a conventional half-bridge type rectifier circuit having a power factor correction function is configured as shown in FIG. A series circuit of the second capacitor C2 and the first capacitor C1, and a series circuit of the second switching element Q2 and the first switching element Q1 are connected to both ends of the DC output voltage Vo, which is the output of the rectifier circuit. ing. A series circuit of an inductance Li and a commercial power supply AC is connected between the connection point between the second capacitor C2 and the first capacitor C1 and the connection point between the second switching element Q2 and the first switching element Q1. There is.

Next, the operation of the rectifier circuit will be explained. The switching elements Q1 and Q2 are switched by gate drive signals Vgs1 and Vgs2 from a control circuit (not shown). As shown in FIG. 8, the gate drive signals Vgs1 and Vgs2 are generated from the gate control PWM signals Vgs1' and Vgs2' of the switching elements Q1 and Q2. FIG. 8 shows a conceptual diagram of generation of PWM signals Vgs1' and Vgs2' for gate control of switching elements Q1 and Q2. One is to generate the carrier frequency that determines the switching frequency as a triangular waveform.

The other is to generate a target sine wave to bring the input current waveform closer to the input commercial power supply frequency waveform (sine wave) in order to improve the power factor of the rectifier circuit. The amplitude of the target sine wave of the target input current waveform is adjusted by comparing the output voltage Vo with a reference DC voltage, and amplifying and feeding back the difference. This target sine wave and the triangular waveform of the carrier frequency are compared by a PWM comparator to generate gate drive signals Vgs1' and Vgs2'. Vgs1' and Vgs2' are symmetrical waveforms whose phases differ by 180°.

As shown in FIG. 9, gate drive signals Vgs1 and Vgs2 of switching elements Q1 and Q2 are set so that both of them are slightly off at Vgs1' and Vgs2' so that switching element Q1 and switching element Q2 are not turned on at the same time. We have a dead time to do this.

By being driven by such a gate drive signal, the output voltage Vo is kept at a constant voltage, and the input current Ii has a current waveform similar to that of the commercial power supply AC that is the input voltage. That is, if the input voltage is a sine wave, a similar sine wave waveform will be obtained. Generally, the output voltage Vo is set higher than the peak voltage of the commercial power supply AC, which is the input voltage, and the input voltage is boosted to generate the output voltage Vo.

Further, a conventional full-bridge rectifier circuit having a power factor correction function was configured as shown in FIG. 13. A first capacitor C1, a series circuit of a fourth switching element Q4 and a third switching element Q3, a series circuit of a second switching element Q2 and a first A series circuit of switching element Q1 is connected. A series circuit of an inductance Li and a commercial power supply AC is connected between the connection point between the fourth switching element Q4 and the third switching element Q3 and the connection point between the second switching element Q2 and the first switching element Q1. has been done.

Switching elements Q1, Q2, Q3, and Q4 are controlled in switching by gate drive signals Vgs1, Vgs2, Vgs3, and Vgs4 from a control circuit (not shown). These gate drive signals Vgs1, Vgs2, Vgs3, Vgs4 have a duty of 50% synchronized with the gate control PWM signals Vgs1', Vgs2' of the switching elements Q1, Q2 and the AC frequency of the commercial power supply AC of the switching elements Q3, Q4. The control signals Vgs3' and Vgs4' are generated from control signals Vgs3' and Vgs4' each having a phase difference of 180°. One is to generate the carrier frequency that determines the switching frequency as a triangular waveform. In order to improve the power factor of the rectifier circuit, a target sine wave is generated to bring the input current waveform closer to the input commercial power supply frequency waveform (sine wave). The amplitude of the target sine wave of the target input current waveform is adjusted by comparing the output voltage Vo with a reference DC voltage, and amplifying and feeding back the difference. This target sine wave is generated by comparing the triangular waveform of the carrier frequency with the positive pole side when the third switching element Q3 is on, and the negative pole side when the fourth switching element Q4 is on, using a PWM comparator, and generates the gate drive signal. Generate Vgs1' and Vgs2'. Vgs1' and Vgs2' are symmetrical waveforms whose phases differ by 180°. Note that when the target sine wave is on the positive side, the gate drive signal Vgs3' of the third switching element Q3 is H, and when the target sine wave is on the negative side, the gate drive signal Vgs4' of the fourth switching element Q4 is generated. H is generated.

As shown in FIG. 9, the gate drive signals Vgs1 and Vgs2 of the switching elements Q1 and Q2 are set to Vgs1' and Vgs2' at the end of waveform generation so that the switching elements Q1 and Q2 are not turned on at the same time. A dead time is provided in which both are turned off.

By being driven by such a gate drive signal, the output voltage Vo is kept at a constant voltage, and the input current Ii has a current waveform similar to that of the commercial power supply AC that is the input voltage. That is, if the input voltage is a sine wave, a similar sine wave waveform will be obtained. Generally, the output voltage Vo is set higher than the peak voltage of the commercial power supply AC, which is the input voltage, and the input voltage is boosted to generate the output voltage Vo.

FIG. 14 shows switching voltage and current waveforms in the conventional inverter shown in FIGS. 7 and 10. FIG. 14(a) shows the waveforms of switching voltages VQ1, VQ2 and currents IQ1, IQ2 when the L side of the output voltage Vo is a + voltage, and FIG. 14(b) shows the waveforms of the switching voltages VQ1, VQ2 and the currents IQ1, IQ2 when the L side of the output voltage Vo is a − voltage. FIG. 15 shows switching voltage and current waveforms in the rectifier circuits shown in FIGS. 12 and 13. FIG. 15(a) shows the waveforms of the switching voltages VQ1, VQ2 and currents IQ1, IQ2 when the L side of the commercial power source AC is a negative voltage, and FIG. 15(b) shows the waveforms of the switching voltages VQ1, VQ2 and the currents IQ1, IQ2 when the L side of the commercial power source AC is a positive voltage.

Japanese Patent Application Publication No. 2010-011555 Patent No. 5355756

However, in the conventional inverters shown in FIGS. 7 and 10, during the regeneration period when the current is discharged from the output inductance Lo, the regenerative current flows through the parasitic Di of one of the switching elements. Furthermore, in the rectifier circuits shown in FIGS. 12 and 13 having a conventional power factor correction function, during the regeneration period when current is released from the input inductance Li, the regeneration current flows through the parasitic Di of one switching element. .

At this time, when the other switching element is turned on, a recovery current flows during the recovery period of the parasitic Di, as shown in FIGS. 14 and 15. Parasitic Di in general MOS-FETs has poor recovery characteristics and a large recovery current flows. This means that a through current due to recovery flows in the arms of the upper and lower switching elements.

There are MOS-FETs with improved recovery characteristics for these parasitic Di, but their performance is far inferior to that of a dedicated fast recovery diode. Therefore, switching losses due to these through-currents are large, and the switching frequency cannot be increased. For example, it is often used at a switching frequency of 20kHz or less. For this reason, miniaturization by increasing the frequency is not possible.

An object of the present invention is to provide an inexpensive and small-sized inverter and rectifier circuit that can achieve high frequencies and significantly reduce the size of inductance and capacitance.

In order to solve the above problems, an inverter according to the present invention includes a DC power supply, a series circuit of a second capacitor and a first capacitor, a series circuit of a second diode and a first switching element, and a series circuit of a second capacitor and a first switching element. 2 switching elements and a series circuit of a first diode are connected in parallel, a connection point between the second capacitor and the first capacitor, and a connection point between the second diode and the first switching element. , the first winding and the second winding wound around one magnetic core have the same phase polarity, and the first winding of the inductance and the capacitor are connected in series between one terminal of the inductor. and the second winding and the capacitor are connected between a connection point between the second capacitor and the first capacitor and a connection point between the second switching element and the first diode. are connected in series, a series connection point of the first winding and the second winding is connected to one end of the capacitor, one end of the capacitor is connected to one end of the inverter output, and the other end of the capacitor is connected to one end of the inverter output. It is characterized in that it is connected to the other end of the inverter output.

Further, the rectifier circuit according to the present invention includes a series circuit of a second capacitor and a first capacitor, a series circuit of a second diode and a first switching element, and a second switching element connected to both ends of the output voltage. The element and a series circuit of a first diode are connected in parallel, and between a connection point between the second capacitor and the first capacitor and a connection point between the second diode and the first switching element. In this case, the first winding and the second winding wound around one magnetic core have the same phase polarity, and the first winding of the inductance and the commercial power supply are connected in series with one terminal of the inductance connected. a series connection point between the first winding and the second winding is connected to one end of the commercial power supply, a connection point between the second capacitor and the first capacitor and the second switching element; The second winding and the commercial power source are connected in series between the first diode and the first diode.

According to the present invention, it is possible to provide an inexpensive and small-sized inverter and rectifier circuit that can realize high frequencies and make it possible to significantly reduce the size of inductors and capacitors.

FIG. 1 is a circuit diagram of a half-bridge inverter according to a first embodiment of the present invention. FIG. 3 is a waveform chart showing voltages and currents of each switching element of the half-bridge inverter according to the first embodiment. FIG. 3 is a circuit diagram of a full-bridge inverter according to a second embodiment of the present invention. FIG. 7 is a circuit diagram of a half-bridge rectifier circuit according to a third embodiment. FIG. 7 is a waveform diagram showing voltages and currents of each switching element of a half-bridge rectifier circuit according to a third embodiment. FIG. 7 is a circuit diagram of a full-bridge rectifier circuit according to a fourth embodiment. FIG. 1 is a circuit diagram of a conventional half-bridge inverter. 8 is a waveform diagram of gate drive signals of each switching element of the conventional half-bridge inverter shown in FIG. 7. FIG. FIG. 3 is a waveform diagram of a gate drive signal to which dead time is added. FIG. 1 is a circuit diagram of a conventional full-bridge inverter. 11 is a waveform diagram of gate drive signals of each switching element of the conventional full-bridge inverter shown in FIG. 10. FIG. FIG. 2 is a circuit diagram of a conventional half-bridge rectifier circuit. FIG. 2 is a circuit diagram of a conventional full-bridge rectifier circuit. FIG. 2 is a waveform diagram showing voltage and current of each switching element of a conventional half-bridge inverter. FIG. 2 is a waveform diagram showing voltage and current of each switching element of a conventional full-bridge rectifier circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Inverters and rectifier circuits according to embodiments of the present invention will be described in detail below with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram of a half-bridge type inverter according to a first embodiment of the present invention. In FIG. 1, a DC power supply Vi includes a series circuit of a second capacitor C2 and a first capacitor C1, a series circuit of a second diode D2 and a first switching element Q1, and a second switching element Q2. A series circuit of the first diode D1 is connected in parallel. The first switching element Q1 and the second switching element Q2 are made of, for example, a MOSFET.

A first capacitor wound around one magnetic core is connected between the connection point between the second capacitor C2 and the first capacitor C1 and the connection point between the second diode D2 and the first switching element Q1. The winding Lo1 and the second winding Lo2 have the same phase polarity, and the first winding Lo1 with an inductance Lo connected between one terminal and the capacitor Co are connected in series. The inductance Lo is an integrated divided choke coil.

A second winding Lo2 and a capacitor Co are connected in series between the connection point between the second capacitor C2 and the first capacitor C1 and the connection point between the second switching element Q2 and the first diode D1. ing. A series connection point between the first winding Lo1 and the second winding Lo2 is connected to one end of the capacitor Co. One end of the capacitor Co is connected to one end of the inverter output, and the other end of the capacitor Co is connected to the other end of the inverter output.

The control circuit 10 alternately turns on and off the first switching element Q1 and the second switching element Q2 at a high frequency with a dead time provided.

The inductance Lo is composed of a first inductance Lo1 made of a first winding and a second inductance Lo2 made of a second winding, and the degree of coupling between the first inductance Lo1 and the second inductance Lo2 is less than 1. It is. A first leakage inductance Lr1 is formed as the leakage inductance of the first inductance Lo1, and a second leakage inductance Lr2 is formed as the leakage inductance of the second inductance Lo2.

Furthermore, a diode D2 is provided to regenerate the surge voltage generated in the leakage inductance Lr1 to the DC power supply Vi. A diode D1 is provided for regenerating the surge voltage generated in the leakage inductance Lr2 to the DC power supply Vi.

Next, the operation of the half-bridge type inverter according to the first embodiment configured as described above will be explained. First, a description will be given using a timing chart shown in FIG. 2A in which the N side of the output voltage Vo is a reference and the L side of the output voltage Vo is a + voltage.

If the degree of coupling between the first inductance Lo1 and the second inductance Lo2 is 1, the leakage inductance Lr1 and the leakage inductance Lr2 are zero. In the half-bridge type inverter according to the first embodiment, the degree of coupling of the first inductance Lo1 and the second inductance Lo2 is set to less than 1 by split winding or the like.

As a result, a leakage inductance Lr1 is formed in the first inductance Lo1 as its leakage inductance, and a leakage inductance Lr2 is formed in the second inductance Lo2 as its leakage inductance.

First, at time t2, the first switching element Q1 is turned on and the second switching element Q2 is turned off. At this time, current IQ1 flows along the path Lo1→Co→C1→Q1→Lr1→Lo1. Next, at time t3, the first switching element Q1 is turned off and the second switching element Q2 is turned on. At this time, current IQ2 flows through the path C2→Q2→Lr2→Lo2→Co→C2.

Next, the operation will be described when the output voltage Vo shown in FIG. 2(b) is set to the N side of the output voltage Vo as a reference and the L side is − voltage.

First, at time t2, the first switching element Q1 is turned off and the second switching element Q2 is turned on. At this time, current IQ2 flows through the path Lo2→Lr2→Q2→C2→Co→Lo2. Next, at time t3, the second switching element Q2 is turned off and the first switching element Q1 is turned on. At this time, current IQ1 flows through the path C1→Co→Lo1→Lr1→Q1→C1.

A first inductance Lo1 and a second inductance Lo2 are inserted into the through current path between the first switching element Q1 and the second switching element Q2, and the first inductance Lo1 and the second inductance Lo2 have the same mode polarity. Since the voltage of the first inductance Lo1 and the voltage of the second inductance Lo2 cancel each other out, the voltage between the first inductance Lo1 and the second inductance Lo2 is approximately zero. .

Furthermore, since at least one of leakage inductance Lr1 and leakage inductance Lr2 exists in the through-current path between the first switching element Q1 and the second switching element Q2, recovery is achieved by the impedance of leakage inductance Lr1 and leakage inductance Lr2. Current can be suppressed.

As shown in FIGS. 2A and 2B, at time t3, the relaxation current due to recovery can be significantly reduced in currents IQ1 and IQ2 of switching elements Q1 and Q2.

As described above, according to the inverter according to the first embodiment, the first winding Lo1 and the second winding Lo2 wound around one magnetic core have the same phase polarity, and one terminal is connected to the other. Since an integrated divided choke consisting of an inductance Lo is placed between the bridge connections, the recovery current can be suppressed by the leakage inductances Lo1 and Lo2 without increasing the number of components. It is possible to provide an inexpensive and compact inverter that can be significantly downsized.

Furthermore, when the switching element Q1 is turned off, the energy stored in the leakage inductance Lr1 is regenerated to C2 along the path Lr1→D2→C2→Co→Lo1→Lr1. When the switching element Q2 is turned off, the energy stored in the leakage inductance Lr2 is regenerated to C1 along the path Lr2→Lo2→Co→C1→D1→Lr2. That is, since the regenerative diodes D1 and D2 are added to the power supply line from the connection points between the switching elements Q1 and Q2 and the windings Lo1 and Lo2, a path for the regenerative current flowing through the inductance Lo can be secured.

(Second embodiment)
FIG. 3 is a circuit diagram of a full-bridge inverter according to a second embodiment of the invention. In FIG. 3, a DC power supply Vi includes a series circuit of a fourth switching element Q4 and a third switching element Q3, a series circuit of a second diode D2 and a first switching element Q1, and a second switching element. Q2 and the series circuit of the first diode D1 are connected in parallel.

A first winding wound around one magnetic core is connected between the connection point between the fourth switching element Q4 and the third switching element Q3 and the connection point between the second diode D2 and the first switching element Q1. The first winding Lo1 and the capacitor Co are connected in series, with the wire Lo1 and the second winding Lo2 having the same phase polarity and having an inductance Lo connected between one terminal thereof.

A second winding Lo2 and a capacitor Co are connected in series between the connection point between the fourth switching element Q4 and the third switching element Q3 and the connection point between the second switching element Q2 and the first diode D1. It is connected. A series connection point between the first winding Lo1 and the second winding Lo2 is connected to one end of the capacitor Co. One end of the capacitor Co is connected to one end of the inverter output, and the other end of the capacitor Co is connected to the other end of the inverter output.

The control circuit 11 alternately turns the first switching element Q1 and the second switching element Q2 on and off at high frequency with a dead time, and also turns the fourth switching element Q4 and the third switching element Q3 on and off from the commercial power supply. Turn on and off at the frequency.

The inductance Lo is composed of a first inductance Lo1 made of a first winding and a second inductance Lo2 made of a second winding, and the degree of coupling between the first inductance Lo1 and the second inductance Lo2 is less than 1. It is. A first leakage inductance Lr1 is formed as the leakage inductance of the first inductance Lo1, and a second leakage inductance Lr2 is formed as the leakage inductance of the second inductance Lo2.

Furthermore, a diode D2 is provided to regenerate the surge voltage generated in the leakage inductance Lr1 to the DC power supply Vi. A diode D1 is provided for regenerating the surge voltage generated in the leakage inductance Lr2 to the DC power supply Vi.

Next, the operation of the full-bridge inverter according to the second embodiment configured as described above will be explained. If the degree of coupling between the first inductance Lo1 and the second inductance Lo2 is 1, the leakage inductance Lr1 and the leakage inductance Lr2 are zero, and the inverter operates exactly the same as the conventional full-bridge inverter shown in FIG. 10.

In the full-bridge inverter according to the second embodiment, the degree of coupling of the first inductance Lo1 and the second inductance Lo2 is set to less than 1 by split winding or the like.

As a result, a leakage inductance Lr1 is formed in the first inductance Lo1 as its leakage inductance, and a leakage inductance Lr2 is formed in the second inductance Lo2 as its leakage inductance.

In the full-bridge inverter according to the second embodiment, since leakage inductance Lr1 or Lr2 exists in the through-current path between the first switching element Q1 and the second switching element Q2, the leakage inductance Lr1 and the leakage inductance Lr2 The recovery current can be suppressed by the impedance.

As shown in FIGS. 2A and 2B, at time t3, the through current due to recovery can be significantly reduced in currents IQ1 and IQ2 of switching elements Q1 and Q2.

As described above, the inverter of the present invention can limit the through current during the recovery period by the leakage inductance Lr1 or Lr2 even if an inexpensive MOSFET with poor recovery characteristics of the parasitic diode Di is used.

As a result, the through current can be significantly reduced, and the switching loss due to the through current can be significantly reduced. Therefore, higher frequencies, which were previously impossible, become possible. For example, it is possible to increase the frequency from the conventional 20kHz to 100kHz.

These can be achieved by simply adding two new inexpensive FRD elements and using leakage inductance without adding any new inductance, so that cost increases can be suppressed to a minimum.

(Third embodiment)
FIG. 4 is a circuit diagram of a half-bridge rectifier circuit according to the third embodiment. In FIG. 4, a series circuit of a second capacitor C2 and a first capacitor C1, a series circuit of a second diode D2 and a first switching element Q1, and a second switching element are connected across the output voltage Vo. Q2 and the series circuit of the first diode D1 are connected in parallel.

A first winding Li1 wound around one magnetic core is connected between the connection point between the second capacitor C2 and the first capacitor C1 and the connection point between the second diode D2 and the first switching element Q1. and the second winding Li2 have the same phase polarity, and the first winding Li1 of the inductance Li, whose one terminal is connected, and the commercial power supply AC are connected in series.

A series connection point between the first winding Li1 and the second winding Li2 is connected to one end of the commercial power supply AC. A second winding Li2 and a commercial power supply AC are connected in series between the connection point between the second capacitor C2 and the first capacitor C1 and the connection point between the second switching element Q2 and the first diode D1. has been done.

The control circuit 12 alternately turns on and off the switching element Q1 and the second switching element Q2 at high frequency with a dead time provided.

The inductance Li is composed of a first inductance Li1 made of a first winding and a second inductance Li2 made of a second winding, and the degree of coupling between the first inductance Li1 and the second inductance Li2 is less than 1. It is. A leakage inductance Lr1 is formed in the first inductance Li1 as its leakage inductance, and a leakage inductance Lr2 is formed in the second inductance Li2 as its leakage inductance.

Further, a diode D2 is provided to regenerate the surge voltage generated in the leakage inductance Lr1 to the output voltage Vo, and a diode D1 is provided to regenerate the surge voltage generated in the leakage inductance Lr2 to the output voltage Vo.

Next, the operation of the half-bridge rectifier circuit according to the third embodiment configured as described above will be explained. If the degree of coupling between the first inductance Li1 and the second inductance Li2 is 1, the leakage inductance Lr1 and the leakage inductance Lr2 are zero, and the conventional half-bridge rectifier circuit with a power factor correction function shown in FIG. The operation is exactly the same.

In the half-bridge rectifier circuit according to the third embodiment, the degree of coupling of the first inductance Li1 and the second inductance Li2 is set to less than 1 by split winding or the like.

As a result, a leakage inductance Lr1 is formed in the first inductance Li1 as its leakage inductance, and a leakage inductance Lr2 is formed in the second inductance Li2 as its leakage inductance.

Since the leakage inductance Lr1 or Lr2 exists in the through-current path, the recovery current can be suppressed by the impedance of the leakage inductance Lr1 and the leakage inductance Lr2.

As shown in FIGS. 5A and 5B, at time t3, the through current due to recovery can be significantly reduced in currents IQ1 and IQ2 of switching elements Q1 and Q2.

(Fourth embodiment)
FIG. 6 is a circuit diagram of a full-bridge rectifier circuit according to the fourth embodiment. In FIG. 6, a first capacitor C1, a series circuit of a fourth switching element Q4 and a third switching element Q3, a second diode D2 and a first switching element Q1 are connected across the output voltage Vo. The series circuit and the series circuit of the second switching element Q2 and the first diode D1 are connected in parallel.

A first winding wound around one magnetic core between the connection point between the fourth switching element Q4 and the third switching element Q3 and the connection point between the second diode D2 and the first switching element Q1. Li1 and the second winding Li2 have the same phase polarity, and the first winding Li1 having an inductance Li connected between one terminal thereof and the commercial power supply AC are connected in series.

A series connection point between the first winding Li1 and the second winding Li2 of the inductance Li is connected to one end of the commercial power supply AC.

The second winding Li2 and the commercial power supply AC are connected in series between the connection point between the fourth switching element Q4 and the third switching element Q3 and the connection point between the second switching element Q2 and the first diode D1. It is connected to the.

The control circuit 13 alternately turns on and off the first switching element Q1 and the second switching element Q2 with a dead time, and alternately turns on and off the fourth switching element Q4 and the third switching element Q3. Turns on and off at commercial power frequency.

The degree of coupling between the first inductance Li1 and the second inductance Li2 is less than 1, and the first inductance Li1 has a leakage inductance Lr1 formed as its leakage inductance, and the second inductance Li2 has its leakage inductance Lr1 formed as its leakage inductance. As a result, leakage inductance Lr2 is formed.

Further, a diode D2 is provided to regenerate the surge voltage generated in the leakage inductance Lr1 to the output voltage Vo, and a diode D1 is provided to regenerate the surge voltage generated in the leakage inductance Lr2 to the output voltage Vo.

Next, the operation of the full-bridge rectifier circuit according to the fourth embodiment configured as described above will be explained. If the degree of coupling between the first inductance Li1 and the second inductance Li2 is 1, the leakage inductance Lr1 and the leakage inductance Lr2 are zero, and the inverter operates exactly the same as the conventional full-bridge inverter shown in FIG. 13.

In the full-bridge rectifier circuit according to the fourth embodiment, the degree of coupling of the first inductance Li1 and the second inductance Li2 is set to less than 1 by split winding or the like.

As a result, a leakage inductance Lr1 is formed in the first inductance Li1 as its leakage inductance, and a leakage inductance Lr2 is formed in the second inductance Li2 as its leakage inductance.

In the full-bridge rectifier circuit, since the leakage inductance Lr1 or Lr2 exists in the through-current path, these recovery currents can be significantly reduced as shown in FIG.

As explained above, the rectifier circuit with the power factor improvement function of the present invention limits the through current during the recovery period by the leakage inductance Lr1 or Lr2, even if an inexpensive MOS-FET with poor recovery characteristics of parasitic Di is used. can do. This significantly reduces the through current, making it possible to significantly reduce switching loss due to the through current. Therefore, higher frequencies, which were previously impossible, become possible. For example, it is possible to increase the frequency from the conventional 20kHz to 100kHz.

These can be achieved by simply adding two new inexpensive FRD elements and using leakage inductance without adding any new inductance, making it possible to minimize cost increases.

Further, since the present invention can be applied to both an inverter and a rectifier circuit, it can also be applied to a bidirectional inverter.

Vi DC power supply Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element C1 First capacitor C2 Second capacitor Co Capacitor D1 First diode D2 Second diode Li , Lo Inductance Lo1, Li1 First winding Lo2, Li2 Second winding Lr1 First leakage inductance Lr2 Second leakage inductance 10 to 13 Control circuit AC Commercial power supply

Claims (6)

A series circuit of a second capacitor and a first capacitor, a series circuit of a second diode and a first switching element, and a series circuit of a second switching element and a first diode are connected in parallel to a DC power supply. connected to
a first winding wound around one magnetic core between a connection point between the second capacitor and the first capacitor and a connection point between the second diode and the first switching element; The first winding and a capacitor are connected in series, the first winding having the same phase polarity as the second winding, and the inductance having one terminal connected to the other,
The second winding and the capacitor are connected in series between a connection point between the second capacitor and the first capacitor and a connection point between the second switching element and the first diode. ,
A connection point between one terminal of the first winding and the second winding is connected to one end of the capacitor,
An inverter, wherein one end of the capacitor is connected to one end of an inverter output, and the other end of the capacitor is connected to the other end of the inverter output. A DC power supply includes a series circuit of a fourth switching element and a third switching element, a series circuit of a second diode and the first switching element, and a series circuit of the second switching element and the first diode. are connected in parallel,
a first winding wound around one magnetic core between a connection point between the fourth switching element and the third switching element and a connection point between the second diode and the first switching element; and the second winding have the same phase polarity, and the first winding and the capacitor of the inductance are connected in series between one terminal thereof,
The second winding and the capacitor are connected in series between a connection point between the fourth switching element and the third switching element and a connection point between the second switching element and the first diode. is,
A connection point between one terminal of the first winding and the second winding is connected to one end of the capacitor,
An inverter, wherein one end of the capacitor is connected to one end of an inverter output, and the other end of the capacitor is connected to the other end of the inverter output. The inductance includes a first inductance made of the first winding wire and a second inductance made of the second winding wire, and the degree of coupling between the first inductance and the second inductance is less than 1. The inverter according to claim 1 or 2, wherein a first leakage inductance is formed in the first inductance, and a second leakage inductance is formed in the second inductance. . A series circuit of a second capacitor and a first capacitor, a series circuit of a second diode and a first switching element, and a series circuit of a second switching element and a first diode are connected to both ends of the output voltage. are connected in parallel,
a first winding wound around one magnetic core between a connection point between the second capacitor and the first capacitor and a connection point between the second diode and the first switching element; The first winding of an inductance having the same phase polarity as the second winding and connected between one terminal thereof and a commercial power source are connected in series,
A series connection point of the first winding and the second winding is connected to one end of the commercial power supply,
The second winding and the commercial power source are connected in series between a connection point between the second capacitor and the first capacitor and a connection point between the second switching element and the first diode. A rectifier circuit characterized by: A series circuit of the fourth switching element and the third switching element, a series circuit of the second diode and the first switching element, and a series circuit of the second switching element and the first diode are connected to both ends of the output voltage. The circuit is connected in parallel,
a first winding wound around one magnetic core between a connection point between the fourth switching element and the third switching element and a connection point between the second diode and the first switching element; A first winding of an inductance with the second winding having the same phase polarity and one terminal connected between the first winding and the commercial power supply are connected in series,
A connection point between one terminal of the first winding and the second winding of the inductance is connected to one end of the commercial power supply,
The second winding and the commercial power source are connected in series between a connection point between the fourth switching element and the third switching element and a connection point between the second switching element and the first diode. A rectifier circuit characterized in that it is connected to. The inductance includes a first inductance made of the first winding wire and a second inductance made of the second winding wire, and the degree of coupling between the first inductance and the second inductance is less than 1. and a first leakage inductance is formed in the first inductance, and a second leakage inductance is formed in the second inductance, according to claim 4 or 5. rectifier circuit.

Images