JP7338238B2 - Signal power separation circuit, signal transmission circuit using the same, and vehicle - Google Patents

Description

The present invention provides a signal power separation circuit that prevents a signal from flowing from a signal line in which a signal and a DC bias power supply are propagated in a superimposed manner to a bias power supply source, and passes the DC bias power supply from the bias power supply source to the signal line. It relates to the signal transmission circuit used and the vehicle.

Conventionally, there is a bias circuit disclosed in Japanese Unexamined Patent Application Publication No. 2002-200310, for example, as this type of signal power supply separation circuit.

In this bias circuit, bias power output from a DC bias circuit is supplied to one end of a high-speed signal line through a parallel circuit of a resistor and an inductor. The parallel circuit prevents a high-frequency signal transmitted through the high-speed signal line from flowing to the DC bias circuit, and constitutes a signal power separation circuit that allows the DC bias power supply to pass through the high-speed signal line. According to this bias circuit, the parallel circuit has not only an inductive reactance component but also a resistance component. Therefore, the resistance component remains in the bias circuit even after canceling out the parasitic capacitance component generated by mounting the inductor, and the impedance of the bias circuit viewed from the transmission line is prevented from decreasing. Therefore, the signal propagating through the high-speed signal line does not flow into the bias circuit side.

WO2005/107063

However, in order to give the signal power separation circuit the characteristic of preventing a drop in impedance for a wider band signal propagating on a high-speed signal line, a plurality of inductors with different frequency characteristics are connected in series and combined. A signal power separation circuit is often configured. However, when different inductors are used in combination, anti-resonance occurs in the signal power separation circuit as shown in the graph of FIG. 8B, for example, and the impedance of the signal power separation circuit decreases. Therefore, the impedance frequency characteristic of the signal power separation circuit is degraded.

The graph shown in FIG. 8(b) shows the frequency of the impedance of the signal power separation circuit 1 configured by connecting, for example, three inductors L1, L2, and L3 in series as shown in FIG. 8(a). characterize. The signal power separation circuit 1 has the characteristic of blocking a signal from flowing from the signal line 2 to the bias supply source 3 and passing the DC bias power output from the bias supply source 3 to the signal line 2 . The horizontal axis of the graph represents frequency f [MHz], and the vertical axis represents impedance Z [Ω]. As shown in the graph, the signal power separation circuit 1 generates resonance at a frequency f of about 7 [MHz] and anti-resonance at a frequency f of about 30 [MHz]. Therefore, a large difference occurs between the impedance Z at a high frequency f and the impedance Z at a low frequency f, and the frequency characteristic of the impedance of the signal power separation circuit 1 is degraded. This is problematic in that it can cause impedance instability in signal line 2 .

For this reason, like the conventional circuit in which a resistor is connected in parallel with an inductor disclosed in Patent Document 1, for example, a signal power separation circuit 1a is configured as shown in FIG. It is conceivable to connect resistors R1, R2, and R3 in parallel to . The resistance values of the resistors R1, R2, and R3 connected in parallel to the inductors L1, L2, and L3 are high in the frequency band of approximately 7 [MHz] where resonance occurs, and at approximately 30 [MHz] where anti-resonance occurs. Low in frequency band is desirable. However, the values of the chip resistors used as resistors R1, R2 and R3 are constant with frequency. Therefore, there is a limit to flatly controlling the frequency characteristic of the impedance of the signal power separation circuit 1a whose impedance varies with frequency.

The present invention was made to solve such problems,
A signal line wired between the signal processing circuits on which a signal transmitted and received between the signal processing circuits and a DC bias power supply supplied from one signal processing circuit side to the other signal processing circuit are superimposed , and one signal processing circuit A plurality of first inductors are connected in series between a bias supply source that is arranged on the side and outputs a DC bias power supply to block passage of the DC bias power supply to the signal processing circuit and transmit a signal to the signal processing circuit. In a signal power separation circuit configured by providing a capacitor at the input end of each signal processing circuit of a signal line ,
A series circuit of a second inductor having a core made of a soft magnetic material having a relative magnetic permeability of 10 to 2,000 and a capacitor is connected in parallel to at least one of the plurality of first inductors. It is characterized by

The first inductor causes anti-resonance at a certain frequency by causing series resonance between the stray capacitance appearing in parallel with the first inductor and the adjacent first inductor. However, according to this configuration, the frequency characteristic of the impedance of the second inductor connected in parallel with the at least one first inductor is changed to the adjacent first inductor by the stray capacitance appearing in parallel with the at least one first inductor. By selecting a frequency that causes anti-resonance with the inductor and that has characteristics that cause anti-resonance, the impedance of the signal power separation circuit at the frequency that causes anti-resonance can be increased. That is, the current flowing through the stray capacitance at the frequency that causes the antiresonance is diverted to the second inductor, and the antiresonance caused between the stray capacitance and the adjacent first inductor is weakened. Therefore, the depression of the frequency characteristic at the anti-resonance point of the impedance of the signal power separation circuit is controlled to the flat side, and the frequency characteristic of the impedance of the signal power separation circuit is brought closer to the desired frequency characteristic.

The present invention also provides a signal transmission circuit in which communication is performed by superimposing a DC bias power supply on a signal line through which a signal propagates, wherein the signal power separation circuit described above is used to separate the signal in the signal line from the DC bias power supply. A signal transmission circuit was constructed.

According to this configuration, a signal transmission circuit is provided in which communication is performed while the signal superimposed on the signal line and the DC bias power supply are separated satisfactorily.

Further, the present invention constitutes a vehicle in which communication between on-vehicle electronic devices is performed using the signal transmission circuit described above.

According to this configuration, a vehicle is provided in which the signal superimposed on the signal line and the DC bias power supply are separated satisfactorily, and communication between the in-vehicle electronic devices is performed.

According to the present invention, it is possible to provide a signal power source separation circuit with improved impedance frequency characteristics, and separate the signal and the DC bias power source on a single signal line while satisfactorily separating the signal and the DC bias power source. It is possible to provide a signal transmission circuit and a vehicle capable of superimposing and communicating.

1 is a block diagram showing a schematic configuration of a signal transmission circuit to which a signal power separation circuit according to one embodiment of the present invention is applied; FIG. 1A is a circuit diagram showing a signal power separation circuit according to an embodiment, and FIG. 1B is a graph showing frequency characteristics of its impedance; FIG. 3A is a circuit diagram showing a series circuit connected in parallel to a resonance suppressing inductor constituting a signal power separation circuit according to an embodiment, and FIG. 3B is a graph showing frequency characteristics of impedance thereof; (a) is a circuit diagram showing a signal power supply separation circuit in which a countermeasure against resonance is implemented in a comparative example, and (b) is a graph showing frequency characteristics of impedance thereof. 4 is a graph showing series superimposition characteristics of a general ferrite bead inductor used as a resonance suppression inductor that constitutes a signal power separation circuit according to one embodiment. FIG. 10 is a circuit diagram showing a modification of the signal power separation circuit according to one embodiment; 1 is a schematic configuration diagram of a vehicle configured using a signal transmission circuit according to one embodiment of the present invention; FIG. (a) is a circuit diagram showing a conventional signal power separation circuit, and (b) is a graph showing the frequency characteristics of its impedance. FIG. 10 is a circuit diagram showing another conventional signal power separation circuit;

Next, a mode for implementing a signal power separation circuit, a signal transmission circuit using the same, and a vehicle according to the present invention will be described.

FIG. 1 is a block diagram showing a schematic configuration of a signal transmission circuit 12 to which a signal power separation circuit 11 according to one embodiment of the invention is applied.

The signal transmission circuit 12 is called Poc (Power Over Coax.), which superimposes a signal and a DC bias power supply on a single signal line 13 composed of a coaxial cable and performs communication using a single coaxial cable. using transmission technology. In this signal transmission circuit 12, a signal propagating on a signal line 13 is controlled by a signal power separation circuit 11 configured using separation inductors L1, L2, and L3 (first inductor, see FIG. 2) called Bias-T inductors. and a DC bias power supply of 5 [V] supplied from the bias supply source 14 to the signal line 13 . That is, the signal power separation circuit 11 prevents the signal from flowing from the signal line 13 to the bias supply source 14 and allows the DC bias power output from the bias supply source 14 to pass through the signal line 13 .

The signal line 13 is wired between each SerDes (Serializer Deserializer) circuits 15 and 16 . The SerDes circuits 15 and 16 serialize the parallel signals sent via a plurality of signal lines into serial signals, send them to one signal line, and send them via the one signal line. This is a circuit that deserializes the serial signals sent through the parallel lines, converts them into parallel signals, and sends them out to multiple signal lines. The DC bias power output from the bias supply source 14 is directly supplied to the SerDes circuit 16 and propagates through the signal line 13 through the signal power separation circuit 11 on the SerDes circuit 16 side. The DC bias power that has propagated through the signal line 13 is separated from the signal line 13 through the signal power separation circuit 11 on the SerDes circuit 15 side and supplied to the SerDes circuit 15 . Capacitors C1 and C1 are connected in series between the SerDes circuits 15 and 6 and the signal line 13, respectively. It is cut by C1. A high-frequency signal propagating through the signal line 13 is transmitted to each SerDes circuit 15, 16 via the capacitors C1, C1. Each of the signal power separation circuits 11, 11 is connected between the capacitor C1 and a coaxial cable connector (not shown) provided at the end of the signal line 13. FIG. The ideal impedance frequency characteristic of each of the signal power separation circuits 11, 11 is a characteristic showing 0 [Ω] for direct current and high impedance for high frequency.

For example, an image sensor 17 is connected to one SerDes circuit 15 via a plurality of signal lines 18, and the SerDes circuit 15 receives a wideband video signal input from the image sensor 17 via a plurality of signal lines 18. It is serialized and sent to one signal line 13 . At this time, the SerDes circuit 15 functions as a serializer and becomes a transmitter (Tx) that converts parallel signals into serial signals and outputs them.

For example, a display 19 is connected to the other SerDes circuit 16 via a plurality of signal lines 20, and the SerDes circuit 16 deserializes the serial video signal sent from the SerDes circuit 15 via the signal line 13, Output to the display 19 via a plurality of signal lines 20 . At this time, the SerDes circuit 16 functions as a deserializer (Deserializer) and becomes a receiver (Rx) that converts the serial signal to the original parallel signal and receives it.

Also, a control signal propagates in the reverse direction through one signal line 13 from the SerDes circuit 16 to the SerDes circuit 15 side, and the image sensor 17 is controlled by the circuit on the display 19 side. At this time, the SerDes circuit 16 functions as a serializer and becomes a transmitter (Tx) that converts parallel signals into serial signals and outputs them. Also, the SerDes circuit 15 functions as a deserializer and serves as a receiver (Rx) that converts the serial signal to the original parallel signal and receives it.

FIG. 2A is a circuit diagram showing the configuration of the signal power separation circuit 11 in this embodiment. In the figure, the same reference numerals are given to the same or corresponding parts as those in FIG. 1, and the description thereof will be omitted.

The signal power separating circuit 11 includes a plurality of separating inductors L1, L2, and L3 between a signal line 13, in which a signal and a DC bias power are superimposed and propagated, and a bias power source 14, which outputs the DC bias power. In the embodiment, three are connected in series. Furthermore, a series circuit of a resonance suppression inductor (second inductor) L4, a resistor R4, and a capacitor C2 is connected in parallel to at least one isolation inductor L3 among the plurality of isolation inductors L1, L2, and L3. It is The resonance suppressing inductor L4 is a ferrite bead inductor having a core made of ferrite, which is a soft magnetic material with a relative magnetic permeability of 10 to 2,000.

FIG. 2(b) shows that the inductance values of the isolation inductors L1, L2, and L3 are 160 [nH], 3.3 [μH], and 100 [μH], respectively, and the impedance of the resonance suppression inductor L4 at 1 [GHz]. is 1,500 [Ω], the resistance value of the resistor R4 is 800 [Ω], and the capacitance value of the capacitor C2 is 10 [pF]. The horizontal axis of the graph represents frequency f [MHz], and the vertical axis represents impedance Z [Ω].

Compared to the frequency characteristics of the impedance of the signal power separation circuit 1 of the comparative example configured by connecting three isolation inductors L1, L2, and L3 in series shown in FIG. In the impedance frequency characteristics of the signal power separation circuit 11 according to the present embodiment shown, the drop in impedance due to anti-resonance occurring at about 30 [MHz] is suppressed, and the characteristics approach ideal flat characteristics. The separating inductors L1, L2 and L3 shown in FIG. 8(b) are the same as those shown in FIG. 2(a) and have the same inductance values.

The improvement of the frequency characteristic of impedance in the signal power separation circuit 11 according to this embodiment can be explained as follows.

FIG. 3(a) is a series circuit of a resonance suppressing inductor L4, a resistor R4, and a capacitor C2 connected in parallel to the separating inductor L3 shown in FIG. 2(a). The graph shown in FIG. 3B is a graph showing frequency characteristics of the impedance of this series circuit. The horizontal and vertical axes of the graph are the same as those of the graph shown in FIG. 2(b). The frequency characteristics of the impedance of the series circuit connected in parallel with the isolation inductor L3 shown in FIG. Anti-resonance occurs at about 30 [MHz], similar to the impedance characteristic of the circuit 1 shown in FIG. 8(b).

In the signal power separation circuit 11 according to this embodiment, the series circuit shown in FIG. It has a configuration connected in parallel. The isolation inductor L3 causes anti-resonance at about 30 [MHz] by causing series resonance between the adjacent isolation inductor L2 and the stray capacitance appearing in parallel with the isolation inductor L3. On the other hand, in the signal power separation circuit 11 according to the present embodiment, the frequency characteristics of the impedance of the resonance suppression inductor L4 connected in parallel with the separation inductor L3 are such that the stray capacitance appearing in parallel with the separation inductor L3 is the separation inductor L3. A frequency of about 30 [MHz] that causes anti-resonance with L2 is selected to have characteristics that cause anti-resonance as shown in FIG. 3(b). In the signal power separation circuit 11 according to the present embodiment, the separation inductor L3 exhibiting anti-resonance characteristics in the same frequency band and the series circuit shown in FIG. The impedance is increased in the frequency band of about 30 [MHz] that causes antiresonance. That is, in the frequency band of about 30 [MHz] that causes anti-resonance, the current flowing in the stray capacitance appearing in parallel with the isolation inductor L3 is diverted to the resonance suppression inductor L4, and the stray capacitance is reduced to the isolation inductor. Anti-resonance caused between L2 is weakened. Therefore, the drop in the frequency characteristic at the anti-resonance point of the impedance of the signal power separation circuit 11 is controlled to the flat side to suppress the drop as shown in the graph of FIG. is brought close to the desired frequency characteristic.

FIG. 4(a) shows that one separating inductor L3 among the separating inductors L1, L2, and L3 has a resistance value of 1,500 [Ω] in place of the series circuit shown in FIG. 3(a). A signal power separation circuit 1b with a resistor R5 connected in parallel is shown. In FIG. 4(a), the same reference numerals are given to the same or corresponding parts as those in FIG. 1, and the description thereof will be omitted. FIG. 4(b) is a graph showing frequency characteristics of impedance of the signal power separation circuit 1b. The horizontal and vertical axes of the graph are the same as those of the graph shown in FIG. 2(b).

The frequency characteristic of the impedance of the signal power separation circuit 1b shown in FIG. 4(b) is 5 [MHz] band compared to the frequency characteristic of the impedance of the signal power separation circuit 11 according to the present embodiment shown in FIG. 2(b). , the peak of is lowered and the high impedance cannot be maintained, and the impedance at the anti-resonance point of the 30 [MHz] band is low and the drop is large. Thus, the countermeasure using only resistors for suppressing anti-resonance has limitations in controlling the impedance frequency characteristics.

The reason why the capacitor C2 is included in the series circuit shown in FIG. 3A is that it prevents a DC current from flowing through the series circuit, and the DC superposition characteristic of the resonance suppression inductor L4 prevents the impedance of the resonance suppression inductor L4 from decreasing. This is to prevent it from occurring. FIG. 5 is a graph showing DC superimposition characteristics of a general ferrite bead inductor used as the resonance suppressing inductor L4. The horizontal and vertical axes of the graph are the same as those of the graph shown in FIG. 2(b). A characteristic line 31 represented by a dotted line is a DC superimposition characteristic when no DC current flows through the ferrite bead inductor at 0 [mA]. DC superimposition characteristics when a DC current is flowing A characteristic line 33 represented by a dashed line is the DC superimposition characteristics when a DC current of 300 [mA] is flowing in the ferrite bead inductor.

As shown in the graph, when a DC current flows through the ferrite bead inductor, the impedance of the ferrite bead inductor decreases according to the magnitude of the DC current. Therefore, when a direct current flows through the series circuit using a ferrite bead inductor for the resonance suppressing inductor L4 shown in FIG. worsens.

The reason why the resistor R4 is included in the series circuit shown in FIG. That is, the frequency characteristics of the impedance of the signal power separation circuit 11 are raised by the amount corresponding to the resistance value of the provided resistor R4 by providing the resistor R4 in series with the resonance suppressing inductor L4 and the capacitor C2. The frequency characteristic line of the impedance shown in the graph has shifted upward on the graph to present frequency characteristics.

Therefore, it is possible to finely adjust the frequency characteristic of the impedance of the signal power separation circuit 11, and the frequency characteristic of the impedance of the signal power separation circuit 11 is brought closer to a more desirable flat frequency characteristic. Therefore, the resistor R4 is for fine adjustment of the impedance of the signal power separation circuit 11, and the series circuit connected in parallel with the resonance suppressing inductor L4 does not necessarily have to include the resistor R4, and may be omitted.

According to this embodiment, it is possible to provide the signal power separation circuit 11 with improved impedance frequency characteristics. In addition, since the signal transmission circuit 12 that separates the signal on the signal line 13 from the DC bias power supply is configured by using the signal power separation circuit 11, the signal superimposed on the signal line 13 and the DC bias power supply are separated. A signal transmission circuit 12 is provided with good isolation and communication between each SerDes circuit 15,16.

In the above embodiment, the series circuit of the resonance suppressing inductor L4, the resistor R4, and the capacitor C2 is connected in parallel to at least one separating inductor L3 among the plurality of separating inductors L1, L2, and L3. I explained the case where it is connected. However, the signal power supply separating circuit 11 may be configured by connecting a series circuit in parallel to one separating inductor L1 or L2 instead of the separating inductor L3. Alternatively, as shown in FIG. 6, the signal power separation circuit 11 may be configured such that a series circuit is connected in parallel to each of the plurality of separation inductors L1, L2, and L3. In addition, a specific inductor among the plurality of isolation inductors L1, L2, L3, for example, two isolation inductors L1, L2, isolation inductors L1, L3, or isolation inductors L2, L3. The signal power separation circuit 11 may be configured such that the circuits are connected in parallel. Also, the number of the separating inductors L1, L2, and L3 connected in series is not limited to three, and may be any number.

In the above embodiment, the resonance suppression inductor L4 has been described as a ferrite bead inductor having a core made of ferrite, which is a soft magnetic material with a relative magnetic permeability of 10 to 2,000. is not limited to this. The resonance suppressing inductor L4 may be, for example, an inductor whose core is made of a soft magnetic material having a relative magnetic permeability of 10 to 2,000, such as an amorphous metal material or a nanocrystalline soft magnetic material.

The signal power supply separating circuits 11 according to such modified examples also provide the same effects as those of the above-described embodiment.

FIG. 7 is a schematic configuration diagram of a vehicle 41 in which the signal transmission circuit 12 according to the above embodiment is used to perform communication between onboard electronic devices. In the figure, the same reference numerals are given to the same or corresponding parts as those in FIG. 1, and the description thereof will be omitted. Each SerDes circuit 15, 16 is connected to each ECU (Electronic Control Unit) 42, 43 that controls each in-vehicle electronic device. According to this configuration, the signal superimposed on the signal line 13 and the DC bias power supply are separated satisfactorily, and the vehicle 41 is provided in which communication between on-vehicle electronic devices is performed.

DESCRIPTION OF SYMBOLS 11... Signal power supply separation circuit 12... Signal transmission circuit 13... Signal line 14... Bias supply source 15, 16... SerDes circuit 17... Image sensor 19... Display 41... Vehicle L1, L2, L3... Separation inductor (first inductor)
L4... Resonance suppression inductor (second inductor)
R4... Resistor C2... Capacitor

Claims (5)

a signal line wired between the signal processing circuits on which a signal transmitted and received between the signal processing circuits and a DC bias power supply supplied from one of the signal processing circuits to the other signal processing circuit are superimposed ; A plurality of first inductors are connected in series between a bias supply source arranged on the signal processing circuit side and outputting the DC bias power supply to block passage of the DC bias power supply to the signal processing circuit. In a signal power separation circuit configured to include a capacitor for transmitting the signal to the signal processing circuit at an input end of each of the signal lines to the signal processing circuit,
A series circuit of a second inductor having a core made of a soft magnetic material having a relative permeability of 10 to 2,000 and a capacitor is connected in parallel to at least one of the plurality of first inductors. A signal power separation circuit characterized by: 2. The signal power separation circuit according to claim 1, wherein said series circuit is connected in parallel to each of said plurality of first inductors. 3. The signal power separation circuit according to claim 1, wherein said series circuit comprises a resistor in series with said second inductor and said capacitor. In a signal transmission circuit in which communication is performed by superimposing a DC bias power supply on a signal line through which a signal propagates, the signal power separation circuit according to any one of claims 1 to 3 is used in the signal line. A signal transmission circuit, wherein the signal and the DC bias power supply are separated. 5. A vehicle, wherein the signal transmission circuit according to claim 4 is used for communication between on-vehicle electronic devices.

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