JP7322566B2 - Modular multilevel cascade converter - Google Patents

Description

The present invention relates to a single star bridge cell (SSBC) modular multi-level cascade converter (MMCC) technology interconnected to a three-phase AC system.

FIG. 1 shows the configuration of a single star bridge cell (SSBC) modular multilevel cascade converter (MMCC). A feature of this circuit is that each arm is configured by a module in which the bridge cells B shown in FIG. The MMCC-SSBC can be connected to a high-voltage system without a transformer, and is expected to be used as a reactive power compensator.

However, MMCC-SSBC has a problem that interphase cell capacitor voltage balance is lost when connecting to an unbalanced voltage system or outputting reversed-phase current, that is, outputting reversed-phase power. This imbalance causes excessive voltage applied to switching elements and cell capacitors, distorted voltage and current waveforms output from MMCC-SSBC, burnout of transformers, overheating and breakdown of power factor improvement capacitors, It causes problems such as motor hum and circuit breaker malfunction, which adversely affect other devices. Patent Document 1 discloses a method for improving this imbalance.

JP 2013-5694 A

Satoshi Ishizuka, Kazuyoshi Nezu, Yukihiko Sato, Hiroshi Yamaguchi, Akio Kataoka, "Power supply current control of voltage source PWM rectifier circuit applying lossless resonator", 1996, Theory of Electrical Engineering D, Vol.116, No.8 , p. 883-884

Feedback control is known to improve the unbalance by detecting the unbalance of the interphase cell capacitor voltage and superimposing the zero-phase voltage. However, in feedback control, superposition of the zero-phase voltage is started only after an imbalance occurs, so a temporary imbalance always occurs.

Therefore, especially when the reverse-phase current is suddenly changed or when the system voltage suddenly becomes unbalanced due to a short circuit or the like, an excessive voltage may be applied to the switching element or the cell capacitor. If the feedback gain is increased, the imbalance can be reduced, but on the other hand, the control becomes unstable, and there is a greater possibility that large vibrations will be superimposed on the cell capacitor voltage and output current, making it impossible to continue operation in some cases.

Patent Literature 1 discloses feedforward control that detects the negative-sequence voltage/current and calculates and superimposes the optimum zero-sequence voltage for maintaining the cell capacitor voltage balance. Since the feedforward control can superimpose the zero-phase voltage before the imbalance occurs, unlike the feedback control, the imbalance can be reduced. The zero-phase voltage of Patent Document 1 is given by equation (1).

Equation (1) is represented by a complex vector. The phase voltages Vu, Vv, and Vw are represented by the equation (2), and the phase currents Iu, Iv, and Iw are represented by the equation (3), and the zero-phase voltage is obtained again.

V1d is the positive phase d-axis voltage. If the PLL is enabled and the control system is locked to the phase of the grid voltage, the positive phase q-axis voltage is zero. V2d, V2q, V0d, and V0q are the anti-phase d-axis voltage, anti-phase q-axis voltage, zero-phase d-axis voltage, and zero-phase q-axis voltage, respectively. The same applies to currents, and I1q, I2d, and I2q are positive-phase q-axis current, negative-phase d-axis current, and negative-phase q-axis current, respectively. The active power per cycle of the fundamental wave of each phase is given by equation (4). It is assumed that the active power per cycle of the fundamental wave of each phase is the same value.

Solving the above equation (4) yields the following equation (5). Equation (5) is equivalent to Equation (1).

However, in the equations (1) and (5), when the amplitudes of the positive-sequence current and the negative-sequence current are equal, the denominator becomes zero, and an appropriate zero-sequence voltage cannot be obtained. Paragraphs [0052] and [0056] of Patent Document 1 also describe that the amplitudes of the positive-phase current and the negative-phase current should not be equal.

Based on the above, in the modular multi-level cascade converter, we realized the cell capacitor voltage balance control by feedforward when the amplitude of the positive sequence current and the negative sequence current are equal, and increased the negative sequence current. The problem is getting it to output.

The present invention has been devised in view of the above-described conventional problems, and one aspect thereof is a three-phase module in which a plurality of bridge cells are connected in series to constitute a one-phase module, and three such modules are included in the three-phase module. A modular multi-level cascade converter that calculates the positive-phase d-axis voltage based on the system voltage detection signal, A corrected amplitude ratio is calculated based on, a zero-phase d-axis voltage and a zero-phase q-axis voltage are calculated based on the positive-phase d-axis voltage and the corrected amplitude ratio, and the zero-phase d-axis voltage and the system voltage detection signal are calculated. and the product of the zero-phase q-axis voltage and the sine value corresponding to the phase of the system voltage detection signal are added together to calculate the zero-phase voltage. and a current command value calculation unit that obtains a negative phase current command value based on the positive phase q-axis current command value, the amplitude ratio, and the phase difference, and calculates a current command value by superimposing the negative phase current command value. , and a current control unit that generates a gate signal based on the zero-phase voltage and the current command value.

Further, as one aspect thereof, when the output voltage and the output current of the modular multi-level cascade converter are defined by equations (2), (3), and (15), the zero-phase voltage calculation unit is , the phase difference is a value selected from 0 deg, 60 deg, 120 deg, 180 deg, 240 deg, and 300 deg, and when the phase difference is 0 deg and 180 deg, formula (10-1), the phase difference is 120 deg and 300 deg The zero-phase d-axis voltage and the zero-phase q-axis voltage are calculated based on equation (10-2) when the phase difference is 240 degrees and equation (10-3) when the phase difference is 240 degrees and 60 degrees.

Vu, Vv, Vw: U-phase output voltage, V-phase output voltage, W-phase output voltage V1d: Positive phase d-axis voltage V2d: Negative phase d-axis voltage V2q: Negative phase q-axis voltage V0d: Zero phase d-axis Voltage V0q: Zero-phase q-axis voltage ωt: System voltage phase φ: Phase difference between positive-phase current and negative-phase current
a': Ratio of negative-sequence current amplitude to positive-sequence current amplitude (a'=√(I2d* ² +I2q* ² )/|I1q*|, where I1d*=0)
a: corrected amplitude ratio where a=a' (φ=0deg, 120deg, 240deg)
a = -a' (φ = 60deg, 180deg, 300deg)
Iu, Iv, Iw : U-phase output current, V-phase output current, W-phase output current I1q: Positive phase q-axis current I2d: Negative phase d-axis current I2q: Negative phase q-axis current
I2d*: Negative phase d-axis current command value
I2q*: Anti-phase q-axis current command value
I1d*: positive phase d-axis current command value
I1q*: Positive phase q-axis current command value .

Further, as another aspect, when the output voltage and output current of the modular multilevel cascade converter are defined by equations (2), (3), and (15), the zero-phase voltage calculator is , the phase difference is a value selected from 0 deg, 60 deg, 120 deg, 180 deg, 240 deg, and 300 deg, and when the phase difference is 0 deg and 180 deg, formula (14-1), the phase difference is 120 deg and 300 deg The zero-phase d-axis voltage and the zero-phase q-axis voltage are calculated based on equation (14-2) when the phase difference is 240 degrees and equation (14-3) when the phase difference is 240 degrees and 60 degrees.

Vu, Vv, Vw: U-phase output voltage, V-phase output voltage, W-phase output voltage V1d: Positive phase d-axis voltage V2d: Negative phase d-axis voltage V2q: Negative phase q-axis voltage V0d: Zero phase d-axis Voltage V0q: Zero-phase q-axis voltage ωt: System voltage phase φ: Phase difference between positive-phase current and negative-phase current
a': Ratio of negative-sequence current amplitude to positive-sequence current amplitude (a'=√(I2d* ² +I2q* ² )/|I1q*|, where I1d*=0)
a: corrected amplitude ratio where a=a' (φ=0deg, 120deg, 240deg)
a = -a' (φ = 60deg, 180deg, 300deg)
Iu, Iv, Iw : U-phase output current, V-phase output current, W-phase output current I1q: Positive phase q-axis current I2d: Negative phase d-axis current I2q: Negative phase q-axis current
I2d*: Negative phase d-axis current command value
I2q*: Anti-phase q-axis current command value
I1d*: positive phase d-axis current command value
I1q*: Positive phase q-axis current command value .

Further, as another aspect, when the output voltage and output current of the modular multilevel cascade converter are defined by equations (2), (3), and (15), the zero-phase voltage calculator is , when the phase difference is 0 deg, 180 deg, (14-1) formula, when the phase difference is 120 deg, 300 deg, (14-2) formula, when the phase difference is 240 deg, 60 deg, based on the formula (14-3) If the phase difference is not 0 deg, 60 deg, 120 deg, 180 deg, 240 deg, or 300 deg, the two closest phase differences are calculated by formula (14-1) , (14-2) and (14-3), the two zero-phase d-axis voltages and the zero-phase q-axis voltage are obtained, and the two zero-phase d-axis voltages and the zero-phase q-axis voltage are The zero-phase d-axis voltage and the zero-phase q-axis voltage are determined by interpolation.

Vu, Vv, Vw: U-phase output voltage, V-phase output voltage, W-phase output voltage V1d: Positive phase d-axis voltage V2d: Negative phase d-axis voltage V2q: Negative phase q-axis voltage V0d: Zero phase d-axis Voltage V0q: Zero-phase q-axis voltage ωt: System voltage phase φ: Phase difference between positive-phase current and negative-phase current
a': Ratio of negative-sequence current amplitude to positive-sequence current amplitude (a'=√(I2d* ² +I2q* ² )/|I1q*|, where I1d*=0)
a: corrected amplitude ratio However, in the formula (14-1), a = a'(φ<90deg,270deg<φ)
a=-a'(90deg<φ<270deg)
(14-2), a=a'(30deg<φ<210deg)
a=-a'(φ<30deg,210deg<φ)
(14-3), a=a'(150deg<φ<330deg)
a=-a'(φ<150deg,330deg<φ)
Iu, Iv, Iw : U-phase output current, V-phase output current, W-phase output current I1q: Positive phase q-axis current I2d: Negative phase d-axis current I2q: Negative phase q-axis current
I2d*: Negative phase d-axis current command value
I2q*: Anti-phase q-axis current command value
I1d*: positive phase d-axis current command value
I1q*: Positive phase q-axis current command value .

Further, as one aspect thereof, the zero-phase voltage calculation unit sets the correction coefficient to 2/√3 when the phase difference is 30 deg, 90 deg, 150 deg, 210 deg, 270 deg, and 330 deg, and the phase difference is 0 deg, 60 deg, 120 deg. , 180 deg, 240 deg, and 300 deg, the correction coefficient is set to 1, and the gain Gi obtained by interpolating the correction coefficient for the phase difference between them is expressed by equations (14-1), (14-2), and (14-3). A term dependent on the positive phase d-axis voltage in the equation is multiplied.

According to the present invention, in a modular multi-level cascade converter, feedforward cell capacitor voltage balance control is realized when the amplitudes of the positive-sequence current and the negative-sequence current are equal, and a larger negative-sequence current can be output. It becomes possible to do so.

Schematic diagram showing the configuration of MMCC-SSBC. Schematic which shows the structure of a bridge cell. FIG. 4 is a block diagram showing a current control unit according to Embodiments 1 to 4; 4 is a block diagram showing a zero-phase voltage calculator and a current command value calculator according to the first embodiment; FIG. FIG. 8 is a block diagram showing a zero-phase voltage calculator and a current command value calculator according to the second embodiment; The block diagram which shows the zero sequence voltage calculating part of Embodiment 3. FIG. The block diagram which shows the zero sequence voltage calculating part of Embodiment 4. FIG. A phasor diagram when only positive phase current (reactive power) is output in a three-phase balanced system. A phasor diagram when a positive-sequence current and a small amount of negative-sequence current are output in a three-phase balanced system. A phasor diagram when the amplitudes of the positive-sequence current and the negative-sequence current are equal and the cell capacitor voltage balance cannot be maintained. A phasor diagram when the amplitudes of the positive and negative sequence currents are equal but the cell capacitor voltage balance can be maintained. A simulation waveform when outputting a negative-phase current having the same amplitude as the positive-phase current with I2d=0 and I2q=I1q. A simulation waveform when a U-phase ground fault is generated. Simulation waveform when a VW line-to-ground fault is generated.

Embodiments 1 to 4 of the modular multilevel cascade converter according to the present invention will be described in detail below with reference to FIGS. 1 to 14. FIG.

[Embodiment 1]
The modular multi-level cascade converter (serial multiple inverter device) of the first embodiment is assumed to be applied to the circuit shown in FIG. 1, for example. In FIG. 1, reference numeral 25 denotes a three-phase alternating current system power supply, and the system voltage is Vs. A plurality of bridge cell B units are connected in series to form a one-phase module. It has three modules and is connected to each phase of the system via a reactor. That is, n bridge cells are connected to each phase (three phases), and 3n bridge cells B are connected in total for the three phases.

As shown in FIG. 2, in the bridge cell B, one end of the first semiconductor switching element S1 is connected to one connection terminal. One end of the second semiconductor switching element S2 is connected to one end of the first semiconductor switching element S1. The third semiconductor switching element S3 is connected between the other end of the first semiconductor switching element S1 and the other connection terminal. The fourth semiconductor switching element S4 is connected between the other end of the second semiconductor switching element S2 and the other connection terminal. The cell capacitor C is connected between the connection point of the first and third semiconductor switching elements S1 and S3 and the connection point of the second and fourth semiconductor switching elements S2 and S4.

FIG. 3 shows a block diagram of the current controller of the MMCC-SSBC. The low-pass filter LPF removes noise, switching ripples, and the like from the output current detection signals Iu, Iv, and Iw of each phase. A three-to-two phase converter 1 converts the output result of the low-pass filter LPF into three-to-two phases and outputs two-phase output current detection signals Ia and Ib.

Subtractors 2a and 2b calculate deviations between current command values Ia* and Ib* on fixed coordinates after three-phase to two-phase conversion and two-phase output current detection signals Ia and Ib, which will be described later. A P (proportional) R (resonant) amplifier PR amplifies the outputs of the subtractors 2a and 2b. The R amplifier is described in Non-Patent Document 1 and has an infinite gain with respect to a specific frequency. By using this frequency as the system power supply frequency, the deviation of both the positive-sequence current and the negative-sequence current can be made zero. A two-to-three-phase converter 3 converts the output of the PR amplifier PR into two-to-three phases and outputs an output voltage command value for each phase.

The adder 4 adds V0dcosωt and V0qsinωt, which will be described later, and outputs a zero-phase voltage. The adders 5u, 5v, and 5w add the zero-phase voltage, which is the output of the adder 4, to the output voltage command value of each phase output from the two-to-three-phase converter 3, respectively. In addition, the zero-phase voltage obtained by cell capacitor voltage balance feedback control may be added.

The PWM modulator PWM compares the output voltage command value of each phase superimposed with the zero-phase voltage and the carrier triangular wave corresponding to each cell, and obtains the gate signal of each bridge cell B. FIG. The obtained gate signal is input to each bridge cell B in FIG.

FIG. 4 shows a block diagram of the zero-phase voltage calculator and the current command value calculator in the first embodiment. Current command values Ia* and Ib* are calculated by a current command value calculator 27 .

A PLL (Phase Locked Loop) obtains the phase ωt from the system voltage detection signal Vs.

The positive phase d-axis current command value I1d* corresponds to active power and is zero in the reactive power compensator. However, the steady-state loss of the device may be included due to the cell capacitor voltage balance feedback control. Also in the case of the first embodiment, the positive phase d-axis current command value I1d* is substantially zero.

The dq inverse converter 6 performs dq inverse conversion on the positive phase d-axis current command value I1d* and the positive phase q-axis current command value I1q* based on the phase ωt to convert them into current command values on fixed coordinates.

a' is the amplitude ratio of the negative sequence current to the positive sequence current. That is, a′=√(I2d* ² +I2q* ² )/|I1q*| (where I1d*=0). However, a'>0. The multiplier 7 calculates the product of the positive phase q-axis current command value I1q* and the amplitude ratio a' to obtain the amplitude a'I1q* of the negative phase current.

φ is the phase difference of the negative sequence current with respect to the positive sequence current. However, the phase difference φ is limited to six values of 0deg, 60deg, 120deg, 180deg, 240deg and 300deg. The switch 17 selects and outputs the closest phase pattern from 0deg, 60deg, 120deg, 180deg, 240deg and 300deg.

The multiplier cos inputs the phase difference φ and the amplitude a′I1q* of the negative-sequence current, and outputs the product of the cosine value corresponding to the phase difference φ and the amplitude a′I1q* of the negative-sequence current. The output of the multiplier cos is the anti-phase q-axis current command value I2q*.

The multiplier sin receives the phase difference φ and the amplitude a′I1q* of the negative-sequence current, and outputs the product of the sine value corresponding to the phase difference φ and the amplitude a′I1q* of the negative-sequence current. A multiplier 8 multiplies the output of the multiplier sin by -1. The output of the multiplier 8 becomes the anti-phase d-axis current command value I2d*.

A multiplier 9 multiplies the phase ωt by -1. The dq inverse converter 10 performs dq inverse transformation on the anti-phase d-axis current command value I2d* and the anti-phase q-axis current command value I2q* based on the phase -ωt to convert them into values on fixed coordinates. Adders 11a and 11b add the outputs of the dq inverse transformers 6 and 10 together. The outputs of the adders 11a and 11b are current command values Ia* and Ib* on fixed coordinates.

Next, the zero-phase voltage calculator 26 will be described. The low-pass filter LPF removes noise, switching ripples, etc. from the system voltage detection signal Vs. The dq converter 12 dq-converts the system voltage detection signal Vs based on the phase ωt. The moving average filters MAVE1 and MAVE2 remove pulsations at twice the fundamental frequency caused by voltage imbalance from the output of the dq converter 12 . After applying the moving average filters MAVE1 and MAVE2, the positive phase d-axis voltage V1d and the positive phase q-axis voltage V1q are obtained. The positive phase q-axis voltage V1q is normally zero as long as the PLL operates normally, and is not used here.

The switch 13 outputs 1 when the phase difference φ is 0 deg, 120 deg, and 240 deg, and -1 when it is 60 deg, 180 deg, and 300 deg. A multiplier 14 obtains the product of the output of the switch 13 and the amplitude ratio a'. The output of the multiplier 14 becomes the correction amplitude ratio a of equation (9), which will be described later.

The calculator 15 calculates three patterns of zero-phase d-axis voltage (amplitude ) V0d and the zero-phase q-axis voltage (amplitude) V0q are obtained. The switch 16 selects an appropriate zero-phase d-axis voltage (amplitude) V0d, zero-phase q-axis voltage (amplitude) V0d, zero-phase q-axis voltage ( amplitude) V0q is output. Formula (10-1) for 0deg and 180deg, formula (10-2) for 120deg and 300deg, and formula (10-3) for 240deg and 60deg.

The multiplier cos receives the zero-phase d-axis voltage (amplitude) V0d output from the switch 16 and the phase ωt, and outputs the product V0dcosωt of the cosine value corresponding to the phase ωt and the zero-phase d-axis voltage (amplitude) V0d. . The multiplier sin receives the zero-phase q-axis voltage (amplitude) V0q output from the switch 16 and the phase ωt, and outputs the product V0qsinωt of the sine value corresponding to the phase ωt and the zero-phase q-axis voltage (amplitude) V0q. . The products V0dcosωt and V0qsinωt are added by the adder 4 in FIG. 3, and added to the voltage command value as zero-phase voltages by the adders 5u, 5v and 5w. It is assumed that the adder 4 is also included in the zero-phase voltage calculator 26 .

In the first embodiment, the system voltage is three-phase balanced (V2d = V2q = 0) and the phase condition of the negative-sequence current with respect to the positive-sequence current is limited so that the negative-sequence current having the same amplitude as the positive-sequence current can be output. bottom.

By substituting V2d=V2q=0 into the equation (5), the following equation (6) is obtained.

Here, even if the amplitudes of the positive-sequence current and the negative-sequence current are equal, if the numerator of the equation (6) is also zero, it is conceivable that a zero-sequence voltage that satisfies the equation (4) exists. As shown in Equation (7), there are three conditions under which the amplitudes of the positive-sequence current and the negative-sequence current are equal and both the numerator and denominator of Equation (6) are zero.

Substituting the expression (7) into the expression (3) and solving the expression (4) under the condition of V2d=V2q=0, the expression (8) is obtained.

From this, it was confirmed that even if the amplitudes of the positive-phase current and the negative-phase current are equal, if the numerator of the equation (6) is zero, then there certainly exists a zero-phase voltage that can maintain the cell capacitor voltage balance. Since the amplitude of the negative-sequence current is also limited in the equation (7), the corrected amplitude ratio a is defined as the amplitude ratio of the negative-sequence current to the positive-sequence current, and the negative-sequence current is expressed by the equation (9). The correction amplitude ratio a and the amplitude ratio a' have a relationship of a'=|a|, and the correction amplitude ratio a can be a negative value.

By substituting the formula (9) into the formula (3) and solving the formula (4) under the condition of V2d=V2q=0, the formulas (10-1), (10-2) and (10-3) are obtained. is obtained.

By using the equations (10-1), (10-2), and (10-3) obtained above instead of equation (1) to calculate the zero-phase voltage and superimpose it on the voltage command value, The cell capacitor voltage can be balanced even if the reversed-phase current is output. Equations (10-1), (10-2) and (10-3) can obtain the zero-phase voltage even when a=1. Although the phase relationship between the positive phase current and the negative phase current is limited to three patterns, the cell capacitor voltage can be balanced even if the negative phase current having the same amplitude as the positive phase current is output.

In the first embodiment, the positive phase d-axis voltage V1d is obtained from the system voltage detection signal Vs, the corrected amplitude ratio a is obtained from the amplitude ratio a′ and the phase difference φ, and the following equations (10-1), (10-2), (10-3) is used to find the zero-phase voltage required for cell capacitor voltage balance.

Also, from the positive phase q-axis current command value I1q*, the amplitude ratio a′, and the phase difference φ, the negative phase d-axis current command value I2d*, the negative phase q-axis current command value I2q*, and the current command value on the fixed coordinates Ia* and Ib* are obtained and output to the current controller.

In Embodiment 1, the phase relationship between the positive-phase current and the negative-phase current is limited to six patterns in increments of 60 degrees including a<0. Therefore, a host controller or the like selects the phase pattern closest to the original reverse-phase current command and inputs it to the control block of FIG.

The amplitude ratio a' of the negative-sequence current to the positive-sequence current that the device can output depends on the amplitude of the zero-sequence voltage that can be superimposed on the device. That is, the larger the number of cells in the device and the larger the cell capacitor voltage, the larger the negative-sequence current that can be output. For example, if the device can output a voltage with an amplitude 1.5 times the rated (maximum) voltage, the phase difference φ is 0 ≤ a' ≤ 1 at 0 deg, 120 deg, and 240 deg, and 0 ≤ a at 60 deg, 180 deg, and 300 deg. The amplitude ratio a' can be specified within the range of '≦1/3.

According to the first embodiment, the phase of the negative-sequence current with respect to the positive-sequence current is limited to three patterns. can be kept constant.

The first embodiment can be applied only when the system voltage is three-phase balanced. Further, in the first embodiment, the phase of the negative-phase current is limited to six patterns, but the negative-phase current having a small amplitude ratio with respect to the positive-phase current can be output. The amplitude ratio of the negative-sequence current that can be output depends on the magnitude of the voltage amplitude that the device can output, that is, the number of cells and the magnitude of the cell capacitor voltage.

[Embodiment 2]
FIG. 5 shows a block diagram of the zero-phase voltage calculator 26 and current command value calculator 27 of the second embodiment. The second embodiment differs from the first embodiment in the following points.

A multiplier 18 multiplies the phase ωt by -1. The dq converter 19 dq-converts the system voltage detection signal Vs to which the low-pass filter LPF is applied based on the phase -ωt. The moving average filters MAVE3 and MAVE4 remove from the output of the dq converter 19 the pulsation twice the fundamental frequency caused by the positive phase voltage. The result of applying the moving average is the anti-phase d-axis voltage V2d and the anti-phase q-axis voltage V2q.

In addition to the positive-phase d-axis voltage V1d and the corrected amplitude ratio a, the calculator 15 also receives the negative-phase d-axis voltage V2d and the negative-phase q-axis voltage V2q. Also, the arithmetic expressions of the calculator 15 are changed to the expressions (14-1), (14-2), and (14-3) described later.

The second embodiment is obtained by modifying the first embodiment so that it can also be applied to an unbalanced system. Substituting the equation (9) into the equation (3) and resolving the equation (4) under the condition that V2d≠0 and V2q≠0 yields the following equation (11).

In the expression (11), the term 1/(a-1) becomes zero when the expression (12) is satisfied. That is, it is conceivable that there is a zero-phase voltage that can maintain the cell capacitor voltage balance even when a=1.

Substituting equation (12) into equations (2) and (3) and resolving equation (4) yields equation (13). I have confirmed that it does exist.

However, in order to apply the formula (13), it is necessary to satisfy the condition of the formula (12), and the phase relationship of not only the negative-sequence current but also the negative-sequence voltage is greatly restricted in obtaining the zero-sequence voltage.

Now consider outputting a small amount of negative-sequence current at an arbitrary voltage unbalance, and outputting a certain amount of negative-sequence current under a specific voltage unbalance condition. For this, we obtain a result approximately equal to equation (11) for a≈0, and approximately equal to equation (13) for a>−1 when equation (12) is satisfied, avoiding division by zero at a=1. An approximation formula is required. Using these as equations that satisfy two conditions, for example, equations (14-1), (14-2), and (14-3) in which the 1/(a-1) term in equation (11) is approximated by the first-order Maclaurin expansion. ) expression.

Formulas (14-1), (14-2) and (14-3) obtained above are used instead of formulas (10-1), (10-2) and (10-3). By calculating the zero-sequence voltage and superimposing it on the voltage command value, it is possible to balance the cell capacitor voltages even if a small amount of negative-sequence current is output in an arbitrary unbalanced voltage system.

Furthermore, the phase relationship between the positive-sequence current and the negative-sequence current is limited to three patterns, and the phase of the negative-sequence voltage is also limited. Cell capacitor voltages can be balanced.

For example, when outputting a negative-phase current with an amplitude equal to the positive-phase current of I2d = 0 and I2q = I1q (when the U-phase current is zero, either the V-phase current or the W-phase current is in phase with the U-phase voltage). , the negative sequence voltage must be V2q=0. Taking a short-circuit accident as an example, a U-phase ground fault and a VW line-to-line short circuit satisfy V2q=0, and in this case the operation can be continued. If the other phase is short-circuited, it is necessary to throttle the negative phase current.

In the second embodiment, in addition to the first embodiment, the anti-phase d-axis voltage V2d and the anti-phase q-axis voltage V2q are obtained from the system voltage detection signal Vs. (14-3) is used to find the zero-phase voltage required for cell capacitor voltage balance. In the second embodiment, as in the first embodiment, the phase relationship between the positive-sequence current and the negative-sequence current is limited to 6 patterns in increments of 60 degrees including a<0. Therefore, a host controller or the like selects the phase pattern closest to the original reverse-phase current command and inputs it to FIG.

The second embodiment has the same effect as the first embodiment. In addition to the effects of the first embodiment, the second embodiment can be applied to any unbalanced voltage system as long as the amplitude ratio of the negative-phase current to the positive-phase current is small. In addition, although limited to a three-phase balanced system and an unbalanced voltage system under specific conditions, it is possible to output a negative-sequence current with an amplitude equal to the positive-sequence current. For example, in a system voltage in which the anti-phase q-axis voltage V2q is zero and an arbitrary anti-phase d-axis voltage V2d is superimposed, the U-phase current is zero, and the phase of either the V-phase current or the W-phase current is the U-phase voltage phase. , the cell capacitor voltage balance can be maintained. Examples of this include a U-phase ground fault and a VW line-to-line short circuit.

[Embodiment 3]
FIG. 6 shows a block diagram of the zero-phase voltage calculator 26 in the third embodiment. The current command value calculation unit 27 is the same as that of the second embodiment, so its description is omitted. The third embodiment differs from the second embodiment in the following points. Unlike the first and second embodiments, any phase from 0deg to 360deg can be specified for the phase difference φ.

The switch 20a outputs 1 if φ<90deg and 270deg<φ, and -1 if 90deg<φ<270deg. The multiplier 21a multiplies the amplitude ratio a' by the output of the switch 20a. The output of the multiplier 21a becomes the correction amplitude ratio a1. That is, if φ<90deg and 270deg<φ, a1=a', and if 90deg<φ<270deg, a1=-a'. The calculator 15a performs calculation using the corrected amplitude ratio a1 instead of the corrected amplitude ratio a in the equation (14-1).

The gain output unit 22a linearly decreases from 1 to 0 in the range of 0deg<φ<60deg, is constant at 0 in the range of 60deg<φ<120deg, and linearly from 0 to 1 in the range of 120deg<φ<180deg. In the range of increasing, 180deg<φ<360deg, the gain G1 that outputs the same value as 0deg<φ<180deg is output. The multiplier 23a multiplies the calculation result (zero-phase d-axis voltage V0d) of the calculator 15a by the gain G1.

The switch 20b outputs 1 if 30deg<φ<210deg, and -1 if φ<30deg and 210deg<φ. The multiplier 21b multiplies the amplitude ratio a' by the output of the switch 20b. The output of the multiplier 21b becomes the correction amplitude ratio a2. That is, if 30deg<φ<210deg, a2=a', and if φ<30deg and 210deg<φ, a2=-a'. The calculator 15b performs calculation using the corrected amplitude ratio a2 instead of the corrected amplitude ratio a in the equation (14-2).

The gain output unit 22b is constant at 0 in the range of 0deg<φ<60deg, increases linearly from 0 to 1 in the range of 60deg<φ<120deg, and decreases linearly from 1 to 0 in the range of 120deg<φ<180deg. , 180deg<φ<360deg, a gain G2 that outputs the same value as 0deg<φ<180deg is output. The multiplier 23b multiplies the calculation result (zero-phase d-axis voltage V0d) of the calculator 15b by the gain G2.

The switch 20c outputs 1 if 150deg<φ<330deg and -1 if φ<150deg and 330deg<φ. The multiplier 21c multiplies the amplitude ratio a' by the output of the switch 20c. The output of the multiplier 21c becomes the correction amplitude ratio a3. That is, if 150deg<φ<330deg, a3=a', and if φ<150deg and 330deg<φ, a3=-a'. The calculator 15c performs calculation using the corrected amplitude ratio a3 instead of the corrected amplitude ratio a in the equation (14-3).

The gain output unit 22c linearly increases from 0 to 1 in the range of 0deg<φ<60deg, decreases linearly from 1 to 0 in the range of 60deg<φ<120deg, and decreases linearly from 1 to 0 in the range of 120deg<φ<180deg. In the range of 0 constant and 180deg<φ<360deg, a gain G3 that outputs the same value as 0deg<φ<180deg is output. The multiplier 23c multiplies the calculation result (zero-phase d-axis voltage V0d) of the calculator 15c by a gain G3.

The adder 24 adds the outputs of the three multipliers 23a, 23b, and 23c to obtain the zero-phase d-axis voltage V0d of the third embodiment. A similar calculation is performed for the zero-phase q-axis voltage V0q.

That is, in the third embodiment, when the phase difference φ is 0 deg and 180 deg, the formula (14-1), when the phase difference φ is 120 deg and 300 deg, the formula (14-2), and when the phase difference φ is 240 deg and 60 deg ( 14-3) Calculate the zero-phase d-axis voltage V0d and the zero-phase q-axis voltage V0q based on the equations. If the phase difference φ is not 0 deg, 60 deg, 120 deg, 180 deg, 240 deg, or 300 deg, two zeros are obtained from the two closest phase differences φ by formulas (14-1), (14-2) and (14-3). A phase d-axis voltage V0d and a zero-phase q-axis voltage V0q are obtained, and the zero-phase voltage is determined by linear interpolation of the two zero-phase d-axis voltage V0d and zero-phase q-axis voltage V0q.

In the subsequent stage, the zero-phase d-axis voltage V0d and cosωt are multiplied, the zero-phase q-axis voltage V0q and sinωt are multiplied, and the sum is added to the voltage command value as the zero-phase voltage.

The third embodiment is different from the second embodiment in that the phase of the reversed-phase current is not limited to six patterns of 60-degree increments, but can be adapted to an arbitrary phase. Since the formulas (14-1), (14-2), and (14-3) can only calculate the zero-phase voltage in increments of 60 degrees, the appropriate zero-phase voltage in the intervening phase is estimated by interpolation. In the third embodiment, linear interpolation is applied as an example of interpolation.

Equation (14-1) of calculator 15a corresponds to φ=0deg and 180deg. Equation (14-2) of calculator 15b corresponds to φ=120deg and 300deg. Equation (14-3) of calculator 15c corresponds to φ=240deg and 60deg. For example, when φ=30 deg is specified, the average of the equation (14-1) of the calculator 15a and the equation (14-3) of the calculator 15b is output as the zero-phase d-axis voltage V0d. If the phase difference φ=75 deg, the equation (14-2) of the calculator 15b and the equation (14-3) of the calculator 15c are added at a ratio of 1:3 and output.

According to the third embodiment, in addition to the second embodiment, in an arbitrary unbalanced voltage system, the cell capacitor voltages can be balanced even if a negative-phase current having a small amplitude and an arbitrary phase is output. When outputting a negative-sequence current with an amplitude equal to the positive-sequence current in an unbalanced voltage system, the phases of the negative-sequence voltage and the negative-sequence current are limited as in the second embodiment.

The third embodiment has the same effect as the second embodiment. In addition to the effects of the second embodiment, it is possible to output a negative-phase current with a small amplitude ratio and an arbitrary phase with respect to the positive-phase current.

[Embodiment 4]
FIG. 7 shows a block diagram of the zero-phase voltage calculator 26 in the fourth embodiment. The fourth embodiment differs from the third embodiment in the following points.

The gain output unit 22 linearly increases from 1 to 2/√3 in the range of 0deg<φ<30deg, linearly decreases from 2/√3 to 1 in the range of 30deg<φ<60deg, and then By repeating this, a gain Gi corresponding to the phase difference φ is output.

That is, the correction coefficient is set to 2/√3 when the phase difference φ is 30deg, 90deg, 150deg, 210deg, 270deg, and 330deg, and the correction coefficient is set to 1 when the phase difference φ is 0deg, 60deg, 120deg, 180deg, 240deg, and 300deg. , the gain Gi obtained by linear interpolation of the correction coefficient in the phase difference φ between the Multiply by .

A gain Gi is also input to the calculators 15a, 15b, and 15c. The arithmetic expressions of the calculators 15a, 15b and 15c are changed to the expressions (19-1), (19-2) and (19-3). Expressions (19-1), (19-2), and (19-3) are the positive phase d-axis voltage V1d of expressions (14-1), (14-2), and (14-3). term is multiplied by the gain Gi.

The calculation results of the zero-phase d-axis voltage V0d are multiplied by the gains G1, G2, and G3 and added together as in the third embodiment. The arithmetic expression for obtaining the zero-phase q-axis voltage V0q is similarly changed.

The fourth embodiment is a method in which the interpolation error in the third embodiment is further reduced. In order to evaluate the interpolation error, the phase difference φ is used to express the anti-phase d-axis current I2d and the anti-phase q-axis current I2q by equation (15).

Substituting equation (15) into equation (5) yields equation (16).

Equation (16) is equivalent to Equation (5), and the zero-phase voltage at a=1 cannot be obtained. Here, consider the influence of linear interpolation when a≈0. Equation (16) can be approximated to Equation (17) by regarding a ² as zero.

The zero-phase voltage is obtained from the positive-phase d-axis voltage V1d, the negative-phase d-axis voltage V2d, the negative-phase q-axis voltage V2q, as well as the corrected amplitude ratio a and the phase difference φ. For the zero-phase d-axis voltage V0d, since a≈0, the coefficient (1−a ^* cosφ) of the anti-phase d-axis voltage V2d can be regarded as approximately 1, and it is almost independent of the corrected amplitude ratio a and the phase difference φ. In the zero-phase q-axis voltage V0q, the anti-phase q-axis voltage V2q is almost independent of the corrected amplitude ratio a and the phase difference φ. Therefore, when a≈0, the anti-phase voltage term is hardly affected by the correction amplitude ratio a and the phase difference φ, and the influence of the error due to interpolation is very small and can be ignored.

However, for the positive-phase d-axis voltage V1d, there is no term that does not depend on the corrected amplitude ratio a, and the first-order term of the corrected amplitude ratio a depends on the trigonometric function of the phase difference φ. Interpolation error due to phase difference φ is received. Evaluating the error of the trigonometric function when linear interpolation is performed for φ=30 deg and 90 deg results in the following equation (18).

In the fourth embodiment, when φ=30 deg, 90 deg, 150 deg, 210 deg, 270 deg, and 330 deg, the term of the positive phase d-axis voltage V1d is multiplied by the gain Gi=2/√3≈1.155 to obtain a triangular shape by linear interpolation. Reduced error of function.

At the phase differences φ=0 deg, 60 deg, 120 deg, 180 deg, 240 deg and 300 deg, the gain Gi is 1 and no correction is performed. The phase in between linearly changes the gain Gi. For example, when the phase difference φ=15 deg, the gain becomes Gi=(2/√3+1)/2≈1.077.

As a result, fluctuations in the cell capacitor voltage when the negative-phase current is suddenly changed can be suppressed at any phase of the negative-phase current, especially at phase differences φ=30deg, 90deg, 150deg, 210deg, 270deg, and 330deg. Equations (19-1), (19-2), and (19-3) are expressions for calculating the zero-phase voltage in the fourth embodiment.

As another interpolation method, for example, a method of pre-calculating the errors in the equations (5) and (14) and creating a table is also conceivable. However, the correction amplitude ratio a, the phase difference φ, the anti-phase d-axis voltage V2d, and the anti-phase q-axis voltage V2q become variables, and the scale of the table becomes large. increases. However, in the fourth embodiment, there are only four correction gains, G1, G2, G3, and Gi, and since all of the correction gains can be expressed by a combination of linear expressions of the phase difference φ, they can be easily realized. .

The fourth embodiment has effects similar to those of the third embodiment. Further, in the fourth embodiment, fluctuations in the cell capacitor voltage when the voltage/current suddenly changes can be suppressed as compared with the third embodiment.

The operating principle of the cell capacitor balance control of the present invention will be described below. FIG. 8 is a phasor diagram when only positive phase current (reactive power) is output in a three-phase balanced system. A thin solid line represents the phase voltage, and a thick dotted line represents the output current. Since the voltage and current of each phase are orthogonal to each other, the active power input and output are zero and the cell capacitor voltages are balanced.

FIG. 9 is a phasor diagram when a positive-sequence current and a negative-sequence current with a small amplitude ratio are output in a three-phase balanced system. In FIG. 9A before the zero-phase voltage is superimposed, the U-phase voltage and current are orthogonal, but the V-phase outputs active power and the W-phase inputs active power. Although the active power input/output in the entire device is zero, the V-phase cell capacitor voltage decreases and the W-phase cell capacitor voltage increases, resulting in an imbalance in the cell capacitor voltages.

Here, when the zero-phase voltage V0 as shown in FIG. 9B is superimposed, the V-phase and W-phase voltages and currents are orthogonal, and the active power can be made zero. This balances the cell capacitor voltages.

FIG. 10 is a phasor diagram when a positive-sequence current and a negative-sequence current of equal amplitude are output in a three-phase balanced system. In FIG. 10 as well, the active power input/output of the entire device is zero, but the V-phase cell capacitor voltage decreases and the W-phase cell capacitor voltage increases. However, in FIG. 10, even if any zero-phase voltage is superimposed, the V-phase and W-phase voltages and currents cannot be orthogonalized at the same time, and the balance of the cell capacitor voltage is lost. Under conditions where the amplitudes of the positive and negative sequence currents are equal, most of the cell capacitor voltages cannot be balanced.

FIG. 11 is also a phasor diagram when a positive-sequence current and a negative-sequence current of equal amplitude are output in a three-phase balanced system, but the phase relationship between the positive-sequence current and the negative-sequence current is different from that in FIG. Under this condition, the U-phase active power is zero because Iu=0. FIG. 11B shows the case of the first embodiment. Here, when a zero-phase voltage V0 having half the amplitude of the U-phase voltage is superimposed as shown in FIG. cell capacitor voltages can be balanced.

FIGS. 11(c) and 11(d) show the cases of the second to fourth embodiments. When a U-phase ground fault occurs as shown in Fig. 11(c), if the amplitude of the U-phase output voltage is reduced to 1/3 (zero-phase voltage only), the V-phase and W-phase voltages and currents remain orthogonal. Therefore, the cell capacitor voltages are balanced. When a short circuit between VW lines occurs as shown in FIG. 11(d), if the U-phase output voltage is not changed and the V-phase and W-phase output voltages are set to zero (including the zero-phase voltage), then Vv=0 , Vw=0, the active power of the three phases is kept zero and the cell capacitor voltages are balanced. In FIG. 11, I2d=0 and I2q=I1q, satisfying the above equation (7). In addition, in both cases (c) and (d), since V2q=0 is satisfied, the cell capacitor voltages can be balanced.

The effectiveness of the first to fourth embodiments described above was confirmed by simulation. The simulation conditions are system voltage 6.6 kV, 50 Hz, device capacity 1 MVA, capacity 2,200 μF, bridge cell B equipped with a capacitor with a rated voltage of 1060 V, 8 units per phase, a total of 24 units to configure the SSBC type MMCC. bottom. For the control, feedback control is also used in addition to Embodiments 1 to 4.

FIG. 12 shows simulation waveforms when I2d=0 and I2q=I1q in a three-phase balanced system. Line-to-line voltage, output current, and cell capacitor voltage average value for each phase are shown from the top. Thin lines at the bottom indicate the maximum and minimum voltages of the 24 cell capacitors. Since the U-phase current amplitude is almost zero, it can be seen that the output of the positive-phase current and the negative-phase current of equal amplitude can be realized and the balance of the cell capacitor voltage can be maintained.

FIG. 13 shows waveforms when a U-phase ground fault is generated at time 0 sec under the same conditions as in FIG. Due to the delay in the moving average filter used to detect the negative phase voltage, the cell capacitor voltage balance is temporarily disturbed, but it is only about 20 V and 2%. At time 0.05 sec, the balance is restored and the operation can be continued.

FIG. 14 shows waveforms when a VW line-to-line short circuit occurs at time 0 sec. Although the U-phase cell capacitor voltage drops temporarily, it is smaller than the steady ripple before time 0 sec, and after 0.05 sec, it is balanced and operation can be continued. After that, the cell capacitor voltages of all phases gradually decreased, but this is because the steady-state loss of the device cannot be compensated for by the system side due to the line-to-line short circuit. In this simulation, it is sufficiently possible to continue operation for 0.3 sec required by FRT (Fault Ride Through) requirements. If continuous operation for a longer period of time is required, it can be dealt with by increasing the capacity of the cell capacitor.

Although the present invention has been described in detail only with respect to the specific examples described above, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are, of course, covered by the claims.

6, 10... dq inverse transformer 7, 8, 9, 14... Multiplier 11a, 11b... Adder 12... dq converter 13, 16, 17... Switch 15... Computing unit 26... Zero phase voltage calculator 27... Current Command value calculator MAVE1, MAVE2...Moving average filter

Claims (4)

A three-phase modular multilevel cascade converter having three modules, wherein a plurality of bridge cells are connected in series to form a one-phase module,
calculating a positive-sequence d-axis voltage based on the system voltage detection signal, calculating a corrected amplitude ratio based on the ratio of the amplitude of the negative-sequence current to the amplitude of the positive-sequence current and the phase difference between the positive-sequence current and the negative-sequence current; A zero-phase d-axis voltage and a zero-phase q-axis voltage are calculated based on the positive-phase d-axis voltage and the corrected amplitude ratio, and a difference between the zero-phase d-axis voltage and a cosine value corresponding to the phase of the system voltage detection signal is calculated. a zero-phase voltage calculator that calculates a zero-phase voltage by adding the product and the product of the zero-phase q-axis voltage and a sine value corresponding to the phase of the system voltage detection signal;
A negative-phase current command value is obtained based on the positive-phase q-axis current command value, the ratio of the amplitude of the negative-phase current to the amplitude of the positive-phase current, and the phase difference, and the current command value superimposed on the negative-phase current command value is obtained. A current command value calculation unit for calculating,
An output voltage command value for each phase is generated based on the current command value, and a value obtained by adding the zero-phase voltage to the output voltage command value for each phase is compared with a carrier triangular wave corresponding to each bridge cell. a current controller that generates a gate signal for each bridge cell ;
prepared ,
When the output voltage and output current of the modular multi-level cascade converter are defined by equations (2), (3), and (15), the zero-phase voltage calculation unit determines that the phase difference is 0 deg, The closest phase difference is selected from 60 deg, 120 deg, 180 deg, 240 deg, and 300 deg, and when the phase difference is 0 deg and 180 deg (10-1), when the phase difference is 120 deg and 300 deg (10-2) A modular multi-level cascade converter, wherein the zero-phase d-axis voltage and the zero-phase q-axis voltage are calculated based on the equation (10-3) when the phase difference is 240 deg and 60 deg.

Vu, Vv, Vw: U-phase output voltage, V-phase output voltage, W-phase output voltage V1d: Positive phase d-axis voltage V2d: Negative phase d-axis voltage V2q: Negative phase q-axis voltage V0d: Zero phase d-axis Voltage V0q: Zero-phase q-axis voltage ωt: System voltage phase φ: Phase difference between positive-phase current and negative-phase current
a': Ratio of negative-sequence current amplitude to positive-sequence current amplitude (a'=√(I2d* ² +I2q* ² )/|I1q*|, where I1d*=0)
a: corrected amplitude ratio where a=a' (φ=0deg, 120deg, 240deg)
a = -a' (φ = 60deg, 180deg, 300deg)
Iu, Iv, Iw : U-phase output current, V-phase output current, W-phase output current I1q: Positive phase q-axis current I2d: Negative phase d-axis current I2q: Negative phase q-axis current
I2d*: Negative phase d-axis current command value
I2q*: Anti-phase q-axis current command value
I1d*: positive phase d-axis current command value
I1q*: positive phase q-axis current command value A three-phase modular multilevel cascade converter having three modules, wherein a plurality of bridge cells are connected in series to form a one-phase module,
calculating a positive-sequence d-axis voltage based on the system voltage detection signal, calculating a corrected amplitude ratio based on the ratio of the amplitude of the negative-sequence current to the amplitude of the positive-sequence current and the phase difference between the positive-sequence current and the negative-sequence current; A zero-phase d-axis voltage and a zero-phase q-axis voltage are calculated based on the positive-phase d-axis voltage and the corrected amplitude ratio, and a difference between the zero-phase d-axis voltage and a cosine value corresponding to the phase of the system voltage detection signal is calculated. a zero-phase voltage calculator that calculates a zero-phase voltage by adding the product and the product of the zero-phase q-axis voltage and a sine value corresponding to the phase of the system voltage detection signal;
A negative-phase current command value is obtained based on the positive-phase q-axis current command value, the ratio of the amplitude of the negative-phase current to the amplitude of the positive-phase current, and the phase difference, and the current command value superimposed on the negative-phase current command value is obtained. A current command value calculation unit for calculating,
An output voltage command value for each phase is generated based on the current command value, and a value obtained by adding the zero-phase voltage to the output voltage command value for each phase is compared with a carrier triangular wave corresponding to each bridge cell. a current controller that generates a gate signal for each bridge cell ;
prepared ,
When the output voltage and output current of the modular multi-level cascade converter are defined by equations (2), (3), and (15), the zero-phase voltage calculation unit determines that the phase difference is 0 deg, The closest phase difference is selected from 60 deg, 120 deg, 180 deg, 240 deg, and 300 deg, and when the phase difference is 0 deg and 180 deg (14-1), when the phase difference is 120 deg and 300 deg (14-2) A modular multi-level cascade converter, wherein the zero-phase d-axis voltage and the zero-phase q-axis voltage are calculated based on the equation (14-3) when the phase difference is 240 deg and 60 deg.

Vu, Vv, Vw: U-phase output voltage, V-phase output voltage, W-phase output voltage V1d: Positive phase d-axis voltage V2d: Negative phase d-axis voltage V2q: Negative phase q-axis voltage V0d: Zero phase d-axis Voltage V0q: Zero-phase q-axis voltage ωt: System voltage phase φ: Phase difference between positive-phase current and negative-phase current
a': Ratio of negative-sequence current amplitude to positive-sequence current amplitude (a'=√(I2d* ² +I2q* ² )/|I1q*|, where I1d*=0)
a: corrected amplitude ratio where a=a' (φ=0deg, 120deg, 240deg)
a = -a' (φ = 60deg, 180deg, 300deg)
Iu, Iv, Iw : U-phase output current, V-phase output current, W-phase output current I1q: Positive phase q-axis current I2d: Negative phase d-axis current I2q: Negative phase q-axis current
I2d*: Negative phase d-axis current command value
I2q*: Anti-phase q-axis current command value
I1d*: positive phase d-axis current command value
I1q*: positive phase q-axis current command value A three-phase modular multilevel cascade converter having three modules, wherein a plurality of bridge cells are connected in series to form a one-phase module,
calculating a positive-sequence d-axis voltage based on the system voltage detection signal, calculating a corrected amplitude ratio based on the ratio of the amplitude of the negative-sequence current to the amplitude of the positive-sequence current and the phase difference between the positive-sequence current and the negative-sequence current; A zero-phase d-axis voltage and a zero-phase q-axis voltage are calculated based on the positive-phase d-axis voltage and the corrected amplitude ratio, and a difference between the zero-phase d-axis voltage and a cosine value corresponding to the phase of the system voltage detection signal is calculated. a zero-phase voltage calculator that calculates a zero-phase voltage by adding the product and the product of the zero-phase q-axis voltage and a sine value corresponding to the phase of the system voltage detection signal;
A negative-phase current command value is obtained based on the positive-phase q-axis current command value, the ratio of the amplitude of the negative-phase current to the amplitude of the positive-phase current, and the phase difference, and the current command value superimposed on the negative-phase current command value is obtained. A current command value calculation unit for calculating,
An output voltage command value for each phase is generated based on the current command value, and a value obtained by adding the zero-phase voltage to the output voltage command value for each phase is compared with a carrier triangular wave corresponding to each bridge cell. a current controller that generates a gate signal for each bridge cell ;
prepared ,
When the output voltage and the output current of the modular multi-level cascade converter are defined by the formulas (2), (3) and (15), the zero-phase voltage calculation section calculates that the phase difference is 0 deg, When the phase difference is 180 deg, expression (14-1), when the phase difference is 120 deg and 300 deg, expression (14-2), and when the phase difference is 240 deg and 60 deg, the zero-phase d-axis voltage is calculated based on expression (14-3). , the zero-phase q-axis voltage is calculated, and if the phase difference is not 0 deg, 60 deg, 120 deg, 180 deg, 240 deg, or 300 deg, from the two closest phase differences (14-1), (14-2) , (14-3) to obtain the two zero-phase d-axis voltages and the zero-phase q-axis voltage, and interpolate the two zero-phase d-axis voltages and the zero-phase q-axis voltage to obtain the zero-phase d-axis voltage A modular multi-level cascade converter, characterized in that it determines a voltage, said zero-phase q-axis voltage.

Vu, Vv, Vw: U-phase output voltage, V-phase output voltage, W-phase output voltage V1d: Positive phase d-axis voltage V2d: Negative phase d-axis voltage V2q: Negative phase q-axis voltage V0d: Zero phase d-axis Voltage V0q: Zero-phase q-axis voltage ωt: System voltage phase φ: Phase difference between positive-phase current and negative-phase current
a': Ratio of negative-sequence current amplitude to positive-sequence current amplitude (a'=√(I2d* ² +I2q* ² )/|I1q*|, where I1d*=0)
a: corrected amplitude ratio However, in the formula (14-1), a = a'(φ<90deg,270deg<φ)
a=-a'(90deg<φ<270deg)
(14-2), a=a'(30deg<φ<210deg)
a=-a'(φ<30deg,210deg<φ)
In the formula (14-3), a=a'(150deg<φ<330deg)
a=-a'(φ<150deg,330deg<φ)
Iu, Iv, Iw : U-phase output current, V-phase output current, W-phase output current I1q: Positive phase q-axis current I2d: Negative phase d-axis current I2q: Negative phase q-axis current
I2d*: Negative phase d-axis current command value
I2q*: Anti-phase q-axis current command value
I1d*: positive phase d-axis current command value
I1q*: positive phase q-axis current command value The zero-phase voltage calculator sets the correction coefficient to 2/√3 when the phase difference is 30deg, 90deg, 150deg, 210deg, 270deg and 330deg, When the correction coefficient is set to 1, the gain Gi obtained by interpolating the correction coefficient for the phase difference between 4. Modular multilevel cascade converter according to claim 3, characterized in that the voltage dependent terms are multiplied.

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