JP7304279B2 - charge pump circuit, semiconductor device, power management circuit - Google Patents

Description

The present invention relates to charge pump circuits.

A charge pump circuit is used when a voltage higher than the power supply voltage is required. The charge pump circuit includes a flying capacitor and an output capacitor, and boosts the input voltage by repeating the operation of charging the flying capacitor with an input voltage and transferring the charge stored in the flying capacitor to the output capacitor.

JP 2011-066750 A

The inventor of the present invention has studied a case where a variable capacitive load is connected to the output of a charge pump circuit, and has come to recognize the following problems.

Assuming a light capacitive load, if the flying capacitor is designed to be small, it will require a large number of switching times to maintain a constant output voltage level when the capacitive load increases, resulting in low power consumption. increase.

On the other hand, if the flying capacitor is designed to be large assuming a situation where the capacitive load is large, when the capacitive load is small, the rise of the output voltage per switching becomes large, resulting in an overshoot of the output voltage. quantity increases.

The present invention has been made in such a situation, and one exemplary object of certain aspects thereof is to provide a charge pump circuit that suppresses the amount of overshoot of the output voltage and/or reduces power consumption.

One aspect of the invention relates to a charge pump circuit. The charge pump circuit includes an output terminal to which the variable load is connected, a flying capacitor, an auxiliary capacitor connected between the output terminal and ground in a first mode, and connected in parallel with the flying capacitor in a second mode. Prepare.

Another aspect of the present invention is a semiconductor device. This semiconductor device includes a charge pump circuit for boosting an input voltage, an output pin to which an external load is connected, a starter circuit provided between the output pins of the charge pump circuit, and a starter circuit provided in parallel. and a bypass switch. The charge pump circuit includes a flying capacitor and an auxiliary capacitor connected between the output terminal and ground in a first mode and connected in parallel with the flying capacitor in a second mode, to drive the output voltage of the charge pump circuit to its target level. A hysteresis comparator that compares with a corresponding threshold voltage, and an oscillator whose operation and stop are controlled according to the output of the hysteresis comparator.

Arbitrary combinations of the above constituent elements, and mutual replacement of the constituent elements and expressions of the present invention between methods, devices, systems, etc. are also effective as aspects of the present invention.

According to one aspect of the present invention, it is possible to suppress the amount of overshoot in the output voltage of the charge pump circuit and/or reduce power consumption.

1 is a block diagram of a charge pump circuit according to an embodiment; FIG. 3 is a circuit diagram showing a specific configuration example of a charge pump circuit; FIG. 3 is an operation waveform diagram of the charge pump circuit of FIG. 2; FIG. FIGS. 4A and 4B are waveform diagrams of the output voltage VCP of Comparative Technique 1 and the embodiment. 5(a) and 5(b) are waveform diagrams of the output voltage VCP of the comparison technique 2 and the embodiment. 3 is a circuit diagram of a semiconductor device including the charge pump circuit of FIG. 2; FIG. 4 is a circuit diagram showing a configuration example of a startup circuit; FIG. 7 is an operation waveform diagram (simulation result) of the semiconductor device of FIG. 6; FIG. 1 is a block diagram of a power management circuit according to an embodiment; FIG. It is a circuit diagram of a starting circuit according to a modification. FIG. 10 is a diagram showing a peripheral circuit of a semiconductor device according to Modification 2;

(Overview of Embodiment)
One embodiment disclosed herein relates to a charge pump circuit. The charge pump circuit has an output terminal to which the variable load is connected, a flying capacitor, and an auxiliary capacitor connected between the output terminal and ground in a first mode and connected in parallel with the flying capacitor in a second mode. Prepare.

In this configuration, in the second mode, since the auxiliary capacitor is connected to the flying capacitor, the effective capacitance value of the flying capacitor becomes larger than in the first mode. By selecting the first mode or the second mode according to the state of the variable load, it is possible to suppress the amount of overshoot of the output voltage and reduce power consumption.

The variable load may be a variable capacitive load. The first mode and the second mode may be selected according to the capacity of the variable load. When the load capacity is small, the overshoot amount of the output voltage can be suppressed by selecting the first mode. When the load capacitance is large, by selecting the second mode, the amount of charge transferred to the load capacitance per switching operation can be increased, so the switching frequency required to maintain the output voltage level and, in turn, the power consumption can be reduced. be able to.

The first mode and the second mode may be selected according to the current flowing through the variable load. For example, the first mode may be selected in a variable light load state, and the second mode may be selected in a variable heavy load state.

The charge pump circuit may further comprise an output capacitor fixedly connected between the output terminal and ground. By providing the output capacitor, it is possible to prevent the output voltage from becoming an overvoltage when the capacitive load is disconnected.

The capacitance value of the auxiliary capacitor may be greater than the capacitance value of the output capacitor.

The charge pump circuit may include a hysteresis comparator that compares the voltage of the output terminal with a threshold voltage, and operate intermittently according to the output of the hysteresis comparator. In a light load or no-load state, an operation is repeated in which the output voltage increases during the operation period and decreases during the non-operation period. When the second mode is selected, the effective capacitance of the flying capacitor is increased, so that the range of increase in the output voltage during the operation period can be increased. Therefore, the length of the idle period following the operating period can be lengthened, and power consumption can be reduced.

The threshold voltage may be different between the first mode and the second mode. Since the hysteresis comparator has a non-negligible response delay, if the same threshold voltage is set in the first mode and the second mode, the fluctuation range of the ripple of the output voltage of the charge pump circuit is the same in the first mode and the second mode. may disappear. In this case, by individually setting the threshold value of the hysteresis comparator for each mode, it is possible to uniform the peak voltage, bottom voltage, or center voltage of the ripple of the output voltage of the charge pump circuit.

The clock frequency of the charge pump circuit may differ between the first mode and the second mode. By setting the clock frequency separately for the period of operation in the first mode and the period of operation in the second mode, the current supply amount (load capacitance) of the charge pump circuit can be adjusted according to the state of the load in each mode. can be optimized.

One embodiment disclosed herein is a semiconductor device. This semiconductor device includes a charge pump circuit for boosting an input voltage, an output pin to which an external load is connected, a starter circuit provided between the output pins of the charge pump circuit, and a starter circuit provided in parallel. and a bypass switch that compares the voltage at the output pin with a predetermined set voltage and turns off the bypass switch when the voltage at the output pin is lower and turns off the bypass switch when the voltage at the output pin is higher and a determination circuit that The charge pump circuit includes a flying capacitor and an auxiliary capacitor connected between the output terminal and ground in a first mode and connected in parallel with the flying capacitor in a second mode, to drive the output voltage of the charge pump circuit to its target level. A hysteresis comparator that compares with a corresponding threshold voltage, and an oscillator whose operation and stop are controlled according to the output of the hysteresis comparator.

The load impedance viewed from the output terminal of the charge pump circuit changes discontinuously depending on whether the bypass switch is turned on or off. Therefore, by dynamically controlling the mode according to the load impedance seen from the charge pump circuit, the amount of overshoot of the output voltage of the charge pump circuit can be suppressed and the power consumption can be reduced.

The charge pump circuit may further comprise an output capacitor fixedly connected between the output terminal and ground. By providing the output capacitor, it is possible to prevent the output voltage of the charge pump circuit from becoming excessive when the load is removed from the output pin.

When the bypass switch is off, the load is invisible from the output terminal of the charge pump circuit, so the load capacitance is small. growing. Therefore, the first mode and the second mode may be switched in conjunction with turning on/off of the bypass switch.

The clock frequency of the charge pump circuit in the first mode may be higher than the clock frequency in the second mode. The clock frequency in the first mode may be determined according to the amount of current supplied to the load by the activation circuit, and the clock frequency in the second mode may be determined so as to keep the voltage supplied to the load at a constant level. .

The threshold voltage may change in association with turning on/off of the bypass switch. Since the hysteresis comparator has a non-negligible response delay, if the same threshold voltage is set in the first mode and the second mode, the fluctuation range of the ripple of the output voltage of the charge pump circuit is the same in the first mode and the second mode. may disappear. In this case, by individually setting the threshold value of the hysteresis comparator for each mode, it is possible to align the peak voltages, bottom voltages, or ripple center voltages of the output voltages of the charge pump circuits.

The starting circuit may include a constant current circuit that supplies a constant current to the load. The activation circuit may include a resistive element.

The load may be a load switch that is a MOS transistor, and the gate of the MOS transistor may be connected to the output pin. The charge pump circuit may be active while the load switch should be on.

The semiconductor device is a power management circuit, and may further include a DC/DC converter that supplies voltage to one end of the load switch.

(Embodiment)
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. Moreover, the embodiments are illustrative rather than limiting the invention, and not all features and combinations thereof described in the embodiments are necessarily essential to the invention.

In this specification, "a state in which member A is connected to member B" refers to a case in which member A and member B are physically directly connected, and that member A and member B are electrically connected to each other. It also includes the case of being indirectly connected through other members that do not substantially affect the physical connection state or impair the functions and effects achieved by their combination.

Similarly, "the state in which member C is provided between member A and member B" refers to the case where member A and member C or member B and member C are directly connected, as well as the case where they are electrically connected. It also includes the case of being indirectly connected through other members that do not substantially affect the physical connection state or impair the functions and effects achieved by their combination.

Also, in this specification, the symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors and capacitors, refer to respective voltage values, current values, resistance values, and capacitance values as necessary. shall be represented.

FIG. 1 is a block diagram of a charge pump circuit 100 according to an embodiment. The charge pump circuit 100 has an input terminal CPIN and an output terminal CPOUT. An input voltage _VSYS is input to the input terminal CPIN. A capacitive load 2 is connected to the output terminal CPOUT. Assume that the capacitance C _LOAD of this load 2 is variable.

The charge pump circuit 100 boosts the input voltage _VSYS and outputs the output voltage _VCP stabilized at a predetermined voltage level _VCP ( _REF ) from the output terminal CPOUT. The boost ratio α of the charge pump circuit 100 is not limited, and may be 1.5 times, 2 times, 3 times, 4 times, etc., and the number of flying capacitors _CF is determined according to the boost ratio.

The following relational expression holds between the target voltage level _VCP(REF) and the input voltage _VSYS , and the charge pump circuit 100 maintains the output voltage _VCP at the target level _VCP(REF). Therefore, intermittent operation is performed.
V _{CP (REF)} < V _SYS × α

Charge pump circuit 100 comprises flying capacitor C _F , auxiliary capacitor C _AUX , output capacitor C _OUT and charge pump core 110 . Charge pump core 110 may include an oscillator, multiple switches, circuitry for regulating the output voltage _VCP, and the like.

The charge pump circuit 100 can operate in a first mode and a second mode. An auxiliary capacitor C _AUX is connected between the output terminal CPOUT and ground in the first mode and in parallel with the flying capacitor C _F in the second mode. The effective capacitance of the flying capacitor in the second mode is
C _{F (EFF)} = C _F +C _AUX
becomes.

For example, selectors SEL1 and SEL2 may be provided across the auxiliary capacitor _CAUX to switch between the first mode and the second mode. Switches may be used instead of the selectors SEL1 and SEL2.

In the present embodiment, switching between the first mode and the second mode is selected in conjunction with the capacity of load 2 . Specifically, the first mode may be selected when the load 2 has a small capacity, and the second mode may be selected when the load 2 has a large capacity. The mode control method is not particularly limited. For example, charge pump circuit 100 may receive a control signal specifying a mode from load 2 . Alternatively, the charge pump circuit 100 may monitor the state of the load 2 and control the mode based on the monitoring results.

FIG. 2 is a circuit diagram showing a specific configuration example of the charge pump circuit 100. As shown in FIG. The charge pump circuit 100 of FIG. 2 has a step-up ratio α of 2. In addition to one flying capacitor C _F , one output capacitor C _OUT , and an auxiliary capacitor C _AUX , four switches (transistors) M1 to M4 are provided. , controller 112, oscillator 114, hysteresis comparator 116, and resistors R11 and R12. The components of the charge pump circuit 100 excluding the capacitors correspond to the charge pump core 110 in FIG.

The connection relationship (topology) between the four switches M1 to M4 and the capacitors C _F and C _OUT is the same as that of a general double boost charge pump.

The oscillator 114 generates the clock signal CLK while the stop signal STOP is negated (low). While the stop signal STOP is asserted (high), the oscillator 114 stops generating the clock signal CLK. The controller 112 synchronizes with the clock signal CLK to switch between a first state φ1 in which the switches M1 and M4 are on and M2 and M3 are off, and a first state φ2 in which the switches M1 and M4 are off and M2 and M3 are on. and repeat alternately. The charge pump circuit 100 operates in an intermittent mode in which stop and operation are alternately repeated in response to the stop signal STOP.

Resistors R11 and R12 divide the output voltage _VCP . The hysteresis comparator 116 compares the divided output voltage (detection voltage) V _CP ' with a threshold voltage V _TH ' based on the target voltage V _{CP (REF)} , and outputs a stop signal STOP according to the comparison result. do. Specifically, the stop signal STOP is asserted (high) when the output voltage V _CP exceeds the upper threshold voltage V _THH and is negated (low) when the output voltage V _CP falls below the lower threshold voltage V _THL . be done.

The capacitance value of the auxiliary capacitor C _AUX is preferably greater than the capacitance value of the output capacitor C _OUT . For example, C _F =8 pF, C _AUX =40 pF, C _OUT =10 pF, and the load capacitance C _LOAD may be several hundred pF.

The above is the basic configuration of the charge pump circuit 100 . Next, the operation will be explained.

FIG. 3 is an operation waveform diagram of charge pump circuit 100 of FIG. Prior to start-up time _t0 , the output voltage _VCP is 0V. Immediately after startup, the capacitance C _LOAD of the load 2 has a relatively small first value _C1 . Charge pump circuit 100 is set in a first mode, with auxiliary capacitor C _AUX connected in parallel with output capacitor C _OUT .

When the output voltage _VCP of the charge pump circuit 100 increases to near the target voltage _VCP(REF) , the charge pump circuit 100 starts intermittent operation.

At time _t1 , the load capacitance C _LOAD increases to a second value _C2 . This sets the charge pump circuit 100 to the second mode and connects the auxiliary capacitor _CAUX in parallel with the flying capacitor _CF.

The above is the operation of the charge pump circuit 100 . Next, the first advantage will be explained in comparison with Comparative Technique 1. FIG. 4(a) and 4(b) are waveform diagrams of the output voltage _VCP of the comparative technique 1 and the embodiment.

(Comparative technique 1)
Please refer to FIG. In comparative technique 1, the flying capacitor C _F is designed to be fixed and large. In this case, when the load capacitance C _LOAD is small, the amount of increase in the output voltage V _CP per one switching of the charge pump circuit 100 becomes large. Then, the output voltage _VCP will greatly exceed the upper threshold _VTHH , and an overvoltage will be applied to the load. In particular, the comparator has a delay so that after the output voltage _VCP exceeds the upper threshold _VTHH , the charge pump circuit 100 does not immediately stop, but after one or more extra switching, it will stop. . This extra switching also causes the output voltage _VCP to jump further, increasing the amount of overshoot _VOS .

Please refer to FIG. In the present embodiment, when the load capacitance C _LOAD is small, the first mode is selected to reduce the effective flying capacitor capacitance C _{F (EFF) .} The amount of increase in is kept small. As a result, the overshoot amount _VOS of the output voltage _VCP can be suppressed, and overvoltage can be prevented.

A second advantage of the charge pump circuit 100 will be described in comparison with the comparative technique 2. FIG. 5(a) and 5(b) are waveform diagrams of the output voltage _VCP of the comparison technique 2 and the embodiment.

(Comparative technique 2)
Please refer to FIG. In comparative technique 2, the flying capacitor C _F is fixedly designed to be small. During the intermittent operation, charge pump circuit 100 needs to increase its output voltage _VCP by a hysteresis width ΔV. If the flying capacitor _{C F} is small, the amount of increase in the output voltage V _CP per switching becomes small when the load capacitance C _LOAD is large. As a result, the power consumption of the charge pump circuit 100 increases.

Please refer to FIG. In the present embodiment, when the load capacitance C _LOAD is large, the second mode is selected to increase the effective flying capacitor capacitance _{CF (EFF)} , thereby increasing the output voltage V _CP per switching. can be prevented from becoming smaller. Therefore, the number of times of switching required to change the output voltage _VCP by ΔV during the intermittent operation can be reduced as compared with the comparison technique 2, and the power consumption of the charge pump circuit 100 can be reduced.

Next, specific applications of the charge pump circuit 100 will be described. FIG. 6 is a circuit diagram of a semiconductor device 200 including the charge pump circuit 100 of FIG.

A load switch 4 as an external load is connected to an output pin LSDRV of the semiconductor device 200 . The load switch 4 is a MOS transistor having a drain to which the input voltage _VIN is applied, a source connected to the smoothing capacitor 8 and the system load 6, and a gate connected to the LSDRV pin. The semiconductor device 200 is a drive circuit for the load switch 4. When the enable signal LS_EN is asserted (for example, high), the load switch 4 is turned on by setting the LSDRV pin, that is, the gate voltage of the load switch 4 to high. , and supplies the voltage V _OUT to the system load 6 . When the enable signal LS_EN is negated (for example, low), the semiconductor device 200 sets the LSDRV pin, ie, the gate voltage of the load switch 4 to low, thereby turning off the load switch 4 and increasing the voltage V to the system load 6 . Cut off the supply of _OUT .

The semiconductor device 200 includes a startup circuit 210, a bypass switch 230, and a determination circuit 240 in addition to the charge pump circuit 100 described above, which are integrated on one semiconductor substrate. Starting circuit 210, bypass switch 230 and load switch 4 correspond to load 2 of charge pump circuit 100 in FIG.

The gate capacitance _CG of the load switch 4 is as large as several hundred to several thousand pF. Therefore, when the charge pump circuit 100 is activated with the output CPOUT of the charge pump circuit 100 directly connected to the gate of the load switch 4 , a rush current flows through the gate capacitance of the load switch 4 . To prevent an inrush current, a startup circuit 210 is provided between the output terminal CPOUT and the output pin OUT of the charge pump circuit 100 . Bypass switch 230 is provided in parallel with activation circuit 210 . The startup circuit 210 becomes active when the bypass switch 230 is off, charges the gate capacitance _CG of the load switch 4 with a constant current, and raises the voltage of the LSDRV pin. The turn-on speed of the load switch 4, that is, the slope of the rise of the output voltage _VOUT is set according to the charging speed of the gate capacitance _CG by the starting circuit 210. FIG.

The determination circuit 240 controls turning on/off of the bypass switch 230 based on the driving voltage _VDRV of the LSDRV pin. Specifically, the voltage V _DRV of the LSDRV pin is divided by resistors R 21 and R 22 and compared with the set voltage V _SET in the determination circuit 240 . Determination circuit 240 turns off bypass switch 230 when drive voltage V _DRV is lower than a predetermined voltage level (eg, 4.95 V), and turns on bypass switch 230 when it exceeds the predetermined voltage level.

When the bypass switch 230 is on, the load capacitance C _LOAD of the charge pump circuit 100 increases because the gate capacitance _CG of the load switch 4 is visible from the output terminal CPOUT of the charge pump circuit 100 . When the bypass switch 230 is turned off, the gate capacitance _{C_G} of the load switch 4 becomes invisible from the output terminal CPOUT of the charge pump circuit 100, so the load capacitance _{C_LOAD} of the charge pump circuit 100 becomes small. That is, the load capacitance C _LOAD of the charge pump circuit 100 changes in conjunction with turning on/off of the bypass switch 230 . Therefore, the operation mode of the charge pump circuit 100 is controlled by the determination circuit 240 in conjunction with the bypass switch 230 .

A mode control signal MODE generated by the determination circuit 240 is supplied to the selectors SEL1 and SEL2. The mode control signal MODE is also supplied to the oscillator 114 . The oscillation frequency of oscillator 114 changes according to mode control signal MODE. Specifically, the oscillation frequency increases in the first mode (referred to as first frequency _f1 ), and the oscillation frequency decreases in the second mode (referred to as second frequency _f2 ). The first frequency _f1 may be determined according to the amount of current that the starting circuit 210 supplies to the gate capacitance _CG of the load switch 4 . The second frequency _f2 may be determined so as to keep the drive voltage _VDRV at a constant level after the charging of the gate capacitance _CG of the load switch 4 is completed. For example, the first frequency _f1 is on the order of several MHz and the second frequency _f2 is on the order of several hundred kHz.

Mode control signal MODE is also supplied to hysteresis comparator 116 . The threshold voltage V _TH ' of the hysteresis comparator 116 may take different values depending on the mode control signal MODE. Specifically, the threshold voltage V _TH1 ' in the first mode should be set lower than the threshold voltage V _TH2 ' in the second mode. In the first mode, since the switching frequency _f1 is high, the number of times of switching increases during the response delay of the hysteresis comparator 116, and therefore the amount of overshoot increases. Therefore, by setting the threshold voltage V _TH1 ' low in anticipation of this overshoot amount, the peak voltage of the output voltage V _CP of the charge pump circuit 100 can be made uniform between the first mode and the second mode. becomes possible. For example, the first mode threshold voltage V _TH1 ' is set to 5.15V, and the second mode threshold voltage V _TH2 ' is set to 5.45V.

FIG. 7 is a circuit diagram showing a configuration example of the activation circuit 210. As shown in FIG. Starting circuit 210 is a constant current circuit and includes constant current source 212 and current mirror circuit 214 . A current mirror circuit 214 multiplies the reference current Ic generated by the constant current source 212 by a constant to generate a starting current I _START and supplies it to the LSDRV pin.

The above is the configuration of the semiconductor device 200 . Next, the operation will be explained. FIG. 8 is an operation waveform diagram (simulation result) of the semiconductor device 200 of FIG. V _SYS =3.3 V, V _IN =1.8 V, and C _G =1 μF. When the turn-on of the load switch 4 is instructed at time _t0 , the operation of the charge pump circuit 100 is started. Immediately after starting, it is in the first mode and operates at the first frequency _f1 . Immediately after startup, the bypass switch 230 is off, the startup circuit 210 becomes active, the gate capacitance _CG of the load switch 4 is charged by the startup current I _START , and the drive voltage V _DRV rises with a constant slope. When the drive voltage V _DRV rises, the load switch 4 turns on and V _OUT =V _IN .

At time _t1 , when the drive voltage _VDRV reaches the set voltage (4.95V), the bypass switch 230 is turned on and the charge pump circuit 100 is set to the second mode. With bypass switch 230 on, V _DRV =V _CP .

After time _t1 , the charge pump circuit 100 operates at the second frequency _f2 , so power consumption can be significantly reduced. Further, in the first mode, the ratio of the operation period of the charge pump circuit 100 (duty ratio of the stop signal STOP) is large, whereas in the second mode, the duty ratio of the stop signal STOP is small and the stop period is long. Therefore, the power consumption of the circuit can be further reduced.

Also, the threshold voltage of the hysteresis comparator 116 is set to be different between the first mode and the second mode. Therefore, the ripple peaks of the output voltage _VP of the charge pump circuit 100 can be aligned.

FIG. 9 is a block diagram of a power management circuit (PMIC: Power Manage Integrated Circuit) 300 according to the embodiment. The PMIC 300 includes a converter controller 310 , an LDO (Low Drop Output) (not shown), and a state machine 320 in addition to the semiconductor device 200 described above. Converter controller 310 configures a DC/DC converter together with external inductor L1 and capacitor C1. The load switch 4 is supplied with the output voltage of the DC/DC converter. State machine 320 first gives activation instruction DCDC_EN to converter controller 310 , and when the output voltage of the DC/DC converter reaches the target voltage, asserts activation instruction LS_EN to charge pump circuit 100 to turn on load switch 4 .

The present invention has been described above based on the embodiments. It should be understood by those skilled in the art that this embodiment is merely an example, and that various modifications can be made to the combination of each component and each treatment process, and that such modifications are within the scope of the present invention. be. Such modifications will be described below.

(Modification 1)
FIG. 10 is a circuit diagram of a starting circuit 210A according to a modification. The starting circuit 210A includes a resistor 216 for preventing rush current. In this case, with the bypass switch 230 off, the voltage V _DRV on the LSDRV pin rises according to the CR time constant.

(Modification 2)
In the semiconductor device 200 of FIG. 6, the load connected to the LSDRV pin is not limited to the load switch. FIG. 11 is a diagram showing peripheral circuits of a semiconductor device 200 according to Modification 2. As shown in FIG. A smoothing capacitor 10 and a system load 20 are connected to the LSDRV pin of the semiconductor device 200 . The system load 20 is light in sleep mode and heavy in operation.

In such a system, the load capacitance C _LOAD viewed from the output of the charge pump circuit 100 dynamically changes depending on whether the bypass switch 230 is turned on or off. Also, the load current I _LOAD of the charge pump circuit 100 dynamically changes according to the operating state of the system load 20 . In such an application, the operation mode of charge pump circuit 100 may be changed according to the combination of the state of bypass switch 230 and system load 20 .

(Modification 3)
In the semiconductor device 200 of FIG. 6, the operation mode of the charge pump circuit 100 is interlocked with the on/off of the bypass switch 230, but this is not the only option. For example, the operation mode of charge pump circuit 100 may be switched based on the elapsed time from the start of activation, or the operation mode may be switched based on a command from a higher-level controller.

Although the present invention has been described using specific terms based on the embodiments, the embodiments merely show the principles and applications of the present invention, and the embodiments are defined in the scope of claims. Many modifications and changes in arrangement are permitted without departing from the spirit of the present invention.

2 load 4 load switch 6 system load 8, 10 smoothing capacitor 20 system load 100 charge pump circuit C _F flying capacitor C _AUX auxiliary capacitor C _OUT output capacitor M1, M2, M3, M4 switch 110 charge pump core 112 controller 114 oscillator 116 Hysteresis comparator R11, R12 resistor 200 semiconductor device 210 startup circuit 230 bypass switch 240 decision circuit 300 PMIC
310 converter controller

Claims (18)

an output terminal to which a variable load is connected;
a flying capacitor;
an auxiliary capacitor connected between the output terminal and ground in a first mode and connected in parallel with the flying capacitor in a second mode;
A charge pump circuit comprising: The variable load is a variable capacitive load,
2. The charge pump circuit according to claim 1, wherein said first mode and said second mode are selected according to the capacitance of said variable load. 3. The charge pump circuit according to claim 1, wherein said first mode and said second mode are selected according to the current flowing through said variable load. 4. The charge pump circuit according to claim 1, further comprising an output capacitor fixedly connected between said output terminal and said ground. 5. The charge pump circuit according to claim 4, wherein the capacitance value of said auxiliary capacitor is greater than the capacitance value of said output capacitor. 6. The charge pump circuit according to claim 1, wherein the charge pump circuit includes a hysteresis comparator that compares the voltage of the output terminal with a threshold voltage, and intermittently operates according to the output of the hysteresis comparator. charge pump circuit. 7. The charge pump circuit according to claim 6, wherein said threshold voltage differs between said first mode and said second mode. 8. The charge pump circuit according to claim 1, wherein a clock frequency of said charge pump circuit differs between said first mode and said second mode. a charge pump circuit that boosts the input voltage;
an output pin to which an external load is connected;
a startup circuit provided between the output terminal of the charge pump circuit and the output pin;
a bypass switch provided in parallel with the startup circuit;
comparing the voltage of the output pin with a predetermined set voltage, turning off the bypass switch when the voltage of the output pin is lower, and turning off the bypass switch when the voltage of the output pin is higher a judgment circuit for
with
The charge pump circuit is
a flying capacitor;
an auxiliary capacitor connected between the output terminal and ground in a first mode and connected in parallel with the flying capacitor in a second mode;
a hysteresis comparator that compares the output voltage of the charge pump circuit with a threshold voltage corresponding to its target level;
an oscillator whose operation and stop are controlled according to the output of the hysteresis comparator;
A semiconductor device comprising: 10. The semiconductor device according to claim 9, wherein said charge pump circuit further comprises an output capacitor fixedly connected between said output terminal and said ground. 11. The semiconductor device according to claim 9, wherein said first mode and said second mode are switched in conjunction with turning on and off of said bypass switch. 12. The semiconductor device according to claim 9, wherein the clock frequency of said charge pump circuit in said first mode is higher than the clock frequency in said second mode. 13. The semiconductor device according to claim 9, wherein said threshold voltage changes in association with turning on/off of said bypass switch. 14. The semiconductor device according to claim 9, wherein said starting circuit includes a constant current circuit that supplies a constant current to said load. 14. The semiconductor device according to claim 9, wherein said starting circuit includes a resistance element. 16. The semiconductor device according to claim 9, wherein said load is a load switch that is a MOS transistor, and said output pin is connected to the gate of said MOS transistor. 17. The semiconductor device according to claim 16, wherein said charge pump circuit is active during a period in which said load switch should be turned on. The semiconductor device is a power management circuit,
18. The semiconductor device according to claim 16, further comprising a DC/DC converter that supplies voltage to one end of said load switch.

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