JP7204828B2 - Controlling reverse current in switch-mode power supplies to achieve zero-voltage switching - Google Patents

Description

The present disclosure relates to controlling reverse current in switch mode power supplies to achieve zero voltage switching.

This paragraph provides background information related to the present disclosure that is not necessarily prior art.

Power supplies generally include one or more power converter stages for converting input currents and voltages to output currents and voltages. A power converter stage may include, for example, a resonant power converter such as a multi-level LLC power converter or an interleaved resonant bus power converter. The power converter stage switches can be controlled with a fixed or variable switching frequency or duty cycle to achieve zero voltage switching (ZVS).

This paragraph provides a general overview of the disclosure and is not a comprehensive disclosure of its full scope or all of its features.

According to one aspect of the disclosure, a switched mode power supply (SMPS) includes a multi-level step-down power converter, a resonant power converter, and a control circuit. The multi-level step-down power converter includes an input, an output, a first step-down circuit and a second step-down circuit respectively coupled between the input and the output. A first step-down circuit includes a power switch, a rectifier, and an inductor, and a second step-down circuit includes a power switch, a rectifier, and an inductor. A resonant power converter is coupled to the output of the multi-level step-down power converter. A control circuit is coupled to the first step-down circuit and the second step-down circuit. The control circuit generates a first control signal for the power switch of the first buck circuit and a second control signal for the power switch of the second buck circuit to control the multi-level buck power converter. configured to

According to another aspect of the disclosure, a SMPS includes a multi-level step-down power converter and control circuitry. A multi-level step-down power converter includes a first step-down circuit and a second step-down circuit. A first step-down circuit includes a power switch, a rectifier, and an inductor, and a second step-down circuit includes a power switch, a rectifier, and an inductor. A control circuit is coupled to the first step-down circuit and the second step-down circuit. The control circuit generates a first control signal for the power switch of the first buck circuit and a second control signal for the power switch of the second buck circuit to provide multi-level buck power in continuous conduction mode. controlling the converter so that a reverse current flows in the first step-down circuit and the second step-down circuit, and adjusting the switching frequencies of the first control signal and the second control signal, The amount of reverse current flowing through one buck circuit and said second buck circuit is controlled to switch the power switch of the first buck circuit and the second buck circuit while the multi-level buck power converter is in its continuous conduction mode. It is configured to achieve zero voltage switching (ZVS) of the power switch of the step-down circuit.

Further aspects and areas of applicability will become apparent from the description provided herein. It is to be understood that various aspects of the disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

The drawings described herein are for purposes of illustration of selected embodiments only, are not all possible implementations, and are not intended to limit the scope of the disclosure.

2 is a block diagram of an SMPS including a multi-level step-down power converter and control circuitry for adjusting the switching frequency of switches within the power converter to achieve ZVS, according to one exemplary embodiment of the present disclosure; FIG. be. 2 is a schematic circuit diagram of a multi-level step-down power converter usable in the SMPS of FIG. 1, according to another exemplary embodiment; FIG. 3 is a timing diagram of control signals for controlling the switches of the multi-level step-down power converter of FIG. 2; FIG. 3 is a graph of voltage waveforms associated with the power switch of the power converter of FIG. 2, wherein the switch has not achieved ZVS; 3 is a graph of voltage waveforms associated with power switches of the power converter of FIG. 2, wherein the switches achieve ZVS; 3 is a timing diagram of control signals with non-overlapping on-times for controlling the switches of the power converter of FIG. 2; FIG. 3 is a schematic circuit diagram of the power converter of FIG. 2 showing different current paths through the power converter when control signals with non-overlapping on-times are used; FIG. 3 is a schematic circuit diagram of the power converter of FIG. 2 showing different current paths through the power converter when control signals with non-overlapping on-times are used; FIG. 3 is a schematic circuit diagram of the power converter of FIG. 2 showing different current paths through the power converter when control signals with non-overlapping on-times are used; FIG. 3 is a graph of voltage and current waveforms associated with the power converter of FIG. 2 when control signals with non-overlapping on-times are used; Graphs of simulated waveforms of peak-to-peak ripple current, power switch turn-on voltage of the power converter of FIG. 2, and output voltage of the power converter of FIG. 2 when control signals with non-overlapping on-times are used; is. 3 is a timing diagram of control signal waveforms with overlapping on-times for controlling the switches of the multi-level step-down power converter of FIG. 2; FIG. 3 is a schematic circuit diagram of the power converter of FIG. 2 showing different current paths through the power converter when control signals with overlapping on-times are used; FIG. 3 is a schematic circuit diagram of the power converter of FIG. 2 showing different current paths through the power converter when control signals with overlapping on-times are used; FIG. 3 is a schematic circuit diagram of the power converter of FIG. 2 showing different current paths through the power converter when control signals with overlapping on-times are used; FIG. 3 is a graph of voltage and current waveforms associated with the power converter of FIG. 2 when control signals with overlapping on-times are used; Graphs of simulated waveforms of peak-to-peak ripple current, power switch turn-on voltage of the power converter of FIG. 2, and output voltage of the power converter of FIG. 2 when control signals with overlapping on-times are used; is. FIG. 4 is a block diagram of an SMPS including a multi-level buck power converter and a resonant power converter according to another exemplary embodiment; FIG. 4 is a schematic circuit diagram of an SMPS including a multi-level step-down power converter and an interleaved resonant bus power converter according to another exemplary embodiment; FIG. 4 is a schematic circuit diagram of an SMPS including a multi-level step-down power converter and a non-interleaved resonant bus power converter according to another exemplary embodiment; FIG. 4 is a schematic circuit diagram of a multi-level step-down power converter including diode rectifiers according to another exemplary embodiment;

Corresponding reference characters indicate corresponding (not necessarily identical) parts and/or features throughout the several views of the drawings.

Example embodiments are provided so that this disclosure will be thorough and will fully convey the scope to those skilled in the art. Numerous specific details are set forth, including examples of specific components, devices, and methods, in order to provide a thorough understanding of the embodiments of the present disclosure. It should be noted that there is no need to use specific details, that example embodiments can be embodied in many different forms, and that none should be construed as limiting the scope of the disclosure. It will be clear to those skilled in the art. In some exemplary embodiments, well-known processes, well-known device structures, and well-known techniques are not described in detail.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" may be intended to include plural forms as well, unless the context clearly indicates otherwise. Although the terms "comprise," "comprise," "include," and "have" are inclusive and thus specify the presence of the recited features, integers, steps, acts, elements and/or components, , does not exclude the presence or addition of one or more other features, integers, steps, acts, elements, components, and/or groups thereof. Method steps, processes, and actions described herein should not be construed as requiring their performance in the particular order described or illustrated, unless specifically identified as an order of performance. . It should also be appreciated that additional or alternative steps may be used.

The terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, although these elements, components, regions, Layers and/or portions should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first," "second," and other numerical terms, as used herein, do not imply an order or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be referred to as a second element, component, region, layer or section without departing from the teachings of the exemplary embodiments. be able to.

Spatially relative terms such as "inner", "outer", "beneath", "below", "lower", "upper", "upper" are used herein as indicated in the figures. may be used to facilitate description to describe the relationship of one element or feature to another. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. For example, if the device in the figures were to be turned over, elements labeled "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both upward and downward orientations. The device may be oriented in other directions (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Exemplary embodiments will now be described more fully with reference to the accompanying drawings.

A switched mode power supply for powering a load according to one exemplary embodiment of the present disclosure is shown in FIG. As shown in FIG. 1, the switched mode power supply 100 includes a multi-level DC-DC step-down power converter 102 having step-down circuits 104, 106 and a control circuit 108 coupled to the step-down circuits 104,106. Step-down circuit 104 includes power switch 110 , rectifier switch 112 and inductor 114 , and step-down circuit 106 includes power switch 116 , rectifier switch 118 and inductor 120 . Control circuit 108 provides control signals 122 for power switches 110, 116 to control multi-level DC-DC step-down power converter 102 in continuous conduction mode (CCM) such that buck circuits 104, 106 have reverse current flow; 124, and while the buck power converter 102 is in its continuous conduction mode, the switching frequency of the control signals 122, 124 is adjusted to reduce the amount of reverse current to achieve ZVS of the power switches 110, 116. configured to control.

By adjusting the switching frequency of the control signals 122, 124 and controlling the amount of reverse current flowing through the step-down circuits 104, 106, the dynamic performance and efficiency of the power supply 100 can be adjusted under various load conditions compared to conventional power supplies. improved over For example, reverse current can flow through each step-down circuit 104, 106 during the freewheeling period. Specifically, when the load current falls below fifty percent (50%) of the peak-to-peak ripple current in inductors 114 and 120, the current through inductors 114 and 120 becomes negative (eg, ripple current minus load current). This causes reverse current to flow from the load through inductors 114, 120 and rectifier switches 112, 118 (eg, field effect transistors such as MOSFETs). For example, during the freewheeling period of buck circuit 104, if the load current drops below 50% of the peak-to-peak ripple current of inductor 114, the output of the power converter will output inductor 114 and rectifier switch 112 (e.g., synchronous rectifier switch, etc.). ) can cause reverse current to flow. For a fixed switching frequency, as the load gets smaller, the amount of reverse current flowing through the buck circuits 104, 106 (eg, through the rectifier switches 112, 118) increases. As the reverse current increases, the root-mean-square (RMS) current through inductors 114 and 120 can increase to undesirable levels, resulting in increased losses.

However, if the switching frequency is changed (eg, when load conditions change), the amount of reverse current flowing through the step-down circuits 104, 106 can be controlled to a desired level. For example, reverse current can be controlled to ensure that ZVS of the power switches 110, 116 is achieved, as described further below. In such an example, reverse current will flow through the rectifier switches 112, 118 and discharge the voltage across the power switches 110, 116 to zero before the power switches 110, 116 are turned on. The desired amount of reverse current to achieve ZVS depends, for example, on the load, inductors 114, 120, and the like. In some examples, ZVS can be achieved without tuning (and/or retuning) the inductors 114, 120 when the load coupled to the power supply 100 changes. Thus, the efficiency of power converter 102 can be optimized during different load conditions (eg, during light load conditions) without tuning (and/or retuning) inductors 114, 120. FIG.

As described above, the multi-level DC-DC step-down power converter 102 is CCM controlled. Current therefore flows continuously through inductors 114 , 120 . CCM operation of power converter 102 can be maintained over the entire load range, including down to zero load conditions. In such examples, the control bandwidth during light load conditions may be increased compared to other power converters controlled in discontinuous conduction mode (DCM). This can lead to longer response times for the control circuit 108 compared to other power converters.

In some examples, it may be desirable to alter, limit, etc. the amount of reverse current flowing through the step-down circuits 104,106. For example, a specified amount of reverse current may be required to achieve ZVS of the power switches 110,116. However, an excessive amount of reverse current can be detrimental to the step-down circuits 104, 106 (eg, reduced efficiency, etc.). Accordingly, control circuit 108 can adjust the switching frequency to obtain the desired amount of reverse current. In some examples, control circuit 108 may decrease or increase the switching frequency of one or both control signals 122, 124 to increase, decrease, or maintain reverse current in step-down circuits 104, 106. can. For example, decreasing the switching frequency can increase inductor ripple current (discussed further below). Increased ripple current can result in increased reverse current.

The switching frequency of control signals 122, 124 may be adjusted based on various parameters. For example, the switching frequency can be adjusted based on the amount of reverse current flowing through the step-down circuits 104,106. In such an example, control circuit 108 monitors the reverse current flowing through buck circuits 104 , 106 (eg, as sensed by a current sensor) and switches control signal 122 based on the value of the reverse current flowing through buck circuit 104 . The frequency may be adjusted and/or the switching frequency of control signal 124 may be adjusted based on the value of the reverse current through step-down circuit 106 .

In some examples, the switching frequency of one or both control signals 122, 124 may be adjusted in steps based on the value of the reverse current. In such an example, if the load changes, the switching frequency can change in steps. For example, different switching frequencies can correspond to different load bands. For example, switching frequency F1 may correspond to a 0-10% load band, switching frequency F2 may correspond to a 10%-20% load band, and switching frequency F3 may correspond to a 20%-30% load band. The switching frequency F4 can correspond to a load band of 30% to 40%. In some examples, switching frequency F1 may have a maximum value compared to other frequency values, switching frequency F4 may have a minimum value compared to other frequency values, and switching frequency F1 may have a minimum value compared to other frequency values. F2 can be greater than the switching frequency F3. In such an example, the reverse current flowing through buck circuit 104 and/or buck circuit 106 may be a certain amount (eg, 2.5 A) before control circuit 108 changes frequency (eg, F1-F2). etc.) (eg due to increased load). As the frequency is changed, the amount of reverse current can decrease to lower levels.

In other examples, the switching frequency may be adjusted based on load. For example, power supply 100 of FIG. 1 provides load current for powering a load (not shown) connected to power supply 100 . In such examples, control circuit 108 may adjust the switching frequency of one or both control signals 122, 124 when the load current is within a specified range. Operating in this mode, the power switches 110, 116 are able to achieve ZVS over the specified range without excessive reverse current due to changing the switching frequency. As a result of the limited reverse current, net efficiency can be maintained and/or increased over the specified load range. Control circuit 108 can adjust the switching frequency as needed to obtain the desired amount of reverse current to achieve ZVS. For example, the switching frequency may be one value when the load current is near the lower end of the specified range, and the switching frequency may be a lower value when the load current is near the upper end of the specified range. can be done.

The specified range may depend, for example, on the full load peak current of power supply 100 . In such an example, the specified ranges are 0-40% of full load peak current, 10%-40% of full load peak current, 15%-35% of full load peak current, 5%-5% of full load peak current. 45% and/or another suitable range can be included. In other examples, the prescribed range may be based on another parameter as desired.

In some preferred embodiments, control circuit 108 adjusts the switching frequency of one or both control signals 122, 124 only when the load current is within a specified range. The control signals 122, 124 may have a fixed switching frequency when the load current is out of the specified range. For example, when the load current of power supply 100 is above a specified range (eg, above 30%, 35%, 40%, 45%, etc.), control signals 122, 124 can have a fixed switching frequency. During this time, power converter 102 may be in a heavy load operating state and controlled in CCM (eg, CCM fixed frequency mode). In some examples, there may be little or no reverse current in the power converter 102, especially as the load increases.

If the load current of the power supply 100 is below a specified range (eg, less than 5%, 10%, 15%, 20%, etc.), the control signals 122, 124 can have another (different) fixed switching frequency. During this time, power converter 102 may be in a light load operating state and controlled in its CCM (eg, CCM fixed frequency mode). In such an example, the reverse current flowing through the buck circuits 104, 106 can exceed the level required for ZVS.

The fixed switching frequency for load currents below the specified range may be the same as or different from the fixed switching frequency for load currents above the specified range. For example, the fixed switching frequency when the load current is below the specified range may be higher than the fixed switching frequency when the load current is above the specified range. This reduced frequency can reduce inductor ripple current and reverse current in the step-down circuits 104,106.

As shown in FIG. 1, a multi-level DC-DC step-down power converter 102 (and/or other multi-level step-down power converters disclosed herein) includes two step-down circuits 104, 106 (eg, power conversion level) only. In other embodiments, the multi-level DC-DC step-down power converter 102 (and/or any of the other multi-level step-down power converters disclosed herein) includes three or more step-down circuits (e.g. , power conversion level).

FIG. 2 shows an example of a multi-level step-down power converter that may be used in power supply 100 of FIG. Specifically, FIG. 2 shows a multi-level DC-DC step-down power converter 202 including step-down circuits 204,206. Buck circuit 204 includes a power switch Q1, a synchronous rectifier switch Q3, and an inductor L1 coupled between power switch Q1 and synchronous rectifier switch Q3 to form a buck converter topology. Buck circuit 206 includes a power switch Q2, a synchronous rectifier switch Q4, and an inductor L2 coupled between power switch Q2 and synchronous rectifier switch Q4 to form a buck converter topology. Switches Q1-Q4 are shown as MOSFETs in FIG. 2, but any other suitable switching device may be used if desired.

As shown in FIG. 2, buck circuit 204 is coupled between the positive bulk input voltage and a reference voltage (eg, ground), and buck circuit 206 is coupled between the negative bulk input voltage and the reference voltage. . Specifically, power switch Q1 is coupled to a positive bulk input voltage (eg, the positive side of input source V1) and power switch Q2 is coupled to a negative bulk input voltage (eg, the negative side of input source V1). , the synchronous rectifier switches Q3, Q4 are coupled to a reference voltage (eg, ground). As shown in FIG. 2, power converter 202 includes an output capacitor Co coupled between inductors L1 and L2.

In the exemplary embodiment of FIG. 2, power converter 202 includes an input capacitor coupled across step-down circuits 204,206. Specifically, power converter 202 includes a capacitor C1 coupled between a positive bulk input voltage and a reference voltage, and a capacitor C2 coupled between a negative bulk input voltage and the reference voltage. . Capacitor C1 is coupled between the converter input and buck circuit 204 (eg, switches Q1, Q3), and capacitor C2 is coupled between the converter input and buck circuit 206 (eg, switches Q2, Q4). connected to This arrangement ensures that the voltage across capacitors C1, C2 (and thus across switches Q1-Q4) is maintained at half the input voltage provided by input source V1. For example, input source V1 may provide a high input DC voltage, such as 800V, to power converter 202 . In this example, the voltage across each capacitor C1, C2 is maintained at 400V. Therefore, the maximum voltage stress (Vds) applied across the switches Q1-Q4 is approximately 400V. In some examples, a Vienna AC-DC rectifier is used to provide voltage across capacitors C1 and C2.

The switches Q1-Q4 receive control signals generated by a control circuit (not shown). Specifically, power switch Q1 receives PWM control signal AA, synchronous rectifier switch Q3 receives PWM control signal AA_SR, power switch Q2 receives PWM control signal BB, and synchronous rectifier switch Q4 receives PWM control signal AA_SR. Receive signal BB_SR. FIG. 3 shows the PWM control signals AA, BB, AA_SR, BB_SR of the switches Q1-Q4. As shown in FIG. 3, control signals AA_SR, BB_SR are complementary to control signals AA, BB, respectively. Thus, if the duty cycle of control signals AA, BB for power switches Q1, Q2 is D, then the duty cycle of control signals AA_SR, BB_SR for synchronous rectifier switches Q3, Q4 is 1-D.

In some examples, the step-down circuits 204, 206 may operate to maintain a phase shift therebetween. For example, as shown in FIG. 3, the control signals AA, BB for the power switches Q1, Q2 are phase shifted 180 degrees with respect to each other. In other examples, the phase shift can be different depending on, for example, the number of step-down circuits used in power converter 202 .

Further, as shown in FIG. 3, during high/low transitions of control signals AA, AA_SR (eg, on/off transitions of switches Q1, Q3) and between high/low transitions of control signals BB, BB_SR (eg, ON/OFF transitions of switches Q1, Q3). , the on/off transitions of the switches Q2, Q4)). The dead time between switching states helps prevent shoot-through conditions and can play a role in achieving ZVS of the power switches Q1, Q2.

As explained above, reverse current can be used to achieve ZVS and optimize converter efficiency, especially during light load conditions. For example, the reverse current in the power converter 202 flows from the converter output through the inductors L1, L2 during the freewheeling period and the voltage (Vds) across the power switches Q1, Q2 to achieve ZVS. is used by the synchronous rectifier switches Q3, Q4 to discharge the . Specifically, when the load current falls below 50% of the peak-to-peak ripple current in inductors L1, L2, the current through inductors L1, L2 becomes negative (eg, ripple current minus load current). This causes reverse current to flow from the output of the converter (eg, output capacitor Co) through inductors L1, L2 and rectifier switches Q3, Q4. For example, during the freewheeling period of buck circuit 204, when the load current drops below 50% of the peak-to-peak ripple current in inductor L1, a reverse current (indicated by dashed arrow 208 in FIG. 2) flows from output capacitor Co to inductor L1 and It flows through the rectifier switch Q3.

Additionally, inductors L1, L2 of FIG. 2 (and/or any one of the other inductors disclosed herein) may be selected to help achieve ZVS. For example, the values of inductors L1, L2 may be selected for a desired peak-to-peak ripple current. Achieving the desired peak-to-peak ripple current can help create a reverse current condition and a desired amount of reverse current, as explained above. ZVS of power switches Q1, Q2 can be achieved when sufficient energy is stored in inductors L1, L2 during reverse current conditions. Therefore, the values of inductors L1, L2 are selected for the desired peak-to-peak ripple current to ensure that a sufficient amount of reverse current is generated at a particular load level to achieve ZVS. obtain.

As described herein, the amount of reverse current can be controlled by adjusting the switching frequency. For example, if the switching frequency is fixed and the duty cycle of the synchronous rectifier switches Q3, Q4 is 1-D, the amount of reverse current increases as the load decreases. Therefore, the energy stored in inductors L1, L2 may exceed the amount necessary to achieve ZVS. However, as the switching frequency is adjusted, the amount of reverse current changes due to the change in the peak-to-peak ripple currents in inductors L1 and L2. For example, increasing the switching frequency reduces the peak-to-peak ripple current. As a result, the reverse current is reduced.

For example, FIGS. 4 and 5 show voltage and current waveforms associated with step-down circuit 204. FIG. Specifically, as shown in FIGS. 4 and 5, waveforms 402, 502 represent the turn-on voltage (Vgs) of power switch Q1, waveforms 404, 504 represent the voltage (Vds) across power switch Q1, Waveforms 406 and 506 represent the current in inductor L1 for a load current of 4.5 amps. The switching frequency in the example of FIG. 4 is 35 kHz and the switching frequency in the example of FIG. 5 is 30 kHz. As shown in FIG. 4, the voltage (Vds) across the power switch Q1 is not discharged before the voltage (Vgs) rises to turn on the power switch Q1. Therefore, in the example of FIG. 4, ZVS is not achieved at power switch Q1. However, decreasing the switching frequency from 35 kHz to 30 kHz increases the amount of reverse current as shown in waveforms 406 and 506 . This increased reverse current discharges the voltage (Vds) across the power switch Q1 before the voltage (Vgs) increases to turn on the power switch Q1, as shown in waveforms 502, 504 of FIG. .

Referring back to FIGS. 2 and 3, the on-times of the control signals AA, BB of the power switches Q1, Q2 may or may not overlap. For example, if the duty cycle of the control signals AA, BB exceeds the duty cycle threshold, the on-times of the control signals AA, BB for the power switches Q1, Q2 may overlap. If the duty cycle of the control signals AA, BB is below the duty cycle threshold, the on-times of the control signals AA, BB for the power switches Q1, Q2 may not overlap. In some examples, the duty cycle threshold may be fifty percent (50%) or another suitable value.

For example, FIG. 6 shows PWM control signals AA, BB, AA_SR, BB_SR of switches Q1-Q4 of FIG. 7-9 illustrate current flow in power converter 202 of FIG. 2 depending on the state of control signals AA, BB, AA_SR, BB_SR. For example, during the sub-interval t0-t1 shown in FIG. 6, control signals AA, BB_SR are high and control signals BB, AA_SR are low. Thus, switches Q1, Q4 are on and current (indicated by arrow 700) flows through power switch Q1, inductors L1, L2, and synchronous rectifier switch Q4, as shown in FIG. In this scenario, both inductors L1, L2 are energized from capacitor C1 (eg, half the input voltage of the power converter) and power is delivered to the output of the power converter. During this time, the peak-to-peak ripple currents in inductors L1 and L2 can be calculated by equation (1) below.
formula (1)

In the above equation (1), Vo is the output voltage of the power converter 202, D is the duty cycle (Vo/Vin), L1 and L2 are the inductance values of the inductors L1 and L2, and Tsw is the time interval is the switching period of Here, "Vin/2" represents the voltage across the capacitor C1 (Vc1), and "D*Tsw" represents the ON time (Ton) of the control signal.

During the sub-intervals t2-t3 shown in FIG. 6, the control signals BB, AA_SR are high and the control signals AA, BB_SR are low. Thus, switches Q2, Q3 are on and current (indicated by arrow 900) flows through synchronous rectifier switch Q3, inductors L1, L2, and power switch Q2, as shown in FIG. In this scenario, both inductors L1, L2 are energized from capacitor C2 (eg, half the input voltage of the power converter) and power is delivered to the output of the power converter. Thus, the step-down circuits 204, 206 alternately draw power from the input capacitors C1, C2 to ensure balanced power dissipation from the input capacitors C1, C2. During sub-interval t2-t3, the peak-to-peak ripple current in inductors L1, L2 can be calculated using equation (1) above when the voltage across capacitor C2 is equal to the voltage across capacitor C1 .

式（３）

During the sub-intervals t1-t2, t3-t4 shown in FIG. 6, the control signals AA_SR, BB_SR are high and the control signals AA, BB are low. Thus, the synchronous rectifier switches Q3, Q4 are on and the power switches Q1, Q2 are off, thereby disconnecting the inductors L1, L2 and the output of the power converter from the input of the power converter. This causes inductors L1 and L2 to start freewheeling. During this time, current (indicated by arrow 800) flows in a loop through synchronous rectifier switches Q3, Q4 and inductors L1, L2 as shown in FIG. During these sub-intervals, the freewheeling period Tfw can be calculated using equation (2) below, and the peak-to-peak ripple current in inductors L1, L2 can be calculated using equation (3) below: can do.
formula (2)

Formula (3)

FIG. 10 shows various waveforms of voltage and current characteristics of the step-down circuit 204 of FIG. 2 when control signals AA and BB have non-overlapping on-times. Specifically, waveforms 1002, 1004, 1006, and 1008 of FIG. 10 represent, respectively, the voltage across inductor L1 during the time intervals t0-t1, t1-t2, t2-t3, t3-t4, the It represents the current through switch Q1, the current through synchronous rectifier switch Q3, and the current through inductor L1.

In one particular example, input source V1 provides a voltage of 800V to multi-level DC-DC step-down power converter 202 of FIG. 2, and inductors L1, L2 have an inductance of 25 μH. In addition, power switches Q1 and Q2 are switched at a switching frequency Fs of 50 kHz. In such an example, the switching period Tsw is 20 μsec (eg, 1/50 kHz) and the multi-level DC-DC step-down power converter 202 provides an output voltage Vo of 320V. In this example, the duty cycle D of the control signals AA, BB can be calculated by dividing the output voltage Vo by the input voltage Vin as explained above, and the on-time Ton of the control signals AA, BB is: It can be calculated by multiplying the duty cycle D and the switching period Tsw, and the freewheeling period Tfw can be calculated using equation (2) above. Thus, in this particular example, the duty cycle D is 0.4 (eg, 320V/800V), the on-time Ton of the control signals AA, BB is 8 μsec (eg, 0.4*20 μsec), and the freewheeling The ring period Tfw is 2 μsec. The peak-to-peak ripple current in inductors L1, L2 during the on-time of power switches Q1, Q2 (eg, during sub-intervals t0-t1, t2-t3) can be calculated using equation (1) above. and the peak-to-peak ripple current in inductors L1, L2 during the freewheeling period Tfw (eg, during sub-intervals t1-t2, t3-t4) can be calculated using equation (3) above: can be done. Thus, in this particular example, the peak-to-peak ripple current during the on-time of the power switches Q1, Q2 is 12.8 amps and the peak-to-peak ripple current during the freewheeling period Tfw is 12.8 amps.

The above peak-to-peak ripple current calculations can be verified by simulation. For example, FIG. 11 shows various simulated waveforms of the voltage and current characteristics of step-down circuit 204 of FIG. 2 when control signals AA, BB have non-overlapping on-times. Specifically, waveforms 1102, 1104, 1106 of FIG. 11 are respectively the peak-to-peak ripple current of inductor L1, the turn-on voltage of power switch Q1 (eg, control signal AA), and the multi-level DC-DC step-down power converter. 202 output voltage Vo. As shown, when the power switch Q1 operates at 50 kHz with a 40% duty cycle, the average output voltage is about 319.75 V and the peak-to-peak ripple current is about 12.7.

FIG. 12 shows PWM control signals AA, BB, AA_SR, BB_SR of the switches Q1-Q4 of FIG. 2, and the ON times of the control signals AA, BB overlap. 13-15 illustrate current flow in power converter 202 of FIG. 2 depending on the state of control signals AA, BB, AA_SR, BB_SR. For example, during the sub-intervals t0-t1, t2-t3 shown in FIG. 12, the control signals AA, BB are high and the control signals AA-SR, BB_SR are low. Thus, as shown in FIG. 13, power switches Q1, Q2 are on and current (indicated by arrows 1300) flows through power switches Q1, Q2 and inductors L1, L2. In this scenario, both inductors L1, L2 are energized from the total input bus voltage of power converter 202 (eg, the voltage provided by input source V1). During these sub-intervals, the peak-to-peak ripple current in inductors L1, L2 can be calculated with equation (4) below.
Formula (4)

In equation (4) above, Vin is the input voltage from power supply V1, Vc1, Vc2 are the voltages across capacitors C1, C2, Vo is the output voltage of power converter 202, and D is the duty cycle. (Vo/Vin) and Tsw is the switching period of this time interval.

式（６）

During the sub-intervals t1-t2 shown in FIG. 12, the control signals AA, BB_SR are high and the control signals BB, AA_SR are low. Thus, switches Q1, Q4 are on and current (indicated by arrow 1400) flows through power switch Q1, inductors L1, L2, and synchronous rectifier switch Q4, as shown in FIG. In this scenario, both inductors L 1 , L 2 are energized from capacitor C 1 (eg, half the input voltage of the power converter) and freewheel on the return path to step-down circuit 204 . During this sub-interval, the freewheeling period Tfw can be calculated using equation (5) below, and the peak-to-peak ripple current in inductors L1, L2 is calculated using equation (6) below: be able to.
Formula (5)

Formula (6)

During the sub-intervals t3-t4 shown in FIG. 12, the control signals AA_SR, BB are high and the control signals AA, BB_SR are low. Thus, switches Q2, Q3 are on and current (indicated by arrow 1500) flows through synchronous rectifier switch Q3, inductors L1, L2, and power switch Q2, as shown in FIG. During this time interval, both inductors L 1 , L 2 are energized from capacitor C 2 (eg, half the input voltage of the power converter) and freewheel back to step-down circuit 206 . During sub-interval t3-t4, the peak-to-peak ripple current in inductors L1, L2 can be calculated using equation (6) above when the voltage across capacitor C2 is equal to the voltage across capacitor C1 .

FIG. 16 shows various waveforms of voltage and current characteristics of the step-down circuit 204 of FIG. 2 when control signals AA and BB have overlapping on-times. Specifically, waveforms 1602, 1604, 1606, and 1608 of FIG. 16 represent, respectively, the voltage across inductor L1 during the time intervals t0-t1, t1-t2, t2-t3, t3-t4, power Represents the current through switch Q2, the current through synchronous rectifier switch Q4, and the current through inductor L1.

As mentioned above, the multi-level DC-DC step-down power converter 202 can receive an input voltage of 800V, and inductors L1, L2 can have an inductance of 25 μH. Additionally, the power switches Q1, Q2 can operate at a switching frequency Fs of 50 kHz, as described above. In such an example, the switching period Tsw is 20 μsec (eg, 1/50 kHz) and the multi-level DC-DC step-down power converter 202 provides an output voltage Vo of 500V. In this example, the duty cycle D of the control signals AA, BB can be calculated by dividing the output voltage Vo by the input voltage Vin as explained above, and the on-time Ton of the control signals AA, BB is: It can be calculated based on the duty cycle D and the switching period Tsw, and the freewheeling period Tfw can be calculated using equation (5) above. Thus, in this particular example, the duty cycle D is 0.625 (eg, 500V/800V) and the on-time Ton of the control signals AA, BB is 2.5 μsec (eg, (D-0.5)*Tsw =(0.625-0.5)*20 μsec) and the freewheeling period Tfw is 7.5 μsec. The peak-to-peak ripple current in inductors L1, L2 during the on-time of power switches Q1, Q2 (eg, during subintervals t0-t1, t2-t3) can be calculated using equation (4) above. and the peak-to-peak ripple current in inductors L1, L2 during the freewheeling period Tfw (eg, during sub-intervals t1-t2, t3-t4) can be calculated using equation (6) above: can be done. Thus, in this particular example, the peak-to-peak ripple current during the on-time of the power switches Q1, Q2 is 15 amps and the peak-to-peak ripple current during the freewheeling period Tfw is 15 amps.

The above peak-to-peak ripple current calculations can be verified by simulation. For example, FIG. 17 shows various simulated waveforms of the voltage and current characteristics of step-down circuit 204 of FIG. 2 when control signals AA, BB have overlapping on-times. Specifically, waveforms 1702, 1704, and 1706 of FIG. 17 show the turn-on voltage of power switch Q1 (eg, control signal AA), the peak-to-peak ripple current, and the output of multilevel DC-DC step-down power converter 202, respectively. represents the voltage Vo. As shown, when the power switch Q1 operates at a frequency of 50 kHz and a duty cycle of 62.66%, the average output voltage is approximately 500 V and the peak-to-peak ripple current is approximately 15.3.

In the examples of Figures 10, 11, 16 and 17, the frequency of the inductor ripple current is approximately twice the switching frequency (Fs) of the power switches Q1, Q2. Therefore, in these particular examples, the frequency of the inductor ripple current is approximately 100 kHz. In such an example, the size (eg, inductance) of inductors L1, L2 may be reduced (eg, by 50%) compared to conventional interleaved step-down power converters.

In some examples, the switches in multi-level DC-DC step-down power converter 202 of FIG. 2 may experience reverse recovery losses and/or switching losses. For example, when the power converter 202 operates in CCM, the synchronous rectifier switches Q3, Q4 may experience reverse recovery losses and the power switches Q1, Q2 may experience ON and/or OFF switching losses. . Specifically, the synchronous rectifier switches Q3, Q4 conduct current through their body diodes for a short period of time (e.g., during dead time) before the switches Q3, Q4 are turned off to avoid shoot-through current. do. Diode conduction can generate reverse recovery currents and cause reverse recovery losses. Reverse recovery and switching losses can be reduced (and possibly eliminated) when GaN type switching devices are used.

The power supplies disclosed herein can include multiple power converter stages. For example, the multi-level DC-DC step-down power converter disclosed herein may be one of the power converter stages. Other power converter stages may include, for example, resonant power converters.

For example, FIG. 18 shows a switched mode power supply 1800 including the multi-level step-down power converter 102 of FIG. show. In some examples, control circuit 1808 of FIG. 18 may function similarly to control circuit 108 of FIG. In such an example, the control circuit 1808 controls the power switch 102 to control the multi-level DC-DC step-down power converter 102 in the CCM such that reverse current flows through the step-down circuits 104, 106 (as described above). A control signal for 110, 116 may be generated and then the switching frequency of the control signal may be adjusted to control the amount of reverse current to achieve ZVS of the power switches 110, 116. FIG. In other examples, the control circuit 1808 of FIG. 18 may function in another suitable manner, with or without reverse current flow through the step-down circuits 104,106.

As shown in FIG. 18, resonant power converter 1802 is coupled to multi-level step-down power converter 102 . Specifically, in the particular example of FIG. 18, resonant power converter 1802 is coupled to the output of multi-level step-down power converter 102 . In other examples, resonant power converter 1802 may be coupled to the output of multi-level step-down power converter 102, eg, via intervening components, power converter stages, and the like.

In the example of FIG. 18, resonant power converter 1802 may be a fixed frequency converter. For example, although not shown in FIG. 18, control circuitry 1808 and/or another suitable control circuitry may provide control signals having a fixed switching frequency to one or more power switches in resonant power converter 1802. can be generated. In other examples, the power switches in resonant power converter 1802 can have varying switching frequencies, can be controlled with adjustable switching frequencies, or the like.

Resonant power converter 1802 may have any suitable resonant topology including, for example, an interleaved resonant bus converter topology, a non-interleaved resonant bus converter topology, and the like. For example, FIG. 19 shows a switched mode power supply 1900 including an interleaved resonant bus power converter 1902 coupled to the output of the multi-level DC-DC step-down power converter 202 of FIG. In the example of FIG. 19, power supply 1900 includes capacitor Co1 coupled between power converter 202 and resonant power converter 1902, resonant power converter 1902 and a load (eg, shown as resistor Rload). and an output capacitor Co2 coupled between.

Switches Q1-Q4 of power converter 202 shown in FIG. 19 may optionally be controlled in a manner similar to that described above. For example, as shown in FIG. 19, power supply 1900 includes control circuitry 1938 for controlling switches Q1-Q4. Specifically, control circuit 1938 is coupled between comparator 1940 , controller 1942 (eg, a PID controller, PI controller, etc.), PWM driver 1944 , and controller 1942 and PWM driver 1944 . and an isolation device 1946 (eg, an isolation transformer, optocoupler, etc.). Comparator 1940 generates an error signal based on the signal representing the output voltage of the power supply and reference signal Vref. In such an example, PWM driver 1944 generates PWM control signals AA, BB, AA_SR, BB_SR based on error signals for controlling switches Q1-Q4 as described above and/or in another suitable manner. can be generated.

As shown in Figure 19, the interleaved resonant bus power converter 1902 includes two sub-converters 1930, 1932 coupled in parallel. Sub-converter 1930 includes transformer TX1, power switches Q5, Q6 coupled to the primary winding of transformer TX1, and capacitors C3, C4 coupled between power switches Q5, Q6 and the output of power converter 202. , an inductor L3 coupled to the primary winding of transformer TX1, and a rectifier circuit 1934 having diodes D1, D2, D3, D4 coupled to the secondary winding of transformer TX1. Sub-converter 1932 comprises similar components to sub-converter 1930, but includes transformer TX2, power switches Q7, Q8, capacitors C5, C6, inductor L4, and diodes D5, D6, D7, D8. and a rectifier circuit 1936 . The power switches of each sub-converter 1930, 1932 are arranged in a half-bridge topology. In addition, the inductor, capacitor and transformer primary winding of each sub-converter 1930, 1932 form a resonant tank circuit.

In the particular example of FIG. 19, the diodes of rectifier circuits 1934, 1936 are arranged as a full bridge rectifier. In another example, the rectifier circuits 1934, 1936 can include two diodes arranged as a half-bridge rectifier. In some examples, the rectifier circuits 1934, 1936 may include one or more other suitable switching devices such as synchronous rectifier switches instead of diodes.

FIG. 20 shows a switched mode power supply 2000 similar to the power supply 1900 of FIG. 19 but including a non-interleaved resonant bus power converter 2002 instead of the interleaved resonant bus power converter 1902. Power supply 2000 includes capacitors Co1, Co2, and control circuit 1938 of FIG. Specifically, as shown in FIG. 20, capacitor Co1 is coupled between power converter 202 and resonant power converter 2002, output capacitor Co2 is coupled between resonant power converter 2002 and the load, Control circuit 1938 generates PWM control signals AA, BB, AA_SR, BB_SR for controlling switches Q1-Q4 as described above.

Non-interleaved resonant bus power converter 2002 includes a substantially similar arrangement of components as sub-converter 1930 of FIG. For example, power converter 2002 includes transformer TX1, power switches Q5, Q6, capacitors C3, C4, and rectifier circuit 1934 of FIG. Capacitors C3, C4 and the primary winding of the transformer form a resonant tank circuit.

In some examples, the resonant power converters 1902, 2002 of FIGS. 19 and 20 provide isolation with fixed gain for the output of the power supply 1900, 2000 (eg, voltage across resistor Rload). For example, power switches of resonant power converters 1902, 2002 may be switched at a fixed switching frequency to achieve fixed gain. Further, in the examples of FIGS. 19 and 20, the control loop of control circuit 1938 is closed on multi-level DC-DC step-down power converter 202 . Thus, the output of the power supply can be regulated, regulated, etc. by controlling the PWM of the power converter 202 .

In some embodiments, the rectifier switches disclosed herein may be replaced with other suitable switching devices such as diodes. For example, FIG. 21 shows a multi-level DC-DC step-down power converter substantially similar to the multi-level DC-DC step-down power converter 202 of FIG. 2, but including diodes D1, D2 instead of synchronous rectifier switches Q3, Q4. Transducer 2102 is shown. In such an example, due to the diodes D1, D2, there may be no reverse current flow in the step-down circuit of the converter.

The control circuitry disclosed herein may include analog control circuitry, digital control circuitry, or hybrid control circuitry (eg, a digital control unit and analog circuitry). A digital control circuit may be implemented with one or more types of digital control circuits. For example, each of the digital control circuits may include a digital controller such as a digital signal controller (DSC), DSP, microcontroller unit (MCU), field programmable gate array (FPGA), application specific IC (ASIC). Accordingly, any one of the control methods disclosed herein may be at least partially (and sometimes fully) performed by a digital controller.

The multi-level DC-DC step-down power converters disclosed herein can be controlled in any suitable manner. For example, a multi-level DC-DC step-down power converter can be controlled using voltage mode control methods, current mode control methods, and the like.

Additionally, the multi-level DC-DC step-down power converter can have a substantially linear duty cycle during operation. For example, the output voltage to input voltage relationship (e.g., duty cycle) of a multi-level DC-DC step-down power converter can be divided into overlapping on-time modes, non-overlapping on-time modes, and continuous conduction with or without fixed frequency. It can remain substantially linear across different operating modes, such as mode. In such an example, the duty cycle may range linearly from about 10% at an output voltage of about 50VDC to 90% at an output voltage of about 700VDC.

The teachings disclosed herein may be applicable to any suitable SMPS. For example, the power supply disclosed herein includes an AC-DC PFC power converter that provides a high input voltage to one of the multi-level DC-DC step-down power converters disclosed herein. can be done. The PFC power converter may be a three-phase PFC power converter in a Wien configuration. In some examples, the power supplies disclosed herein include overcurrent protection and/or hyperscaling capabilities to provide appropriate outputs (e.g., trimmable outputs) in response to changes in system load demands. can be used in systems requiring

Various advantages may be achieved by using any one of the power sources disclosed herein. For example, inductors (eg, inductors L1, L2 of power converter 202) may be operable in an interleaved manner. As a result, the inductor size can be reduced and the control bandwidth increased compared to conventional power converters. Additionally, input capacitors (eg, capacitors C1, C2 in FIG. 2) in a multi-level DC-DC step-down power converter can have balanced voltages due to dedicated charge/discharge times of the capacitors. Furthermore, the power converter can operate over a wide output voltage range while maintaining half the input voltage voltage stress when an input capacitor is used.

The power converter may also experience improved control performance due to CCM operation that is maintained down to zero load. Thus, the light load control bandwidth can be increased compared to conventional converters with discontinuous conduction mode (DCM) operation.

In addition, multi-level DC-DC step-down power converters can operate over a wide duty cycle range, such as 10% to 90%. This can increase the holdup of other power converter stages coupled to the step-down power converter compared to conventional systems. For example, the power supply may include a resonant power converter capable of operating at a specified voltage (eg, 400V input) to achieve high efficiency such as over 99%. If the multi-level DC-DC step-down power converter receives a high input DC voltage (e.g., 800V bulk voltage), then the typical duty cycle under nominal conditions is about 50% for the step-down power conversion. ensure that the converter provides the desired voltage (eg, 400V input) to the resonant power converter. As the load demand changes and/or the input of the step-down power converter changes, the duty cycle can be adjusted to provide the desired voltage to the resonant power converter. This ensures that the power supply maintains the desired regulation.

Additionally, the resonant power converters disclosed herein can achieve ZVS and/or zero current switching (ZCS). For example, if the resonant power converter operates at a fixed switching frequency, the primary side switch can achieve ZVS and the secondary side switch can achieve ZVS and ZCS under all load conditions. Additionally, the gain curve of a resonant power converter can be flat such that the operation of the converter is fixed at a single resonant gain. As a result, the current sharing between rails is not sensitive to resonant component tolerances.

The foregoing descriptions of the embodiments have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, are interchangeable where applicable, and have been selected even if not specifically shown or described. Embodiments can be used. This may also be varied in many ways. Such variations are not to be considered a departure from the present disclosure, and all such modifications are intended to be included within the scope of this disclosure.

Claims (19)

A switched mode power supply for powering a load, comprising:
Multi-level step-down power conversion including an input, an output, a first step-down circuit coupled between the input and the output, and a second step-down circuit coupled between the input and the output a multi-level step-down power converter, wherein the first step-down circuit includes a power switch, a rectifier, and an inductor, and the second step-down circuit includes a power switch, a rectifier, and an inductor;
a resonant power converter coupled to the output of the multi-level step-down power converter;
A control circuit coupled to the first step-down circuit and the second step-down circuit, wherein a first control signal for the power switch of the first step-down circuit and the power switch of the second step-down circuit a control circuit configured to generate a second control signal for a power switch to control the multi-level step-down power converter;
with
The control circuit adjusts the switching frequencies of the first control signal and the second control signal to control the amount of reverse current flowing through the first step-down circuit and the second step-down circuit, configured to achieve zero voltage switching of the power switch of the first buck circuit and the power switch of the second buck circuit while the multi-level buck power converter is in its continuous conduction mode; , a switch-mode power supply. 2. The switched mode power supply of claim 1, wherein said resonant power converter comprises an interleaved resonant power converter. 2. The switched mode power supply of claim 1, wherein said resonant power converter operates at a fixed switching frequency. The first control signal and the second control signal have overlapping on-times when duty cycles of the first control signal and the second control signal exceed a duty cycle threshold; 2. The switched mode power supply of claim 1, wherein on-times do not overlap when the duty cycles of the signal and the second control signal are below the duty cycle threshold. 5. The switched mode power supply of claim 4, wherein said duty cycle threshold is 50%. The multi-level step-down power converter comprises a first capacitor coupled between the input and the first step-down circuit and a second capacitor coupled between the input and the second step-down circuit. 2. The switch mode power supply of claim 1, comprising a capacitor. The control circuit monitors the reverse current flowing through the first step-down circuit and the second step-down circuit, and controls the output of the first control signal and the second control signal based on the value of the reverse current. 2. The switch mode power supply of claim 1 , configured to adjust the switching frequency in steps. The control circuit reduces the switching frequencies of the first control signal and the second control signal to increase the amount of reverse current flowing through the first step-down circuit and the second step-down circuit. 2. The switched mode power supply of claim 1 , wherein: 2. The control circuit of claim 1 , wherein the control circuit is configured to adjust the switching frequency of the first control signal and the second control signal when a load current of the switched mode power supply is within a specified range. Switch mode power supply as described. 10. The switch mode power supply of claim 9 , wherein said specified range comprises 10% to 40% of full load peak current of said switch mode power supply. The first control signal and the second control signal have a first fixed switching frequency when the load current of the switched mode power supply is above the specified range, and the load current of the switched mode power supply is higher than the specified range. 10. The switched mode power supply of claim 9 , having a second fixed switching frequency when is below said specified range. A switched mode power supply for powering a load, comprising:
A multi-level step-down power converter including a first step-down circuit and a second step-down circuit, the first step-down circuit including a power switch, a rectifier and an inductor, the second step-down circuit comprising , a power switch, a rectifier, and an inductor;
A control circuit coupled to the first step-down circuit and the second step-down circuit, wherein a first control signal for the power switch of the first step-down circuit and the power switch of the second step-down circuit Generating a second control signal for a power switch to control the multi-level buck power converter in a continuous conduction mode such that reverse current flows through the first buck circuit and the second buck circuit. controlling the amount of reverse current flowing through the circuit and flowing through the first step-down circuit and the second step-down circuit by adjusting the switching frequencies of the first control signal and the second control signal; configured to achieve zero voltage switching of the power switch of the first buck circuit and the power switch of the second buck circuit while the multi-level buck power converter is in its continuous conduction mode; , a control circuit, and
A switch mode power supply. The first control signal and the second control signal have overlapping on-times when duty cycles of the first control signal and the second control signal exceed a duty cycle threshold; 13. The switched mode power supply of claim 12 , wherein on-times do not overlap when the duty cycles of the signal and the second control signal are below the duty cycle threshold. 14. The switched mode power supply of claim 13 , wherein said duty cycle threshold is 50%. The control circuit monitors the reverse current flowing through the first step-down circuit and the second step-down circuit, and controls the output of the first control signal and the second control signal based on the value of the reverse current. 13. The switched mode power supply of claim 12 , configured to adjust the switching frequency in steps. The control circuit reduces the switching frequencies of the first control signal and the second control signal to increase the amount of reverse current flowing through the first step-down circuit and the second step-down circuit. 13. The switched mode power supply of claim 12 , wherein the switch mode power supply is configured as: 13. The control circuit of claim 12 , wherein the control circuit is configured to adjust the switching frequency of the first control signal and the second control signal when a load current of the switched mode power supply is within a specified range. Switch mode power supply as described. 18. The switch mode power supply of claim 17 , wherein said specified range comprises 10% to 40% of full load peak current of said switch mode power supply. The first control signal and the second control signal have a first fixed switching frequency when the load current of the switched mode power supply is above the specified range, and the load current of the switched mode power supply is higher than the specified range. 18. The switched mode power supply of claim 17 , having a second fixed switching frequency when is below said specified range.

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