JP7185405B2 - switch device - Google Patents

Description

The present invention relates to a switching device.

2. Description of the Related Art Conventionally, various switch devices for driving low-side switches, high-side switches, etc. have been developed (see, for example, Patent Document 1).

Here, the inventors of the present application have found that the conventional switch device has the problems described later by conducting the following tests.

FIG. 1 is a circuit diagram showing the configuration of a low-side switch IC 100 used for testing by the inventors of the present application. The low-side switch IC 100 has a configuration for testing added to the conventional structure. Specifically, in the low-side switch IC 100, the conventional structural parts are the low-side switch M1, the resistor R1, the output terminal OUT, the input terminal IN, and the ground terminal GND, and the components added for testing are the resistor Rt and the terminal GT.

The low-side switch M1 is composed of an n-channel MOSFET (MOS field effect transistor). The drain of the low-side switch M1 is connected to the output terminal (drain terminal) OUT. A source of the low-side switch M1 is connected to the ground terminal GND. A gate of the low-side switch M1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the input terminal IN.

The output terminal OUT is originally connected to the low potential side of the load. The application of Low (0 V) to the input terminal IN turns off the low-side switch M1, and the application of High to the input terminal IN turns on the low-side switch M1. That is, conduction/cutoff of the path between the output terminal OUT and the ground terminal GND is switched according to the voltage applied to the input terminal IN.

Also, as a configuration for testing, one end of the resistor Rt is connected to a connection node between one end of the resistor R1 and the gate of the low-side switch M1. The other end of the resistor Rt is connected to the test terminal GT.

As a test, the inventor connected the pulse source 200 to the output terminal OUT through the bipolar amplifier 150, applied the ground (0 V) to the input terminal IN, and applied a steep voltage rise to the output terminal OUT. The behavior of the gate voltage of the low-side switch M1 at this time was investigated using the gate test voltage Vgt generated at the test terminal GT. The situation in which the voltage rises at the output terminal OUT corresponds to the start-up of the power supply connected to the load when the IC is actually used.

First, a test was conducted without using an external resistor R connected between the test terminal GT and the ground as shown in FIG. The results are shown in FIG.

As shown in FIG. 2, when the voltage Vout applied to the output terminal OUT was rapidly raised from 0V to a predetermined voltage, the gate test voltage Vgt rose from 0V. In other words, the gate voltage of the low-side switch M1 rises even though the low voltage is applied to the input terminal IN, turning on the low-side switch M1. This is due to the gate-drain parasitic capacitance C1 included in the low-side switch M1.

JP-A-2001-345686

Therefore, the inventor of the present application connected an external resistor R between the test terminal GT and the ground as shown in FIG. 1 and conducted a test. The results are shown in FIG.

As shown in FIG. 3, when the voltage Vout applied to the output terminal OUT is abruptly raised from 0 V to a predetermined voltage, the gate test voltage Vgt rises even though the period is limited. Therefore, even in this case, there is a problem that the low-side switch M1 is turned on.

SUMMARY OF THE INVENTION In view of the above situation, an object of the present invention is to provide a switch device capable of suppressing malfunction of a switch when powering on a load.

The switch device of the present invention is
a switch;
a first terminal connected to the drain of the switch;
a second terminal connected to the source of the switch;
an input terminal connected to the gate of the switch;
a capacitor;
a first transistor;
has
one end of the capacitor is connected to the first terminal;
a gate of the first transistor is connected to the other end of the capacitor;
the drain of the first transistor is connected to the gate of the switch;
The source of the first transistor is configured to be connected to the second terminal (first configuration).

Moreover, the first configuration may further include a second transistor including the capacitor as a parasitic capacitance (second configuration).

In the second configuration, the switch may be configured by an n-channel MOSFET with a trench structure, and the second transistor may be configured by an n-channel MOSFET with a planar structure (third configuration).

Further, in any one of the first to third configurations,
further comprising a third transistor;
a gate of the third transistor is connected to the input terminal;
the drain of the third transistor is connected to the gate of the first transistor;
The source of the third transistor may be connected to the second terminal (fourth configuration).

Further, in the fourth configuration, further having a Zener diode,
the cathode of the Zener diode is connected to the drain of the third transistor;
The anode of the Zener diode may be connected to the source of the third transistor (fifth configuration).

In any one of the first to fifth configurations, the withstand voltage of the first transistor may be lower than the withstand voltage of the switch (sixth configuration).

Further, in the above first configuration,
a second transistor including the capacitor as a parasitic capacitance;
a third transistor;
a gate of the third transistor is connected to the input terminal;
the drain of the third transistor is connected to the gate of the first transistor;
the source of the third transistor is connected to the second terminal;
The withstand voltage of the third transistor may be lower than the withstand voltage of the second transistor (seventh configuration).

Further, an electronic device of the present invention includes a switch device having any one of the configurations described above, and a load connected to a first terminal of the switch device.

According to the switch device of the present invention, when the signal at the input terminal is Low and the power source of the load is turned on, the voltage at the first terminal rises sharply, but the gate of the first transistor goes High due to the capacitor. Low is applied to the gate of the switch by turning on the first transistor. Therefore, even if there is a parasitic capacitance between the gate and the drain of the switch, the gate of the switch is suppressed to Low, so it is possible to prevent the switch from being erroneously turned on even though the signal at the input terminal is Low. . In other words, it is possible to prevent the switch from malfunctioning when the power of the load is turned on.

3 is a circuit diagram showing the configuration of a low-side switch IC for testing; FIG. 4 is a timing chart showing an example of test results of a low-side switch IC for testing; 4 is a timing chart showing an example of test results of a low-side switch IC for testing; 1 is a circuit diagram showing a configuration example of a low-side switch IC according to one embodiment of the present invention; FIG. 4 is a timing chart showing the operation of the low-side switch IC according to one embodiment of the present invention; It is a figure which shows an example of the vertical structure of the low side switch M1. FIG. 4 is a diagram showing an example of a vertical structure of a transistor M2 provided to utilize parasitic capacitance; FIG. 4 is a diagram showing an example of a vertical structure of transistors M3 and M4; 1 is an external view showing one configuration example of a vehicle; FIG.

An embodiment of the present invention will be described below with reference to the drawings.

<1. Configuration of low-side switch IC>
FIG. 4 is a circuit diagram showing the configuration of the low-side switch IC1 according to one embodiment of the present invention. The low-side switch IC1 is a switching device that conducts/disconnects between the low potential side of the load 2 and the ground. The low-side switch IC1 can be used for vehicles, industrial equipment, and the like. For example, when the low-side switch IC1 is for vehicles, the low-side switch IC1 is a kind of IPD (intelligent power device) for vehicles.

The low-side switch IC1 includes a low-side switch M1, a transistor M2 (second transistor), a transistor M3 (first transistor), a transistor M4 (third transistor), resistors R1 and R2, and a Zener diode D1. is a semiconductor integrated circuit device configured by integrating The low-side switch IC1 also has an output terminal (first terminal) OUT, an input terminal IN, and a ground terminal (second terminal) GND in order to establish electrical connection with the outside.

The output terminal OUT is a terminal for connecting the low potential side of the load 2 to which the power supply voltage Vcc is applied. The load 2 can be, for example, a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor.

The input terminal IN is a terminal for receiving an external input signal. An external input signal is applied to the input terminal IN as each level of Low or High. The ground terminal GND is a terminal for applying ground.

The low-side switch M1 is composed of an n-channel MOSFET. The drain of the low-side switch M1 is connected to the output terminal (drain terminal) OUT. A source of the low-side switch M1 is connected to the ground terminal GND. A gate of the low-side switch M1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the input terminal IN.

The transistor M2 is composed of an n-channel MOSFET. A drain of the transistor M2 is connected to the output terminal OUT. The gate and source of transistor M2 are shorted. Thus, transistor M2 is always off. When the same gate-source voltage is applied to the transistor M2 and the transistor M1, the current flowing through the transistor M2 is, for example, 1/100 of that of the transistor M1.

The transistor M2 includes a parasitic capacitance C2 (an example of a capacitor) between its gate and drain. One end of the parasitic capacitance C2 is connected to the output terminal OUT.

The transistor M3 is composed of an n-channel MOSFET. A drain of the transistor M3 is connected to a connection node between the gate of the low-side switch M1 and one end of the resistor R1. The gate of transistor M3 is connected to a connection node short-circuiting the gate and source of transistor M2 and the other end of parasitic capacitance C2. A source of the transistor M3 is connected to the ground terminal GND.

The transistor M4 is composed of an n-channel MOSFET. The drain of transistor M4 is connected to the gate of transistor M3. A source of the transistor M4 is connected to the ground terminal GND. The gate of transistor M4 is connected to one end of resistor R2. The other end of the resistor R2 is connected to the input terminal IN. The breakdown voltage of the transistor M3 is lower than that of the transistor M1, and the breakdown voltage of the transistor M4 is lower than that of the transistor M2. This is because the transistors M3 and M4 may have a breakdown voltage corresponding to the breakdown voltage between the gate and source of the transistors M1 and M2.

The cathode of Zener diode D1 is connected to the drain of transistor M4. The anode of Zener diode D1 is connected to the source of transistor M4. Zener diode D1 clamps the drain-source voltage of transistor M4 to protect transistor M4.

<2. Operation of low-side switch IC>
In the low-side switch IC1 having such a configuration, when the power supply voltage Vcc sharply rises from 0 V while Low (0 V) is applied to the input terminal IN, the operation is as follows. At this time, the transistor M4 is turned off.

A voltage Vout applied to the output terminal OUT rises sharply from 0V. Then, the gate voltage of the transistor M3 rises and becomes High due to the parasitic capacitance C2 between the gate and the drain included in the transistor M2. As a result, the transistor M3 is turned on, and the gate voltage VG of the low-side switch M1 is grounded. That is, even if the low-side switch M1 includes a parasitic capacitance C1 between the gate and the drain, it is possible to prevent the gate voltage VG from rising, and to prevent the low-side switch M1 from being erroneously turned on. The above operation is shown in FIG. As shown in FIG. 5, the gate voltage VG is maintained at 0V even when the voltage Vout rises.

When the input terminal IN is switched to High after the power supply voltage Vcc rises as described above, the gate voltage of the transistor M4 rises and the transistor M4 is turned on. As a result, the gate voltage of the transistor M3 becomes Low and the transistor M3 is turned off. Therefore, the gate voltage VG of the low side switch M1 becomes High, and the low side switch M1 is turned on.

Here, instead of using the parasitic capacitance C2 included in the transistor M2, a single capacitance may be provided as a capacitor instead of the transistor M2. However, in that case, the capacitor is required to have a high withstand voltage, so the space for providing the capacitor becomes large. In this respect, it is better to use the parasitic capacitance C2 included in the high-voltage transistor M2 to reduce the layout space and provide the high-voltage capacitor.

<3. Vertical structure of MOSFET>
Next, the vertical structure of the low side switch M1 and the transistor M2 in the low side switch IC1 will be described.

FIG. 6 is a diagram showing an example of the vertical structure of the low-side switch M1 (n-channel MOSFET). As shown in FIG. 6, an n-type epitaxial layer 51 is formed on the silicon substrate to form the drain region. An n drift layer 52 is formed on the surface layer of the n− type epitaxial layer 51 . A p body layer 53 is formed on the surface layer of the n drift layer 52 .

The low-side switch M1 is configured by horizontally arranging units having a trench gate structure. Describing the unit of the trench gate structure, vertically extending gate electrode 54 vertically penetrates p body layer 53 , n drift layer 52 and n− type epitaxial layer 51 . A gate insulating film 55 is formed around the gate electrode 54 . An n + -type source region 56 is formed on the surface layer of the p body layer 53 on the side of the gate electrode 54 . A p + -type region 57 is formed on the surface layer of the p body layer 53 on the opposite side of the n + -type region 56 from the gate electrode 54 side. A source metal 58 is formed on the surface side of the n + -type region 56 and the p + -type region 57 . Vertically extending polysilicon portions 59 are formed at both lateral ends of the low-side switch M1.

FIG. 7 is a diagram showing an example of the vertical structure of the transistor M2 (n-channel MOSFET). The transistor M2 shown in FIG. 7 has a planar structure. As shown in FIG. 7, an n-type epitaxial layer 62 is formed on a silicon substrate 61 which will serve as a drain region. A high breakdown voltage p-well layer 63 is formed so as to be surrounded by the n− type epitaxial layer 62 . A low-breakdown-voltage p-well layer 64 is formed on the high-breakdown-voltage p-well layer 63 . An n+ region 65 is formed so as to be surrounded by the low breakdown voltage p-well layer 64 . A source metal 66 is connected to the n+ region 65 . A gate 67 is connected to the surface of the low-breakdown-voltage p-well layer 64 .

By constructing such a high withstand voltage transistor M2, a high withstand voltage gate-drain parasitic capacitance can be formed and used as a capacitor.

Also, FIG. 8 is a diagram showing an example of the vertical structure of the transistors M3 and M4 (n-channel MOSFETs). The transistors M3 and M4 shown in FIG. 8 are planar structures. As shown in FIG. 8, an n-type epitaxial layer 72 is formed on a silicon substrate 71 which will serve as a drain region. A high breakdown voltage p-well layer 73 is formed on the n− type epitaxial layer 72 . A low-breakdown-voltage p-well layer 74 is formed on the high-breakdown-voltage p-well layer 73 . An n+ region 75 is formed so as to be surrounded by the low breakdown voltage p-well layer 74 . A source metal 76 is connected to the n+ region 75 . A gate 77 is connected to the surface of the low-breakdown-voltage p-well layer 74 .

<4. Application to vehicles>
FIG. 9 is an external view showing one configuration example of the vehicle. A vehicle X of this configuration example is equipped with a battery (not shown in the drawing) and various electronic devices X11 to X18 that operate with power supplied from the battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamps] and DRL [daytime running lamps].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

Electronic device X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, and other electronic devices built into vehicle X at the factory shipment stage as standard equipment or manufacturer options. is.

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

The low-side switch IC1 and the load 2 described above can be incorporated in any of the electronic devices X11 to X18.

In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is indicated by the scope of claims rather than the description of the above-described embodiments. It should be understood that all changes that fall within the meaning and range of equivalence to the claims are included.

For example, in the above-described embodiment, the application target is a low-side switch, but the present invention is not limited to this and may be applied to a high-side switch. In this case, the high-side switch IC has a power supply terminal to which the power supply voltage is applied and an output terminal to which the high potential side of the load is connected, and the high-side switch is connected between the power supply terminal and the output terminal. be done.

INDUSTRIAL APPLICABILITY The present invention can be used for in-vehicle IPDs and the like.

1 Low side switch IC
2 Load M1 Low-side switch M2-M4 Transistor C1, C2 Parasitic capacitance D1 Zener diode R1, R2 Resistor OUT Output terminal IN Input terminal GND Ground terminal 100 Low-side switch IC
150 Bipolar amplifier 200 Pulse source Rt Resistance GT Test terminal R External resistance X Vehicle X11 to X18 Electronic equipment

Claims (6)

a switch;
a first terminal connected to the drain of the switch;
a second terminal connected to the source of the switch;
an input terminal connected to the gate of the switch;
a capacitor;
a first transistor;
has
one end of the capacitor is connected to the first terminal;
a gate of the first transistor is connected to the other end of the capacitor;
the drain of the first transistor is connected to the gate of the switch;
the source of the first transistor is connected to the second terminal ;
further comprising a third transistor;
a gate of the third transistor is connected to the input terminal;
the drain of the third transistor is connected to the gate of the first transistor;
the source of the third transistor is connected to the second terminal;
further comprising a Zener diode;
the cathode of the Zener diode is connected to the drain of the third transistor;
the anode of the Zener diode is connected to the source of the third transistor;
The switch device, wherein the Zener diode can protect the third transistor by clamping the drain-source voltage of the third transistor. 2. The switch device according to claim 1, further comprising a second transistor including said capacitor as a parasitic capacitance. 3. The switch device according to claim 2, wherein said switch comprises an n-channel MOSFET having a trench structure, and said second transistor comprises an n-channel MOSFET having a planar structure. 4. The switch device according to claim 1, wherein a withstand voltage of said first transistor is lower than a withstand voltage of said switch. further comprising a second transistor including the capacitor as a parasitic capacitance;
2. The switch device according to claim 1, wherein the withstand voltage of said third transistor is lower than the withstand voltage of said second transistor. A switch device according to any one of claims 1 to 5 ;
a load connected to the first terminal of the switch device;
An electronic device having

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