JP7151034B2 - Control circuit and DC/DC converter device - Google Patents

Description

The present invention relates to a control circuit that outputs a drive signal for driving a switching element to a device having a switching element to control the device, and a DC/DC converter device having the control circuit.

Hysteresis control is known as a feedback control method in a DC/DC converter device. For example, Patent Literature 1 discloses a control circuit that performs feedback control of a power converter by hysteresis control.

FIG. 8A is a circuit diagram showing an outline of an example of a DC/DC converter device that includes a half-bridge inverter circuit and performs hysteresis control. The DC/DC converter device A100 converts the DC voltage input from the DC power supply B into a desired DC voltage and supplies it to the load C. The DC/DC converter device A100 has a half bridge circuit having two switching elements 11 and 12, and includes an inverter circuit 1 that converts direct current to alternating current, a rectifying/smoothing circuit 3 that converts alternating current to direct current, and an inverter circuit 1. A transformer 2 for insulating the rectifying/smoothing circuit 3 and a control circuit 400 for generating drive signals for driving the switching elements 11 and 12 of the inverter circuit 1 are provided.

The control circuit 400 has a comparator 410 and a drive signal generator 460 . The comparator 410 compares the output voltage signal detected by the voltage sensor with a target voltage, switches between a high level signal and a low level signal, and outputs the signal according to the comparison result. FIG. 8B is a diagram showing the input signal and output signal of the comparator 410. As shown in FIG. The upper part of FIG. 8B shows the output voltage signal V detected by the voltage sensor and the target voltage _Vref . The comparator 410 has hysteresis, and the upper part of FIG. 8B shows the hysteresis range of the target voltage _Vref from voltage _VH to voltage _VL . The middle part of FIG. 8B shows the status signal output from the comparator 410 . Comparator 410 outputs a high level signal when output voltage signal V becomes less than voltage V _L and continues to output a high level signal until output voltage signal V exceeds voltage V _H . Also, when the output voltage signal V exceeds the voltage _VH , a low level signal is output, and the low level signal is continued until the output voltage signal V becomes less than the voltage _VL .

Drive signal generator 460 generates a drive signal for driving switching elements 11 and 12 based on the state signal output from comparator 410 . The lower part of FIG. 8B shows the first drive signal and the second drive signal output from the drive signal generator 460 . The first drive signal is a drive signal for driving the switching element 11. When the state signal is at a low level, the first drive signal is a low level signal. The signal is generated alternately with the The second drive signal is a drive signal for driving the switching element 12. When the state signal is at a low level, the second drive signal is a low level signal. The signal is generated alternately with the Further, the driving pulse signal of the first driving signal is delayed by half the period of the driving pulse signal. When the output voltage signal V becomes less than the voltage V _L , the inverter circuit 1 is driven, so the output voltage rises. When the output voltage signal V exceeds the voltage V _H , the inverter circuit 1 stops and the output voltage drops. . As a result, the output voltage is controlled to the target voltage _Vref .

JP 2016-152642 A

As shown in FIG. 8B, the high level period of the state signal is not constant. Therefore, the number of drive pulse signals may differ between the first drive signal and the second drive signal. For example, in the high level period on the left side of the state signal shown in FIG. ing. If the number of drive pulse signals differs between the first drive signal and the second drive signal, the length of the period during which each switching element is ON becomes unbalanced. In the example of FIG. 8, the time during which the switching element 11 is ON is longer than the time during which the switching element 12 is ON. If an imbalance occurs during the ON time, the transformer 2 may be saturated due to biased magnetism.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a control circuit in which the length of the period during which each switching element is ON is not unbalanced.

A control circuit provided by a first aspect of the present invention is a control circuit for controlling a device having a plurality of switching elements by outputting a drive signal for driving each switching element. a first detection means for detecting electrical information relating to output; and a state in which the value of the electrical information detected by the first detection means continues to be equal to or greater than a predetermined lower threshold after exceeding a predetermined upper threshold. During the interval, a first state signal indicating that the value of the electrical information is in the first state is output, and the value of the electrical information changes from the state of being less than the lower limit threshold to the state of being equal to or less than the upper threshold. is continued, state determining means for outputting a second state signal indicating that the value of the electrical information is in the second state; clock generating means for generating a clock pulse signal at a predetermined cycle; The first state signal and switching timing adjusting means for adjusting the signal level of the second state signal and outputting the signal, and when the signal output from the switching timing adjusting means is the first state signal, the switching elements are not driven. and drive signal generation means for generating a drive signal for each of the switching elements in order to drive each of the switching elements when the signal output from the switching timing adjustment means is the second state signal. and when the signal output from the switching timing adjustment means is the second state signal, the number of drive pulse signals constituting the drive signal for each switching element generated by the drive signal generation means is , the same number within one cycle defined by the clock pulse signal, and the pulse widths of the driving pulse signals are all the same.

According to this configuration, the first state signal and the first state signal are synchronized with the timing of the clock pulse signal so that the switching timing from the first state signal to the second state signal and the switching timing from the second state signal to the first state signal are synchronized with the timing of the clock pulse signal. Since the signal level of the two-state signal is adjusted, the adjusted first-state signal and second-state signal are signals having a period that is a natural number multiple of one cycle of the clock pulse signal. Further, when the signal output from the switching timing adjusting means is the second state signal, the number of driving pulse signals forming the driving signal for each switching element generated by the driving signal generating means is defined by the clock pulse signal. It is the same number within one cycle. Further, the pulse width of the driving pulse signal of each driving signal is the same. Therefore, there is no imbalance in the length of the period during which each switching element is ON.

In a preferred embodiment of the present invention, second detecting means for detecting other electrical information relating to the output of said device, and based on the electrical information detected by said second detecting means, if an abnormality has occurred in said device. and an abnormality determination means for determining whether or not there is an abnormality, wherein the state determination means outputs the first state signal and the second state signal when the abnormality determination means determines that no abnormality has occurred. When the abnormality determination means determines that an abnormality has occurred, the first state signal is output.

In this configuration, for example, a current sensor that detects the output current signal of the device is used as the second detection means, and it is determined whether or not an overcurrent has occurred based on the output current value detected by this current sensor. be able to. When the abnormality determination means determines that an abnormality has occurred, the state determination means outputs only the first state signal. Therefore, the drive signal generator does not generate a drive signal for driving each switching element. Therefore, the device can be stopped when it is determined that an abnormality has occurred.

In a preferred embodiment of the present invention, the upper threshold is a value larger than the lower threshold. According to this configuration, the state determination means can make a determination with a hysteresis characteristic.

In a preferred embodiment of the present invention, the upper threshold and the lower threshold are the same value. This configuration facilitates threshold setting.

A DC/DC converter device provided by the second aspect of the present invention includes a control circuit provided by the first aspect of the present invention, an inverter circuit, a rectifier circuit, and a circuit comprising the inverter circuit and the rectifier circuit. and a transformer disposed therebetween. According to this configuration, there is no imbalance in the length of the period during which each switching element is ON. Therefore, it is possible to prevent the transformer from being saturated due to biased magnetism.

According to the present invention, the timing of switching from the first state signal to the second state signal and the timing of switching from the second state signal to the first state signal are synchronized with the timing of the clock pulse signal. Since the signal level of the two-state signal is adjusted, the adjusted first-state signal and second-state signal are signals having a period that is a natural number multiple of one cycle of the clock pulse signal. Further, when the signal output from the switching timing adjustment means is the second state signal, the number of drive pulse signals forming the drive signal for each switching element generated in the drive signal generator is defined by the clock pulse signal. It is the same number within one cycle. Further, the pulse width of the driving pulse signal of each driving signal is the same. Therefore, there is no imbalance in the length of the period during which each switching element is ON.

1 is a circuit diagram showing an outline of a DC/DC converter device according to a first embodiment; FIG. 4 is a time chart showing waveforms of signals in each part of the control circuit according to the first embodiment; 5 is a time chart showing waveforms of signals in each part of the modification of the control circuit according to the first embodiment; It is a circuit diagram which shows the outline of the DC/DC converter apparatus which concerns on 2nd Embodiment. 9 is a time chart showing waveforms of signals in each part of the control circuit according to the second embodiment; FIG. 11 is a circuit diagram showing an outline of an interleaved multiphase converter device according to a third embodiment; 9 is a time chart showing waveforms of signals in each part of the control circuit according to the third embodiment; BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating an example of the conventional DC/DC converter apparatus, (a) is a circuit diagram which shows an outline, (b) is a time chart which shows the waveform of the signal of each part of a control circuit.

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will now be specifically described with reference to the accompanying drawings, taking as an example a case where a control circuit according to the present invention is used in a DC/DC converter device.

1 and 2 are diagrams for explaining the DC/DC converter device according to the first embodiment. FIG. 1 is a circuit diagram showing an outline of a DC/DC converter device according to a first embodiment. FIG. 2 is a time chart showing waveforms of signals in each part of the control circuit according to the first embodiment.

As shown in FIG. 1, the DC/DC converter device A1 includes an inverter circuit 1, a transformer 2, a rectifying/smoothing circuit 3, and a control circuit 4. The DC/DC converter device A1 converts the direct current input from the direct current power supply B into alternating current with the inverter circuit 1, inputs it to the primary side terminal of the transformer 2, and rectifies the alternating current output from the secondary side terminal of the transformer 2. The smoothing circuit 3 converts it into a direct current and supplies it to the load C. The control circuit 4 performs feedback control by detecting the voltage between the output terminals of the DC/DC converter device A1 and outputting a drive signal to the inverter circuit 1 so that the voltage becomes the target voltage. As a result, the DC/DC converter device A1 supplies the load C with the DC voltage controlled to the target voltage.

The inverter circuit 1 is a half-bridge type inverter, converts the direct current input from the direct current power supply B into alternating current, and outputs the alternating current to the transformer 2 . The inverter circuit 1 includes a half bridge circuit including two switching elements 11 and 12 and a resonance circuit 15 . The half bridge circuit has two switching elements 11 and 12 . In this embodiment, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as the switching elements 11 and 12 . The switching elements 11 and 12 are not limited to MOSFETs, and may be bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), or the like. The switching element 11 and the switching element 12 are connected in series by connecting the source terminal of the switching element 11 and the drain terminal of the switching element 12 . The drain terminal of the switching element 11 is connected to the positive electrode side of the DC power source B, and the source terminal of the switching element 12 is connected to the negative electrode side of the DC power source B, forming a bridge structure. A flywheel diode is connected in antiparallel to each of the switching elements 11 and 12 . Drive signals are input from the control circuit 4 to the gate terminals of the switching elements 11 and 12 . A resonance circuit 15 is connected to a connection point between the switching element 11 and the switching element 12 . When the switching element 11 is in the ON state and the switching element 12 is in the OFF state, the potential at the connection point is the potential on the positive electrode side of the DC power supply B. On the other hand, when the switching element 11 is in the OFF state and the switching element 12 is in the ON state, the potential of the connection point becomes the negative potential of the DC power supply B. As a result, a pulse-like AC signal in which the potential on the positive electrode side and the potential on the negative electrode side of the DC power supply B are switched is output from the connection point. The resonance circuit 15 is a series resonance circuit in which an inductor and a capacitor are connected in series. Due to the resonance characteristics of the resonance circuit 15, the AC signal input from the half bridge circuit is output as a sine wave signal with a resonance frequency (clock frequency). Moreover, when both the switching element 11 and the switching element 12 continue to be in the OFF state, the inverter circuit 1 stops and stops outputting the sine wave signal. Note that the configuration of the inverter circuit 1 is not limited.

The transformer 2 is for insulating the inverter circuit 1 and the rectifying/smoothing circuit 3 . A primary winding of the transformer 2 is connected between the output terminal of the inverter circuit 1 and the negative electrode side of the DC power supply B. As shown in FIG. A secondary winding of the transformer 2 is connected between input terminals of the rectifying/smoothing circuit 3 . The transformer 2 inputs the signal output from the inverter circuit 1 to the rectifying/smoothing circuit 3 while the inverter circuit 1 and the rectifying/smoothing circuit 3 are insulated from each other.

The rectifying/smoothing circuit 3 converts alternating current input from the transformer 2 into direct current. The rectifying/smoothing circuit 3 includes a full-wave rectifying circuit in which four diodes are bridge-connected, and a smoothing circuit including an inductor and a capacitor. The rectifying/smoothing circuit 3 rectifies the alternating current input from the transformer 2 by a full-wave rectifying circuit, smoothes it by a smoothing circuit, and outputs it to a load C. The configuration of the rectifying/smoothing circuit 3 is not limited as long as it converts AC to DC. For example, other rectifier circuits such as a half-wave rectifier circuit may be used instead of the full-wave rectifier circuit. Also, the rectifying/smoothing circuit 3 may be a voltage doubler rectifying circuit or a Cockcroft-Walton circuit.

The control circuit 4 outputs a drive signal to the inverter circuit 1 to perform feedback control of the output voltage. As shown in FIG. 1, the control circuit 4 includes a comparator 41a, a comparator 41b, an AND circuit 42, a clock generator 43, a D flip-flop 44, a photocoupler 45, a drive signal generator 46, a voltage sensor 47, and a current sensor. 48 are provided.

A voltage sensor 47 detects the output voltage of the DC/DC converter device A1. The voltage sensor 47 has, for example, a voltage dividing circuit, divides the voltage between the output terminals of the DC/DC converter device A1, and outputs it as an output voltage signal V. FIG. The "voltage sensor 47" corresponds to an example of the "first detection means" of the present invention. Also, the output voltage of the DC/DC converter device A1 corresponds to an example of the "electrical information" of the present invention. A current sensor 48 detects the output current of the DC/DC converter device A1. The current sensor 48 outputs, as an output current signal I, a voltage corresponding to the detected output current. The "current sensor 48" corresponds to an example of the "second detection means" of the present invention. Also, the output current of the DC/DC converter device A1 corresponds to an example of "other electrical information" in the present invention.

The comparator 41a compares the output voltage signal V detected by the voltage sensor 47 with the target voltage _Vref . A voltage sensor 47 is connected to the inverting input terminal of the comparator 41a, and the output voltage signal V detected by the voltage sensor 47 is input. A reference power supply for voltage is connected to the non-inverting input terminal of the comparator 41a, and the target voltage _Vref is inputted. The comparator 41a switches between a high level signal and a low level signal according to the result of comparison between the output voltage signal V and the target voltage _Vref , and outputs it as a state signal. The comparator 41a has hysteresis, and the hysteresis range of the target voltage _Vref is set from the voltage _VH to the voltage _VL . The comparator 41a outputs a high level signal when the output voltage signal V becomes less than the voltage _VL which is lower than the target voltage _Vref . Then, while the output voltage signal V continues to be equal to or lower than the voltage _VH higher than the target voltage _Vref , the high level signal is maintained. When the output voltage signal V exceeds the voltage _VH , a low level signal is output, and the low level signal continues while the output voltage signal V continues to be at the voltage _VL or higher. An output terminal of the comparator 41 a is connected to one input terminal of the AND circuit 42 , and the comparator 41 a outputs a state signal to the AND circuit 42 . The "comparator 41a" corresponds to an example (including some cases) of the "state determination means" of the present invention.

FIG. 2(a) shows the waveforms of the output voltage signal V and the target voltage _Vref input to the comparator 41a. Also shown are a voltage _VH and a voltage _VL indicating the hysteresis range of the target voltage _Vref . FIG. 2(b) shows the waveform of the state signal output by the comparator 41a. The state signal switches to a high level signal (an example of the second state signal of the present invention) when V< _VL at time t1, and continues to be a high level signal until V> _VH at time t3. ing. In other words, the high level signal continues while the state of _V≤VH continues. Then, after V> _VH at time t3 and switching to a low level signal, the low level signal (an example of the first state signal of the present invention) continues until V< _VL at time t5. . That is, the low level signal continues while the state of V≧ _VL continues.

The comparator 41b detects overcurrent, and compares the output current signal I detected by the current sensor 48 with a threshold value _Iref for overcurrent detection. A current sensor 48 is connected to an inverting input terminal of the comparator 41b, and an output current signal I detected by the current sensor 48 is input. A current reference power supply is connected to the non-inverting input terminal of the comparator 41b, and a current threshold value _Iref is input. The comparator 41b switches between a high level signal and a low level signal according to the result of comparison between the output current signal I and the current threshold value _Iref , and outputs the signal as an overcurrent detection signal. The comparator 41b outputs a high level signal while the output current signal I is lower than the current threshold _Iref , and outputs a low level signal when the output current signal I is higher than the current threshold _Iref . That is, the comparator 41b normally outputs a high level signal as an overcurrent detection signal, and outputs a low level signal when an overcurrent is detected. The output terminal of the comparator 41 b is connected to the other input terminal of the AND circuit 42 , and the comparator 41 b outputs an overcurrent detection signal to the AND circuit 42 . The "comparator 41b" corresponds to an example (including some cases) of the "abnormality determination means" of the present invention.

The AND circuit 42 is a logic circuit, and outputs the AND of the state signal input from the comparator 41a and the overcurrent detection signal input from the comparator 41b. The output signal of the AND circuit 42 becomes a high level signal when both the state signal and the overcurrent detection signal are high level signals, and otherwise becomes a low level signal. The output terminal of the AND circuit 42 is connected to the D input terminal of the D flip-flop 44 , and the AND circuit 42 outputs an output signal to the D flip-flop 44 . The "AND circuit 42" corresponds to an example (including some cases) of the "state determination means" of the present invention.

The clock generator 43 generates a clock pulse signal. In this embodiment, the frequency of the clock pulse signal is 170 kHz, for example. Note that the frequency of the clock pulse signal is not limited. The output terminal of the clock generator 43 is connected to the clock input terminal of the D flip-flop 44 , and the clock generator 43 outputs the generated clock pulse signal to the D flip-flop 44 . The clock generator 43 also outputs the generated clock pulse signal to the drive signal generator 46 . FIG. 2(c) shows the waveform of the clock pulse signal output by the clock generator 43. As shown in FIG. The "clock generator 43" corresponds to an example of the "clock generator" of the present invention.

The D flip-flop 44 is a D-type flip-flop that reads the D input in synchronization with the clock and holds it until the next clock is input. Since the D input terminal of the D flip-flop 44 is connected to the output terminal of the AND circuit 42, the output signal of the AND circuit 42 is input to the D input. Since the clock input terminal of the D flip-flop 44 is connected to the output terminal of the clock generator 43, the clock pulse signal generated by the clock generator 43 is input to the clock input terminal. In this embodiment, reading is performed at the rising edge of the clock pulse signal. Therefore, the timing of switching the output signal of the AND circuit 42 from the high level signal to the low level signal and from the low level signal to the high level signal is delayed until the rising timing of the clock pulse signal. That is, the switching timing is synchronized with the timing of the clock pulse signal. A signal whose switching timing is delayed is output from the Q output of the D flip-flop 44 as an ON/OFF control signal. The ON/OFF control signal becomes a signal having a high level period that is a natural number times the period of the clock pulse signal. The Q output terminal of the D flip-flop 44 is connected to the input terminal of the photocoupler 45, and the ON/OFF control signal output from the Q output is input to the driving signal generator 46 via the photocoupler 45. . The "D flip-flop 44" corresponds to an example of the "switching timing adjusting means" of the present invention.

FIG. 2(d) shows the waveform of the ON/OFF control signal output by the D flip-flop 44. FIG. When no overcurrent is detected (overcurrent detection signal is at a high level), the state signal output from the comparator 41a (see FIG. 2(b)) is input to the D input terminal of the D flip-flop 44. be. A clock pulse signal (see FIG. 2(c)) output by the clock generator 43 is input to the clock input terminal of the D flip-flop 44 . As for the ON/OFF control signal, the timing of switching from the low level signal to the high level signal and the timing of switching from the high level signal to the low level signal in the state signal (see FIG. 2(b)) are: The signal is delayed until the rising timing of the clock pulse signal (see FIG. 2(c)). The state signal is switched to a high level signal at time t1 (t5), but the ON/OFF control signal is at a high level at time t2 (t6) which is the rise timing of the clock pulse signal after time t1 (t5). switched to a signal. Also, the state signal switches to a low level signal at time t3, but the ON/OFF control signal switches to a low level signal at time t4, which is the rise timing of the clock pulse signal after time t3. In the example shown in FIG. 2, the switching ON period (from time t2 to time t4) is four times the period of the clock pulse signal.

The photocoupler 45 transmits a signal while electrically insulating the D flip-flop 44 and the drive signal generator 46 . The photocoupler 45 includes a light-emitting element and a light-receiving element. The light-emitting element converts an input electrical signal into light, and the light-receiving element receives the light, converts the light back into an electrical signal, and outputs the electrical signal. The ON/OFF control signal output by the D flip-flop 44 is input to the drive signal generator 46 via the photocoupler 45 .

The drive signal generator 46 drives the switching elements 11 and 12 based on the ON/OFF control signal input from the D flip-flop 44 via the photocoupler 45 and the clock pulse signal input from the clock generator 43. Generate a drive signal for driving. The "driving signal generator 46" corresponds to an example of the "driving signal generating means" of the present invention.

FIG. 2(e) shows the waveform of the first drive signal generated by the drive signal generator 46. FIG. The drive signal generator 46 generates a low level signal during the low level period of the ON/OFF control signal, and generates a high level drive pulse signal and a low level signal at predetermined intervals during the high level period of the ON/OFF control signal. and are generated alternately as a first drive signal for driving the switching element 11 and output. Note that the high-level period of the ON/OFF control signal is a period during which each switching element performs switching, and therefore may be referred to as a "switching ON period". Also, since the low level period of the ON/OFF control signal is a period in which switching of each switching element is stopped, it may be described as a "switching OFF period".

The drive pulse signal of the first drive signal is, for example, a pulse signal generated with the same period as the period T of the clock pulse signal input from the clock generator 43 . In the following, the period of the drive pulse signal is T' (T'=T in this embodiment). The period T of the clock pulse signal is the time from the rise timing of the clock pulse signal to the rise timing of the next clock pulse signal. In the following description, one cycle is defined as the period from the rise timing of the clock pulse signal to the rise timing of the next clock pulse signal.

The driving pulse signal has a dead time for preventing the switching elements 11 and 12 from being turned ON at the same time, so the pulse width is less than 1/2 of one period T'. Since the dead time is very short compared to one period of the driving pulse signal, it does not appear in FIG. 2(e) (FIG. 2(f), FIGS. 5(e), (f), (g), and (h)). In this embodiment, dead time is provided before each drive pulse signal. Therefore, the driving pulse signal of the first driving signal rises at the timing when the dead time has passed from the start timing of the cycle defined by the clock pulse signal (the rising timing of the clock pulse signal). A dead time may be provided after each drive pulse signal. In this case, the drive pulse signal of the first drive signal rises at the start timing of the cycle defined by the clock pulse signal. Also, the position of the drive pulse signal within the period defined by the clock pulse signal is not limited.

FIG. 2( f ) shows the waveform of the second drive signal generated by the drive signal generator 46 . The drive signal generation unit 46 generates a low level signal during the switching OFF period, and generates a signal generated by alternately generating a high level drive pulse signal and a low level signal at a predetermined cycle during the switching ON period, to the switching element. 12 is generated and output as a second drive signal for driving . The drive pulse signal of the second drive signal is a pulse signal having the same period and pulse width as those of the drive pulse signal of the first drive signal and provided with a dead time. The drive pulse signal of the second drive signal is arranged within the low level period of the first drive signal during the switching ON period. In other words, the drive pulse signal of the first drive signal and the drive pulse signal of the second drive signal do not overlap. In the present embodiment, the drive signal generation unit 46 generates and outputs a signal obtained by delaying the drive pulse signal of the first drive signal by half the period of the clock pulse signal as the second drive signal. As a result, the same number of drive pulse signals of the first drive signal and the same number of drive pulse signals of the second drive signal are generated during the switching ON period. In the example shown in FIG. 2, four driving pulse signals are generated as the first driving signal and four driving pulse signals as the second driving signal.

A first drive signal shown in FIG. 2E is input to the switching element 11, and a second drive signal shown in FIG. During the period from time t2 to time t4, the switching element 11 and the switching element 12 are ON/OFF operated, so the inverter circuit 1 outputs an AC voltage. Therefore, a DC voltage is output from the rectifying/smoothing circuit 3, and the output voltage signal V increases (see FIG. 2(a)). On the other hand, during the period from time t4 to time t6, switching element 11 and switching element 12 stop the ON/OFF operation, so inverter circuit 1 does not output AC voltage. Therefore, no DC voltage is output from the rectifying/smoothing circuit 3, and the output voltage signal V drops (see FIG. 2(a)).

Next, the operation and effects of the DC/DC converter device A1 according to this embodiment will be described.

According to the present embodiment, when overcurrent is not detected (when the overcurrent detection signal is a high level signal), the control circuit 4 outputs the first drive signal and the second drive signal based on the state signal of the comparator 41a. A signal is generated and output to switching element 11 and switching element 12, respectively. When the output voltage signal V is low, the switching element 11 and the switching element 12 perform ON/OFF operation, so that the output voltage rises, and when the output voltage signal V is high, the switching element 11 and the switching element 12 stop the ON/OFF operation. Therefore, the output voltage drops. This controls the output voltage to approach the target voltage. The switching ON period is a natural number multiple of the cycle T of the clock pulse signal, and the cycle T' of the drive pulse signal of the first drive signal and the second drive signal is the same as the cycle T of the clock pulse signal. . Therefore, the switching ON period includes the drive pulse signals of the first drive signal and the second drive signal by a natural number multiple of the period T'. Also, the number of drive pulse signals of the first drive signal and the number of drive pulse signals of the second drive signal are the same number within one cycle defined by the clock pulse signal. Further, the pulse width of the driving pulse signal of each driving signal is the same. Therefore, there is no imbalance in the length of the period during which each switching element is ON. Therefore, it is possible to prevent the transformer 2 from being saturated due to biased magnetism.

Further, according to this embodiment, when an overcurrent is detected (when the overcurrent detection signal is a low level signal), the output signal of the AND circuit 42 is at a low level regardless of the state signal output from the comparator 41a. Therefore, the first drive signal and the second drive signal become low level signals, and the ON/OFF operations of the switching element 11 and the switching element 12 are stopped. Therefore, the output of the DC/DC converter device A1 can be stopped when overcurrent is detected. When the output voltage of the DC/DC converter device A1 becomes overvoltage, the output voltage signal V continues to be higher than the target voltage _Vref , so the state signal continues to be a low level signal. Therefore, in this case also, the output signal of the AND circuit 42 becomes a low level signal, and the first drive signal and the second drive signal become low level signals, so that the ON/OFF operation of the switching element 11 and the switching element 12 is Stop. That is, the comparator 41a also functions as an overvoltage detection circuit.

According to this embodiment, when the output voltage signal V is high, the switching element 11 and the switching element 12 stop the ON/OFF operation, so the number of times of switching can be reduced as compared with the case of PWM control. That is, in PWM control, the switching elements 11 and 12 repeat ON/OFF operations in the same period regardless of the load. The period during which the ON/OFF operation is stopped becomes longer. Therefore, switching loss can be reduced more than in the case of PWM control. Moreover, according to this embodiment, unlike the case of PWM control, there is no need for designing for preventing oscillation. Therefore, the design is easier than in the case of PWM control, and the time required for design can be shortened.

Note that in the present embodiment, the period T' of the driving pulse signals of the first driving signal and the second driving signal is the same period as the period T of the clock pulse signal, but it is not limited to this. The period T' of each driving pulse signal may be 1/2 or 1/3 times the period T of the clock pulse signal, and if the period T of the clock pulse signal is a natural number multiple of the period T' of the driving pulse signal. good. In other words, in terms of frequency, the frequency (1/T') of each drive pulse signal should be a natural number multiple of the frequency (1/T) of the clock pulse signal. When the frequency of the drive pulse signal is N times the frequency of the clock pulse signal (N is a natural number), N drive pulse signals of the first drive signal and the second drive signal are generated within one cycle defined by the clock pulse signal. will be included. Therefore, the drive pulse signal of the first drive signal and the drive pulse signal of the second drive signal are included in the same number in one switching ON period.

Further, in the present embodiment, a signal obtained by delaying the switching timing of the state signal to the rise timing of the clock pulse signal is used as the ON/OFF control signal, but the present invention is not limited to this. A signal obtained by delaying the switching timing of the state signal to the fall timing of the clock pulse signal may be used as the ON/OFF control signal. In this case, one period defined by the clock pulse signal is from the fall timing of the clock pulse signal to the fall timing of the next clock pulse signal.

Although the case where the comparator 41a has hysteresis has been described in the present embodiment, the present invention is not limited to this. The comparator 41a does not have to have hysteresis. FIG. 3 is a time chart showing waveforms of signals in each part of the control circuit 4 when the comparator 41a has no hysteresis. FIG. 3(a) shows the waveforms of the output voltage signal V and the target voltage _Vref input to the comparator 41a. 3(b) shows the waveform of the state signal, FIG. 3(c) shows the waveform of the clock pulse signal, FIG. 3(d) shows the waveform of the ON/OFF control signal, and FIG. FIG. 3(f) shows the waveform of the second drive signal. While the output voltage signal V is higher than the target voltage _Vref (see FIG. 3(a)), the state signal becomes a low level signal (see FIG. 3(b)), while the output voltage signal V is lower than the target voltage _Vref (See FIG. 3(a)), and the state signal becomes a high level signal (see FIG. 3(b)). In this case also, the D flip-flop 44 outputs an ON/OFF control signal in which the switching timing of the state signal is delayed to the rising timing of the clock pulse signal (see FIG. 3(d)). Based on this ON/OFF control signal, the drive signal generator 46 generates the first drive signal and the second drive signal. Also in this case, the drive pulse signal of the first drive signal and the drive pulse signal of the second drive signal are included in the same number in one switching ON period. Also, the number of drive pulse signals of the first drive signal and the number of drive pulse signals of the second drive signal are the same number within one cycle defined by the clock pulse signal. Further, the pulse width of the driving pulse signal of each driving signal is the same. Therefore, there is no imbalance in the length of the period during which each switching element is ON. Therefore, it is possible to prevent the transformer 2 from being saturated due to biased magnetism.

Although the case where the output voltage of the DC/DC converter device A1 is controlled to the target voltage has been described in the present embodiment, the present invention is not limited to this. The output current of the DC/DC converter device A1 may be controlled to the target current. In this case, in the control circuit 4 shown in FIG. 1, the comparator 41b is provided with hysteresis, the target current is set instead of the threshold _Iref , and the threshold for overvoltage detection is set instead of the target voltage _Vref of the comparator 41a. You can set it. In this case, the "current sensor 48" corresponds to an example of the "first detection means" of the present invention, and the "voltage sensor 47" corresponds to an example of the "second detection means" of the present invention. Also, the output current of the DC/DC converter device A1 corresponds to an example of "electrical information" in the present invention, and the output voltage corresponds to an example of "other electric information" in the present invention.

Also, the output power of the DC/DC converter device A1 may be controlled to the target power. In this case, the power sensor that detects the output power of the DC/DC converter device A1 or the output power is detected by multiplying the output voltage signal V detected by the voltage sensor 47 and the output current signal I detected by the current sensor 48. A multiplier is provided, a comparator is provided for comparing the detected output power signal and the target power, and its output is added to the input of the AND circuit 42. It may be made to function as a detection circuit. The power sensor that detects the output power, or the voltage sensor 47, the current sensor 48, and the multiplier correspond to an example of the "first detection means" of the present invention. Also, the comparator that compares with the target power corresponds to an example of the "state determination means" of the present invention. Also, the output power of the DC/DC converter device A1 corresponds to an example of the "electrical information" of the present invention.

4 and 5 are diagrams for explaining the DC/DC converter device according to the second embodiment. FIG. 4 is a circuit diagram showing an outline of the DC/DC converter device A2 according to the second embodiment. FIG. 5 is a time chart showing waveforms of signals in each part of the control circuit according to the second embodiment. In FIG. 4, elements that are the same as or similar to those of the DC/DC converter device A1 (see FIG. 1) according to the first embodiment are given the same reference numerals. 4, the internal configuration of the control circuit 4 is omitted.

As shown in FIG. 4, the DC/DC converter device A2 includes a full-bridge inverter circuit 1' in place of the half-bridge inverter circuit 1. It differs from the converter device A1. The inverter circuit 1 ′ is a full-bridge inverter obtained by adding a bridge structure of two switching elements 13 and 14 to the inverter circuit 1 .

In FIG. 5, (a) to (f) show the same signal waveforms as (a) to (f) in FIG. FIG. 5(g) shows the waveform of the third drive signal generated by the drive signal generator 46 (not shown). The third drive signal is a drive signal for driving the switching element 13 and is input to the gate terminal of the switching element 13 . In this embodiment, the third drive signal is the same signal as the second drive signal. FIG. 5(h) shows the waveform of the fourth drive signal generated by the drive signal generator 46. FIG. The fourth drive signal is a drive signal for driving the switching element 14 and is input to the gate terminal of the switching element 14 . In this embodiment, the fourth drive signal is the same signal as the first drive signal. In order to prevent the switching element 11 and the switching element 12 from being turned on at the same time, a dead time is provided in the driving pulse signals of the first driving signal and the second driving signal, and the switching element 13 and the switching element 14 are switched. A dead time is provided in the driving pulse signals of the third driving signal and the fourth driving signal in order to prevent them from being turned on at the same time.

According to this embodiment, when overcurrent is not detected (when the overcurrent detection signal is a high level signal), the control circuit 4 controls the first to first 4 drive signals are generated and output to the switching elements 11 to 14, respectively. When the output voltage signal V is low, the switching elements 11 to 14 perform ON/OFF operation, so that the output voltage rises. descends. As a result, the output voltage is controlled to the target voltage. Also, the first drive signal and the second drive signal include the same number of drive pulse signals in one switching ON period. Also, the number of drive pulse signals of the first drive signal and the number of drive pulse signals of the second drive signal are the same number within one cycle defined by the clock pulse signal. Further, the pulse width of the driving pulse signal of each driving signal is the same. Therefore, there is no imbalance in the length of the period during which each switching element is ON. Therefore, it is possible to prevent the transformer 2 from being saturated due to biased magnetism. Also, the third drive signal and the fourth drive signal include the same number of drive pulse signals in one switching ON period. Also, the number of drive pulse signals of the third drive signal and the number of drive pulse signals of the fourth drive signal are the same number within one cycle defined by the clock pulse signal. Further, the pulse width of the driving pulse signal of each driving signal is the same. Therefore, there is no imbalance in the length of the period during which each switching element is ON. Therefore, it is possible to prevent the transformer 2 from being saturated due to biased magnetism.

Also in this embodiment, when an overcurrent is detected (when the overcurrent detection signal is a low level signal) or when the output voltage becomes an overvoltage, the first to fourth drive signals become low level signals. Then, the ON/OFF operations of the switching elements 11 to 14 are stopped. Therefore, the output of the DC/DC converter device A1 can be stopped. Also in the present embodiment, when the output voltage signal V is high, the switching elements 11 to 14 stop the ON/OFF operation, so compared to the case of PWM control, the number of times of switching can be reduced, and the switching loss can be reduced. can be reduced. Moreover, according to this embodiment, unlike the case of PWM control, there is no need for designing for preventing oscillation. Therefore, the design is easier than in the case of PWM control, and the time required for design can be shortened.

In the present embodiment, the case where the first drive signal and the fourth drive signal are the same signal (phases match), and the second drive signal and the third drive signal are the same signals (phases match) has been described. However, it is not limited to this. The phases of the first drive signal and the fourth drive signal may be shifted, and the phases of the second drive signal and the third drive signal may be shifted accordingly.

Note that the DC/DC converter device may be one using a push-pull converter or the like. Even in these cases, the same effects as in the first embodiment can be obtained.

FIG. 6 is a circuit diagram showing an outline of an interleaved multiphase converter device A3 according to the third embodiment. In FIG. 6, elements that are the same as or similar to those of the DC/DC converter device A1 (see FIG. 1) according to the first embodiment are denoted by the same reference numerals. 6, the internal configuration of the control circuit 4 is omitted.

As shown in FIG. 6, the interleaved multiphase converter device A3 includes an interleaved multiphase converter circuit 1'' in place of the inverter circuit 1, the transformer 2 and the rectifying/smoothing circuit 3, which is the same as the first embodiment. The interleaved multiphase converter circuit 1″ comprises three switching elements 11, 12, and 13. Each of the switching elements 11, 12, and 13 has a diode connected in series (the source terminal is connected to the cathode terminal of the diode), and the drain terminal is connected to the positive electrode side of the DC power supply B. Each diode has an anode terminal connected to the negative electrode side of the DC power supply B. As shown in FIG. An inductor is connected between each diode connection point of each switching element 11, 12, 13 and one output terminal of the interleaved multiphase converter circuit 1″. , and the other output terminal connected to the negative electrode side of the DC power source B. It has a structure.

Since the internal configuration of the control circuit 4 is the same as that of the control circuit 4 according to the first embodiment, the internal configuration of the control circuit 4 is omitted in FIG. It differs from the control circuit 4 according to the first embodiment in that the generator 46 generates three drive signals. A drive signal generator 46 (not shown) generates a low level signal during the switching OFF period of the ON/OFF control signal output from the D flip-flop 44 (not shown), and at a predetermined cycle during the switching ON period. A signal obtained by alternately generating a high-level drive pulse signal and a low-level signal is generated and output as a first drive signal for driving the switching element 11 .

Also in the drive pulse signal in this embodiment, the period T' is the same period as the period T of the clock pulse signal, as in the first embodiment. The pulses of the driving pulse signal are arranged so as to fit within one period defined by the clock pulse signal. On the other hand, the drive pulse signal in this embodiment has no dead time because only one switching element is arranged in one arm. The drive pulse signal of the first drive signal rises at the start timing of one cycle (rising timing of the clock pulse signal) defined by the clock pulse signal. Note that the position of the pulse of the drive pulse signal in one cycle is not limited. In this embodiment, the pulse width of the drive pulse signal is ⅓ of one cycle. Note that the pulse width of the driving pulse signal is not limited.

In addition, the driving signal generation unit 46 generates a low level signal during the switching OFF period, and generates a signal obtained by alternately generating a high level driving pulse signal and a low level signal generated at a predetermined cycle during the switching ON period. It is generated and output as a second drive signal for driving the switching element 12 . In addition, the driving signal generation unit 46 generates a low level signal during the switching OFF period, and generates a signal obtained by alternately generating a high level driving pulse signal and a low level signal generated at a predetermined cycle during the switching ON period. A third driving signal for driving the switching element 13 is generated and output. The drive pulse signals of the second drive signal and the third drive signal have the same period and pulse width as the drive pulse signal of the first drive signal. The drive pulse signal of the second drive signal is arranged in the low level period between the drive pulse signals of the first drive signal in the switching ON period. Further, the drive pulse signal of the third drive signal is in the low level period between the drive pulse signals of the first drive signal and the low level between the drive pulse signals of the second drive signal in the switching ON period. placed within the period. In other words, the drive pulse signal of the first drive signal, the drive pulse signal of the second drive signal, and the drive pulse signal of the third drive signal do not overlap. In addition, each drive pulse signal may overlap. Further, the pulse width of each drive pulse signal is not limited to 1/3 of one cycle, and may be larger than 0% of one cycle and smaller than 100% of one cycle. Further, the drive pulse signal of the second drive signal and the drive pulse signal of the third drive signal are arranged so as to fall within one cycle defined by the clock pulse signal. In the present embodiment, the drive signal generator 46 generates and outputs a signal obtained by delaying the drive pulse signal of the first drive signal by ⅓ period of the clock pulse signal as the second drive signal. , a signal obtained by delaying the drive pulse signal of the first drive signal by ⅔ cycle of the clock pulse signal is generated and output as the third drive signal.

FIG. 7 is a time chart showing waveforms of signals in each part of the control circuit 4 according to the third embodiment. FIG. 7(a) shows the waveforms of the output voltage signal V and the target voltage _Vref input to the comparator 41a. 7(b) shows the waveform of the state signal, FIG. 7(c) shows the waveform of the clock pulse signal, and FIG. 7(d) shows the waveform of the ON/OFF control signal. 7(e) shows the waveform of the first drive signal input to the switching element 11, FIG. 7(f) shows the waveform of the second drive signal input to the switching element 12, and FIG. The waveform of the third drive signal input to the switching element 13 is shown. The second drive signal is delayed from the first drive signal by ⅓ period of the clock pulse signal (see FIG. 7(c)), and the third drive signal is delayed from the first drive signal. , the signal is delayed by 2/3 period of the clock pulse signal.

According to this embodiment, the switching ON period is a natural number multiple of the cycle T of the clock pulse signal, and the cycle T' of the pulse signals of the first to third drive signals is the same as the cycle T of the clock pulse signal. be. Therefore, the switching ON period includes the drive pulse signals of the first to third drive signals that are natural number multiples of the period T'. Further, the drive pulse signals of the first to third drive signals are arranged so as to fall within one period defined by the clock pulse signal. Therefore, the first to third drive signals include the same number of drive pulse signals in one switching ON period. Further, the number of drive pulse signals of the first to third drive signals is the same number within one cycle defined by the clock pulse signal. Further, the pulse width of the driving pulse signal of each driving signal is the same. Therefore, there is no imbalance in the length of the period during which each switching element is ON. Therefore, it is possible to suppress the occurrence of imbalance in the lives of the switching elements 11 , 12 , 13 .

In addition, although this embodiment demonstrated the case where the number of switching elements was three, it is not restricted to this. The number of switching elements may be two, or four or more. In these cases, the drive pulse signals of the drive signals for driving the switching elements should all include the same number of pulses and have the same pulse width in one switching ON period.

In the above-described first to third embodiments, the case where the control circuit according to the present invention is used in the DC/DC converter device has been described as an example, but the present invention is not limited to this. The control circuit according to the present invention can also be used in other power converters.

The control circuit and DC/DC converter device according to the present invention are not limited to the above-described embodiments. The specific configuration of each part of the control circuit and the DC/DC converter device according to the present invention can be changed in various ways.

A1, A2: DC/DC converter device A3: Interleaved multiphase converter device 1, 1': Inverter circuit 1″: Interleaved multiphase converter circuit 11 to 14: Switching element 15: Resonant circuit 2: Transformer 3: Rectifying and smoothing Circuit 4: Control circuits 41a, 41b: Comparator 42: AND circuit 43: Clock generator 44: D flip-flop 45: Photocoupler 46: Drive signal generator 47: Voltage sensor 48: Current sensor B: DC power supply C: Load

Claims (5)

A control circuit for controlling a device having a plurality of switching elements by outputting a drive signal for driving each switching element,
first sensing means for sensing electrical information relating to the output of said device;
While the value of the electrical information detected by the first detection means exceeds the predetermined upper threshold and continues to be equal to or higher than the predetermined lower threshold, the value of the electrical information is in the first state. outputting a first state signal indicating that the electric information state determination means for outputting a second state signal indicating that the is in the second state;
clock generation means for generating a clock pulse signal at a predetermined cycle;
The first state signal and switching timing adjusting means for adjusting the signal level of the second state signal and outputting the second state signal;
When the signal output from the switching timing adjusting means is the first state signal, the switching elements are not driven, and the signal output from the switching timing adjusting means is the second state signal. driving signal generating means for generating a driving signal for each switching element to drive each switching element;
and
When the signal output from the switching timing adjustment means is the second state signal, the number of drive pulse signals constituting the drive signal for each switching element generated by the drive signal generation means is equal to the clock pulse signal. is the same number within one period defined by, and the pulse widths of the drive pulse signals are all the same,
A control circuit characterized by: second sensing means for sensing other electrical information relating to the output of said device;
Abnormality determination means for determining whether or not an abnormality has occurred in the device based on the electrical information detected by the second detection means;
further comprising
The state determining means outputs the first state signal and the second state signal when the abnormality determining means determines that an abnormality has not occurred, and the abnormality determining means outputs the first state signal and the second state signal. when determined, outputting the first state signal;
2. A control circuit as claimed in claim 1. 3. The control circuit according to claim 1, wherein said upper threshold is a value larger than said lower threshold. 3. The control circuit according to claim 1, wherein said upper threshold and said lower threshold are the same value. a control circuit according to any one of claims 1 to 4;
an inverter circuit;
a rectifier circuit;
a transformer disposed between the inverter circuit and the rectifier circuit;
A DC/DC converter device comprising:

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