JP7001011B2 - Power sequence controller for digital protective relay - Google Patents

Description

The present invention relates to a power supply monitoring function of a digital protective relay and relates to a power supply ON / OFF sequence control circuit.

In the digital protective relay, the voltage of the control power supply is converted into a predetermined voltage by the power supply circuit and supplied to the digital circuit. In a power supply circuit that generates a circuit power supply (for example, 3.3V) for driving an IC or the like from this control power supply (for example, DC: 110V), it becomes electrically unstable in a transient state due to ON / OFF of the control power supply. The circuit may malfunction.

Further, since the time until the power is restored cannot be specified, the operation of the momentary interruption circuit cannot be specified, and there is a possibility that the circuit may be erroneously detected, malfunction, or malfunction.

Conventionally, it is described in Patent Document 1, for example, to prevent a malfunction of a relay at the time of power restoration of a system.

Japanese Unexamined Patent Publication No. 2001-37073

An object of the present invention is to prevent a circuit malfunction or malfunction due to a transient response region at the time of rising and falling of a control power supply in a digital protective relay.

The power sequence control device for a digital protective relay according to claim 1 for solving the above problems is
In a digital protective relay having a first power supply line that converts the voltage of the control power supply into a predetermined voltage by the first power supply circuit and supplies the voltage to the digital circuit via the first power supply switching element.
A power supply that activates the electric circuit connecting the first power supply circuit and the first power supply switching element when the voltage of the control power supply is equal to or higher than the first set voltage, and is used to drive the first sequence control circuit. The power supply for the first sequence control circuit is used, and the electric circuit connecting the first power supply switching element and the digital circuit is used as the power supply for the first digital circuit for driving the digital circuit.
The first sequence control circuit is
A control power supply voltage detection unit that detects the voltage of the control power supply and emits a power supply voltage drop detection signal when the detection voltage is lower than the second set voltage higher than the first set voltage.
A first latch circuit that latches a power supply voltage drop detection signal emitted from the control power supply voltage detection unit, and a first latch circuit.
When the power supply voltage drop detection signal latched by the first latch circuit or the abnormality detection signal is input, a reset pulse is output for a predetermined time to turn off the first power supply switching element. Off control circuit and
A second off control circuit that turns off the first power supply switching element during the period from when the power supply voltage drop detection signal is issued until the control power supply becomes equal to or higher than the second set voltage.
When the second latch circuit for detecting the end of the reset pulse output from the first off control circuit is provided and the power supply voltage drop detection signal is emitted after the end of the reset pulse, the first A third off control circuit that keeps the power supply switching element off,
When the voltage of the control power supply becomes lower than the first set voltage and the power supply for the first sequence control circuit is turned off, the operation of the first off control circuit is reset and the voltage of the control power supply becomes the said. A first reset circuit that resets the operation of the second off control circuit when the voltage exceeds the first set voltage, and
The first latch when the second latch circuit detects the end of the reset pulse, the power supply voltage drop detection signal is not emitted, and the voltage of the control power supply is equal to or higher than the first set voltage. It is characterized by comprising a second reset circuit for resetting a circuit and a second latch circuit.

The power sequence control device for the digital protective relay according to claim 2 is the power sequence control device according to claim 1.
A second power supply line is provided which converts the voltage of the control power supply into a predetermined voltage by the second power supply circuit and supplies the voltage to the transmission signal circuit of the digital circuit via the second power supply switching element.
A power supply that activates the electric circuit connecting the second power supply circuit and the second power supply switching element when the voltage of the control power supply is equal to or higher than the first set voltage, and is used to drive the second sequence control circuit. The power supply for the second sequence control circuit is used, and the electric circuit connecting the second power supply switching element and the transmission signal circuit of the digital circuit is used as the power supply for the second digital circuit for driving the digital circuit.
The second sequence control circuit is controlled to turn on the second power supply switching element after a predetermined time has elapsed after the control power supply exceeds the first set voltage, and the control power supply is less than the second set voltage. When it becomes, it is composed of a circuit that controls off the second power supply switching element.
It has a light emitting element driven by the power supply for the first sequence control circuit and a light receiving element to which the power supply for the second digital circuit is applied and receives the light emitted from the light emitting element. It is characterized by providing a power supply monitoring circuit that uses the potential as a power supply abnormality detection signal.

The power sequence control device for the digital protective relay according to claim 3 is the power sequence control device according to claim 1 or 2.
It is characterized by including a delay circuit for delaying the input of the power supply voltage drop detection signal latched by the first latch circuit to the first off control circuit for a predetermined time.

The power sequence control device for the digital protective relay according to claim 4 is the power sequence control device according to any one of claims 1 to 3.
The first reset circuit detects the voltage of the control power supply, and when the detected voltage is less than the first set voltage, the low level (L) signal is output, and when the detected voltage is equal to or higher than the first set voltage, the high level (H) signal is detected. ) Equipped with a level detection IC that outputs each signal
The second off control circuit includes an AND circuit that takes a logical product of a signal obtained by inverting the power supply voltage drop detection signal and an output signal of the level detection IC, and a delay circuit that delays the output of the AND circuit for a set time. The output of the delay circuit is used as a clock input, the output of the level detection IC is used as a clear input, the first power supply switching element is turned off by the low level (L) output, and the high level (H) output is used. It is characterized by including a third latch circuit that enables the first power supply switching element to be turned on.

(1) According to the inventions according to claims 1 to 4, in the digital protective relay, it is possible to prevent the circuit from malfunctioning or malfunctioning due to the transient response region at the time of rising and falling of the control power supply. ..

In addition, a constant reset time can be secured regardless of the uncertain factor of the power recovery time when a momentary power failure occurs, and the circuit operation can be stabilized.
(2) According to the second aspect of the present invention, since the two power supplies are sequence-controlled, the power supply can be monitored without erroneous detection even when the control power supply starts up or falls off.
(3) According to the third aspect of the present invention, a delay time is provided between the detection of the voltage drop of the control power supply and the off-control of the first power supply switching element. The process of saving data can be performed on the CPU side depending on the delay time.
(4) According to the invention of claim 4, by repeating turning on and off the control power supply in a short time, the control power supply is turned on first, and then the power supply for the first sequence control circuit is started. Even in this case, since the clock input of the third latch circuit in the second off control circuit is delayed by the delay circuit for a set time, the level detection IC, which is the first reset circuit, is transferred to the third latch circuit. The clear input is not delayed (the reset operation of the second off control circuit is delayed). Therefore, the clock input always enters through the delay circuit after the reset of the third latch circuit, and the third latch circuit latches the clock input and outputs a high (H) level, whereby the first power supply without any problem. It is possible to turn on the supply switching element.

The sequence control circuit diagram in Example 1 of this invention. The power supply system diagram in Example 1 of this invention. A time chart illustrating the operation of the first embodiment of the present invention. The sequence control circuit diagram in Example 2 of this invention. A time chart illustrating the operation of the second embodiment of the present invention. The circuit diagram of the power supply monitoring circuit in Example 2 of this invention. The sequence control circuit diagram in Example 3 of this invention. The block diagram of the clock compensation circuit in Example 3 of this invention. A time chart illustrating the operation of the clock compensation circuit according to the third embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments.

FIG. 1 shows the overall configuration of the power supply sequence control device for the digital protective relay according to the first embodiment, and FIG. 2 shows the power supply system diagram thereof. In FIGS. 1 and 2, 101 is a power supply circuit (first power supply circuit) that converts the voltage 110V of the control power supply to 3.3V. The output voltage (3.3V) of the power supply circuit 101 is supplied to a digital circuit (not shown) via the source S and drain D of the FET (field effect transistor) 201 (first power supply switching element). These constitute the first power supply line.

The electric circuit connecting the power supply circuit 101 and the FET 201 is the A power supply (VCC_A: power supply for the first sequence control circuit) for driving the first sequence control circuit described later, and the electric circuit connecting the FET 201 and the digital circuit is a digital circuit. B power supply (VCC_B: power supply for the first digital circuit) for driving.

The A power supply VCS_A operates when the control power supply input to the power supply circuit 101 is 30 V (first set voltage) or more, and the B power supply VCS_B does not turn on unless the control power supply reaches 72 V (second set voltage). ..

The first sequence control circuit is configured as follows.

Reference numeral 10 is a level detection IC that detects the voltage level of the power supply circuit 101, and outputs a low level signal L when the detected voltage is 70 V or less, and outputs a high level signal H when the detected voltage is 72 V or more (has a hysteresis characteristic). Yes).

Reference numeral 11 is a photocoupler to which the output signal of the level detection IC 10 is input, and when the input signal is low level L, it becomes a non-operating state and becomes a high level signal H (power supply voltage drop detection signal (illustration, drop detection = H)). Is output, and when the input signal is high level H, the operation state is set and the low level signal L is output.

These level detection ICs 10 and photocouplers 11 constitute the control power supply voltage detection unit of the present invention.

Reference numeral 12 denotes a latch circuit (first latch circuit) that latches the high level signal H (power supply voltage drop detection signal) output from the photocoupler 11, and latches a detection event at the drop detection edge of the control power supply (110V). (Remembers the drop detection event).

Reference numeral 13 is a delay circuit for outputting the power supply voltage drop detection signal (H) latched by the latch circuit 12 with a delay of 300 msec for a predetermined time, for example, in order to secure a data save processing time by the CPU.

The output signal of the delay circuit 13 is input to the 1-second reset pulse circuit 15 after being ORed with the abnormality detection signal (high level signal H) by the OR circuit 14.

The 1-second reset pulse circuit 15 is a one-shot timer circuit based on an input trigger edge, and the timer IC acts as a one-shot multivibrator by the power supply voltage drop detection signal (high level signal H) input via the OR circuit 14. For a certain period of time (1 second) determined by the resistance value and the capacitor capacity value, a reset pulse (a low level signal L having the opposite polarity if the input signal is a high level signal H) is used in the NAND circuit (negative gate of logical product) 21. Output to the input end of 1 and the latch circuit 16 (second latch circuit).

The output of the 1-second reset pulse circuit 15 returns to the original high-level signal H when the 1-second pulse (low level signal L) ends.

When the output side of the NAND circuit 21 is connected to the gate G of the FET 201 via the resistor R1 and any one or more of the signals input to the first to third input terminals is low level L, For example, during the period in which the low level L of the 1-second pulse is input, the output becomes the high level H, and the FET 201 is configured to be off-controlled.

The OR circuit 14, the 1-second reset pulse circuit 15, and the NAND circuit 21 constitute the first off control circuit of the present invention.

The output signal of the photocoupler 11 is input to the first input terminal of the NOT circuit 17 and the NAND circuit 22, and is sent to a CPU (not shown) as an NMI (Non Maskable Interrupt) signal.

The CPU performs data saving processing based on the input NMI signal.

The output signal of the NOT circuit 17 is input to the second input terminal of the latch circuit 18 and the NAND circuit 23. When the voltage of the control power supply is low (when it is 70V or less), the latch circuit 18 latches the low level L output of the NOT circuit 17, and the low level L is applied to the NAND circuit 21 until the control power supply voltage reaches 72V. Output to the input end of 2.

The low level signal input from the latch circuit 18 to the second input terminal of the NAND circuit 21 maintains the off control of the FET 201 until the control power supply voltage reaches 72 V.

The NOT circuit 17 and the latch circuit 18 constitute the second off control circuit of the present invention.

The latch circuit 16 is a circuit that detects and latches the end edge of the 1-second pulse, and when the end of the reset pulse output from the 1-second reset pulse circuit 15 is detected, the high-level signal H is input to the second input of the NAND circuit 22. Output to the end and the first input end of the NAND circuit 23.

In the NAND circuit 22, even if the high level signal H indicating the end of the 1-second pulse is input to the second input end, the signal from the photocoupler 11 input to the first input end is the high level signal H. That is, if it is a power supply voltage drop detection signal, the low level signal L is output to the third input terminal of the NAND circuit 21.

Therefore, even if the signal at the first input end of the NAND circuit 21 (the output signal of the 1-second reset pulse circuit 15) becomes the high-level signal H after the end of the 1-second pulse, the NAND is input to the third input end. The low level signal L from the circuit 22 maintains the high level H of the output, which continues the off control of the FET 201.

The latch circuit 16 and the NAND circuit 22 constitute the third off control circuit of the present invention.

Reference numeral 19 is a level detection IC that detects the voltage of the A power supply VCS_A, outputs a low level L signal when the control power supply (110V) becomes less than 30V and the A power supply VCS_A is turned off, and outputs a low level L signal otherwise. Output H.

The low level signal L output from the level detection IC 19 is used as a reset signal of the 1-second reset pulse circuit 15, and the high level signal H is used as a reset signal of the latch circuit 18.

The output signal of the level detection IC 19 is input to the third input end of the NAND circuit 23.

The first input end of the NAND circuit 23 is high level H (the pulse for 1 second has ended), the second input end is high level H (control power supply (110V) is restored to 72V or more). When the third input end is at high level H (A power supply VCS_A is in the activated state), the output of the NAND circuit 23 becomes a low level L signal.

The low level L output signal of the NAND circuit 23 is used as a reset signal of the latch circuit 12 and the latch circuit 16.

Note that R2 in FIG. 1 is a resistance connected between the source S and the gate G of the FET 201. Further, 300 in FIG. 2 is a connector for connecting the control power supply (110V) and the power supply circuit 101.

The functions of the main parts of the first sequence control circuit configured as described above are summarized as follows.

<Latch circuit 12 (1): Memory of drop detection event>
Latch the detection event at the drop detection edge of the control power supply (110V). A circuit for always resetting (3.3V cutoff of B power supply VCS_B) when a voltage drop occurs even once. Further, even if the voltage flutters near the detection level in a short time, the reset is not accepted until the reset is generated once, so that the stable operation of the reset is achieved.

<Latch circuit 16 (2): 1 second pulse end detection>
1-second reset pulse Detects and latches the end edge of the 1-second pulse (1 second reset) from the circuit 15. The latch circuit 12 (1) is cleared via the NAND circuit 23 to prepare for the next drop detection. Further, the control power supply state at the end of the 1-second pulse is determined by NAND with the power supply voltage drop detection signal in the NAND circuit 22, and if the power is not restored, the FET 201 for supplying the B power supply VCS_B is left OFF.

<Latch circuit 18 (3): Lock up to 72V control power supply>
A circuit that locks the FET 201 for supplying the B power supply VCS_B until the control power supply rises to 72V (the purpose is not to turn on the VCS 3.3V circuit at a low voltage of the control power supply). It is started after the control power is turned on, and then the latch is held until the control power is lowered and the A power supply VCS_A is exhausted.

<1 second reset pulse circuit 15 (4): securing reset time>
One-shot timer circuit with input trigger edge. The power supply voltage drop detection is received via the delay circuit 13, and a pulse for 1 second is generated. This pulse shuts off the FET 201 for 1 second.

The circuit shown in FIG. 1 can also be realized in a programmable device such as FPGA (Field Programmable Gate Array).

Next, the operation of the sequence control circuit configured as described above will be described together with the time chart of FIG.

In FIG. 3, since the control power supply (P110V) is not turned on in the time zone before the time t1, the output of the photocoupler 11 is high level H, the output of the latch circuit 18 is low level L, and the output of the NAND circuit 21 is high. The level is H, and the FET 201 is off-controlled.

When the control power supply (P110V) rises at time t1 and the voltage reaches 30V at time t2, the A power supply VCS_A is started. Further, when the control power supply (P110V) reaches 30V at time t2, the output of the level detection IC 19 is switched to the high level signal H, and the latch circuit 18 is reset.

When the control power supply (P110V) reaches 72V at time t3, the output of the photocoupler 11 is low level L, the input of the latch circuit 12 is low level L, the input of the 1-second reset pulse circuit 15 is low level L, and the output is high. Since the level is H, the input and output of the latch circuit 18 are high level H, the first input end of the NAND circuit 22 is low level L, and the output end is high level H, the NAND circuit 21 outputs a low level signal. The FET 201 is turned on and controlled. As a result, the B power supply VCS_B is initially started.

During the period from time t3 to time t4 when the instantaneous voltage drop of the control power supply (P110V) occurs, the signals at the three input ends of the NAND circuit 23 are all high level H, so that the NAND circuit 23 has a low level L. A signal is output to reset the latch circuit 12 and the latch circuit 16.

When a momentary voltage drop occurs in the control power supply (P110V) at time t4 and becomes 70V or less, a high level H signal is output from the photocoupler 11 and the latch circuit 12 latches it.

Since the high-level output signal of the latch circuit 12 is delayed by the delay circuit 13, the CPU performs data saving processing for the time from the time t4 until the time t5 after the delay time of the delay circuit 13 (300 msec in this example) elapses. Will be done.

When a high level H signal is input to the 1-second reset pulse circuit 15 at the time t5 after the delay, the 1-second reset pulse circuit 15 outputs a 1-second reset pulse (low-level signal), so that the NAND circuit 21 A high level H signal is output to control the FET 201 to be off, whereby the B power supply VCS_B is cut off.

The latch circuit 16 detects the end of the 1-second reset pulse output by the 1-second reset pulse circuit 15 and outputs a high-level H signal. At this time (between time t5 and t6), the control power supply (P110V) is restored. Both the NAND circuit 22 and the latch circuit 18 output a high level H signal because they are powered.

Since the output of the 1-second reset pulse circuit 15 switches to the high-level H signal at the time t6 when the 1-second reset pulse (low level L signal) of the 1-second reset pulse circuit 15 ends, the output signal of the NAND circuit 21 is low. It becomes a level signal, FET 201 is turned on, and B power supply VCC_B is restarted.

During the period from time t6 to time t7 when the voltage drop of the control power supply (P110V) occurs, the signals at the three input ends of the NAND circuit 23 are all high level H, so that the low level L signal from the NAND circuit 23 Is output to reset the latch circuit 12 and the latch circuit 16.

When a voltage drop occurs in the control power supply (P110V) at time t7 and becomes 70V or less, a high level H signal is output from the photocoupler 11 and the latch circuit 12 latches it.

Since the high-level output signal of the latch circuit 12 is delayed by the delay circuit 13, data saving processing is performed by the CPU during the time from the time t7 to the time t8 after the delay time of the delay circuit 13 has elapsed.

When a high level H signal is input to the 1-second reset pulse circuit 15 at the time t8 after the delay, the 1-second reset pulse circuit 15 outputs a 1-second reset pulse (low-level signal), so that the NAND circuit 21 A high level H signal is output to control the FET 201 to be off, whereby the B power supply VCS_B is cut off.

The latch circuit 16 detects the end of the 1-second reset pulse output by the 1-second reset pulse circuit 15 and outputs a high-level H signal. At this time (between time t8 and t9), the control power supply (P110V) is restored. Both the NAND circuit 22 and the latch circuit 18 output a high level H signal because they are powered.

Since the output of the 1-second reset pulse circuit 15 switches to the high-level H signal at the time t9 when the 1-second reset pulse (low level L signal) of the 1-second reset pulse circuit 15 ends, the output signal of the NAND circuit 21 is low. It becomes a level signal, FET 201 is turned on, and B power supply VCC_B is restarted.

During the period from time t9 to time t10 when the voltage drop of the control power supply (P110V) occurs, the signals at the three input ends of the NAND circuit 23 are all high level H, so that the low level L signal from the NAND circuit 23 Is output to reset the latch circuit 12 and the latch circuit 16.

When a momentary voltage drop occurs in the control power supply (P110V) at time t10 and becomes 70V or less, a high level H signal is output from the photocoupler 11 and the latch circuit 12 latches it.

Since the high-level output signal of the latch circuit 12 is delayed by the delay circuit 13, the CPU performs data saving processing for the time from the time t10 until the time t11 after the delay time of the delay circuit 13 (300 msec in this example) elapses. Will be done.

When a high level H signal is input to the 1-second reset pulse circuit 15 at the time t11 after the delay, the 1-second reset pulse circuit 15 outputs a 1-second reset pulse (low-level signal), so that the NAND circuit 21 A high level H signal is output to control the FET 201 to be off, whereby the B power supply VCS_B is cut off.

When the control power supply (P110V) further decreases to less than 30V at time t12, the A power supply VCS_A is lost and the level detection IC 19 outputs a low level L signal. The 1-second reset pulse circuit 15 is reset by the low level L signal of the level detection IC 19.

By this reset, the output of the 1-second reset pulse circuit 15 is canceled before 1 second elapses and becomes high level H.

On the other hand, since the latch circuit 16 outputs the high level H signal when the 1-second pulse of the 1-second reset pulse circuit 15 is canceled, the second input end of the NAND circuit 22 becomes the high level H, and the control power supply becomes Since (P110V) has not recovered to 70V to 72V, the first input terminal of the NAND circuit 22 has a high level H, so that the NAND circuit 22 outputs a low level L signal.

As a result, the OFF control of the FET 201 is maintained from the time t13 when the control power supply (P110V) becomes 30V or more and the A power supply VCS_A restarts until the control power supply (P110V) reaches 72V.

When the control power supply (P110V) reaches 72V at time t14, the output becomes high level H because the first input end of the NAND circuit 22 becomes low level L. Therefore, all the first to third input ends of the NAND circuit 21 become high level H, the output becomes a low level L signal, the FET 201 is turned on, and the B power supply VCS_B is activated.

During the period from time t14 to time t15 when the voltage drop of the control power supply (P110V) occurs, the signals at the three input ends of the NAND circuit 23 are all high level H, so that the low level L signal from the NAND circuit 23 Is output to reset the latch circuit 12 and the latch circuit 16.

When a momentary voltage drop occurs at the control power supply (P110V) at time t15 and becomes 70V or less, a high level H signal is output from the photocoupler 11 and the latch circuit 12 latches it.

Since the high-level output signal of the latch circuit 12 is delayed by the delay circuit 13, the CPU performs data saving processing for the time from the time t15 until the time t16 after the delay time of the delay circuit 13 (300 msec in this example) elapses. Will be done.

When a high level H signal is input to the 1-second reset pulse circuit 15 at the time t16 after the delay, the 1-second reset pulse circuit 15 outputs a 1-second reset pulse (low-level signal), so that the NAND circuit 21 A high level H signal is output to control the FET 201 to be off, whereby the B power supply VCS_B is cut off.

When the voltage of the control power supply (P110V) becomes less than 30V at time t17, the A power supply VCS_A goes down.

As described above, according to the first embodiment, it is possible to prevent the circuit from malfunctioning or malfunctioning due to the transient response region at the time of rising and falling of the control power supply. Further, it is possible to stabilize the circuit operation by securing a constant reset time regardless of the uncertain factor of the power recovery time when the momentary power failure occurs.

In a digital protective relay, in a configuration in which a transmission function is mounted on a device as an optional function, the transmission signal circuit may be an isolated power supply. Correspondingly, in the second embodiment, another power supply circuit (110V → 3.3V) of FIG. 1 is additionally provided, and two 3.3V power supply circuits are configured as shown in FIG.

FIG. 4 shows only the second power supply line and the second sequence control circuit additionally provided, and the first power supply line and the first sequence control circuit of the system 1 (main system) are shown. Illustration is omitted (system 1 is configured in the same manner as in FIG. 1).

In FIG. 4, 102 is a power supply circuit (second power supply circuit) that converts the voltage 110V of the control power supply to 3.3V. The output voltage (3.3V) of the power supply circuit 102 is supplied to the transmission signal circuit of the digital circuit (not shown) via the source S and drain D of the FET 202 (second power supply switching element). These constitute a second power supply line.

The electric circuit connecting the power supply circuit 102 and the FET 202 is the A power supply (VCC2_A: power supply for the second sequence control circuit) for driving the second sequence control circuit described later, and the electric circuit connecting the FET 202 and the digital circuit is a digital circuit. Is used as a B power supply (VCC2_B: a power supply for a second digital circuit) for driving the above.

The A power supply VCS2_A operates when the control power supply (P110V) is 30V or more and fails when the control power supply (P110V) is less than 30V, similarly to the A power supply VCS_A of the 1st system (FIG. 1).

The second sequence control circuit is configured as follows.

Reference numeral 10 is a level detection IC for detecting the voltage level of the power supply circuit 102, which is common with the level detection IC (10) of the first system (FIG. 1), and outputs a low level signal L when the detection voltage is 70 V or less. , A high level signal H is output when the voltage is 72 V or higher (has a hysteresis characteristic).

Reference numeral 31 is a photocoupler to which the output signal of the level detection IC 10 is input, and when the input signal is low level L, it is in a non-operating state and the low level signal L (power supply voltage drop detection signal (illustration, drop detection = L)). Is output, and when the input signal is high level H, the operation state is set and the high level signal H is output. The output signal of the photocoupler 31 is input to the first input terminal of the NAND circuit 24.

32 detects the voltage of the A power supply VCS2_A, outputs a low level L signal when the detected voltage is less than 30 V, and outputs a high level H signal after a predetermined time (for example, 700 msec) delay after detecting 30 V or more. It is a detection IC.

This level detection IC 32 acts as a reset IC for activating the B power supply VCS2_B of the second system with a delay of a predetermined time (for example, 700 msec) from the activation of the A power supply VCS2_A of the second system.

The output signal of the level detection IC 32 is input to the second input end of the NAND circuit 24, and the output end of the NAND circuit 24 is connected to the gate G of the FET 202 via the resistor R21. A resistor R22 is connected between the source S and the gate G of the FET 202.

In the NAND circuit 24, when any one or more of the first and second input ends is low level L, the output becomes high level H and the FET 202 is off-controlled, and both of the two input ends are high level. When it is H, the output becomes low level L and the FET 202 is configured to be on-controlled.

Next, the operation of the sequence control circuit of the second embodiment including the system 1 and the system 2 will be described together with the time chart of FIG. FIG. 5 shows the transition of the voltage of the control power supply (P110V), the A power supply VCS_A of the 1 system, the A power supply VCS2_A of the 2 system, the B power supply VCS_B of the 1 system, and the B power supply VCS2_B of the 2 system.

Since the control power supply (P110V) does not start up in the time zone before the time t1, in the 1 system, the output of the photocoupler 11 in FIG. 1 is high level H, the output of the latch circuit 18 is low level L, and the NAND circuit 21. The output of is high level H, and the FET 201 is off-controlled.

Further, in the second system, since the output of the photocoupler 31 in FIG. 4 is low level L and the output of the level detection IC 32 is low level L, the output of the NAND circuit 24 is high level H and the FET 202 is off-controlled. ..

The control power supply (P110V) rises at time t1, and when the voltage reaches 30V at time t2, both the A power supply VCS_A of the 1 system and the A power supply VCS2_A of the 2 system start up.

When the control power supply (P110V) reaches 72V at time t3, the output of the photocoupler 11 in FIG. 1 is low level L, the input of the latch circuit 12 is low level L, and the input of the 1-second reset pulse circuit 15 is in the 1st system. The low level L and the output become the high level H, the input and the output of the latch circuit 18 become the high level H, the first input end of the NAND circuit 22 becomes the low level L, and the output end becomes the high level H. 21 outputs a low level signal and the FET 201 is on-controlled. As a result, the B power supply VCS_B is initially started.

On the other hand, in the second system, the high level H signal from the photocoupler 31 of FIG. 4 is input to the first input terminal of the NAND circuit 24. Then, at the time t3 when the delay time of the level detection IC 32 has elapsed, the output of the level detection IC 32 is inverted to the high level H, so that the output of the NAND circuit 24 becomes the low level L and the FET 202 is on-controlled. As a result, the B power supply VCS2_B of the 2 system is started.

At time t15, when the voltage of the control power supply (P110V) drops to less than 70V, the output of the photocoupler 31 in FIG. 4 becomes a low level L signal in the second system, so that the output of the NAND circuit 24 becomes high level H. Then, the FET 202 is turned off and the B power supply VCS2_B of the second system goes down.

On the other hand, in the 1st system, the output of the NAND circuit 21 becomes a high level H signal after a delay of 300 msec by the delay circuit 13 (FIG. (6) in FIG. 1), so that the FET 201 of the 1st system is turned off at time t16 and the 1st system B power supply VCS_B goes down.

When the voltage of the control power supply (P110V) becomes less than 30V at time t17, the A power supply VCS_A of the 1st system and the A power supply VCS2_A of the 2nd system go down.

Further, in the second embodiment, as shown in FIG. 6, the B power supply VCS2_B of the system 2 is used to monitor the power supply of the A power supply VCS_A of the system 1 (main system).

In FIG. 6, 51 is a photo in which a light emitting diode 51D in which the voltage of the A power supply VCC_A of the system 1 is applied to the anode via the resistor R31 and the B power supply VCS2_B of the system 2 are applied to the collector side via the resistor R32. It is a photocoupler having a transistor 51T.

Reference numeral 52 is a NOT circuit in which one end is connected to the collector of the phototransistor 51T and an external abnormality signal is output from the other end.

In the power supply monitoring circuit of FIG. 6, when the A power supply VCS_A of the system 1 is normal, the photocoupler 51 is in the ON state, the collector side potential of the phototransistor 51T becomes the GND level of the B power supply VCS2_B of the system 2, and the NOT circuit 52. The output of is high level H.

When the A power supply VCS_A of the system 1 is abnormal, the photocoupler 51 is inactive, the collector side potential of the phototransistor 51T becomes high level H, and the output of the NOT circuit 52 becomes low level L, causing an abnormality. Can be detected.

As described above, according to the second embodiment, the reset release time of the level detection IC 19 and the delay circuit 13 of FIG. 1 and the reset release time of the level detection IC 32 of FIG. 4 are adjusted as shown in FIG. By sequence control, the power supply of the system 1 (main system) can be monitored by using the system 2 (transmission power supply) without erroneous detection even when the power is turned on or off.

In the circuit of FIG. 1, when the control power supply is repeatedly turned on and off in a short time, the timing of reaching the threshold voltage of the logic IC (level detection IC 19) changes depending on the residual voltage, and the reset signal of the IC and the latch circuit 18 can be coordinated. May not be.

That is, if the control power supply (P110V) is repeatedly turned on and off in a short time, the start timing of the A power supply VCS_A (3.3V) may shift and the control power supply (P110V) may start up after the start-up.

In this case, since the power recovery detection H signal from the NOT circuit 17 reaches the latch circuit 18 earlier than the reset signal input from the level detection IC 19 to the latch circuit 18, the latch circuit 18 latches the power recovery detection H signal. I can't. As a result, even though the control power supply is restored, the H level signal cannot be output from the latch circuit 18 to turn on the FET 201.

In the third embodiment, a clock compensation circuit is provided so that the latch circuit 18 operates correctly even in a special case where the control power is repeatedly turned on and off in a short time as described above.

FIG. 7 shows a sequence control circuit according to the third embodiment. In FIG. 7, the difference from FIG. 1 is that between the level detection IC 19, the NOT circuit 17, and the latch circuit 18, one input end is connected to the output end side of the NOT circuit 17, and the other input end is the level detection IC 19. The AND circuit 61 connected to the output side of the AND circuit 61 and the resistor 62 and the capacitor 63 constituting the delay circuit connected between the output side of the AND circuit 61 and the clock input terminal of the latch circuit 18 are provided to detect the level. The output (reset signal) of the IC 19 is introduced into the clear terminal (CLR) of the latch circuit 18, and the other parts are configured in the same manner as in FIG.

The AND circuit 61, the resistor 62, and the capacitor 63 constitute the clock compensation circuit (60) in the third embodiment.

FIG. 8 shows the details of the clock compensation circuit 60 and the latch circuit 18. In FIG. 8, the AND circuit 61 takes an AND of the A signal (output signal of the NOT circuit 17) input to one input end and the B signal (output signal of the level detection IC 19) input to the other input end. ..

The output end of the AND circuit 61 is grounded via the resistor 62 and the capacitor 63, and the common connection point of the resistor 62 and the capacitor 63 is connected to the clock terminal (CLK) of the latch circuit 18. The voltage of the A power supply VCC_A (3.3V) of FIG. 7 is applied to the PRE terminal and the D terminal of the latch circuit 18 via the resistor R71.

The B signal input to the other input end of the AND circuit 61, that is, the output signal of the level detection IC 19, is input to the clear terminal CLR of the latch circuit 18. The Q output of the latch circuit 18 is connected to the second input end of the NAND circuit 21 of FIG.

The PRE terminal and the clear terminal CLR of the latch circuit 18 are configured to be low active (negative logic).

Next, the operation of the sequence control circuit of the third embodiment configured as described above will be described. The normal operation is the same as that of the first embodiment, and here, the operation when the control power supply (P110V) is repeatedly turned on and off in a short time will be described together with the time chart of FIG.

In FIG. 9, (a) is the voltage of the control power supply (P110V), (b) is the voltage of the A power supply VCC_A (3.3V), and (c) is the input of the photocoupler 11 (output signal of the level detection IC 10). d) is the output of the photocoupler 11, (e) is the signal at one input end of the AND circuit 61 (A signal in FIG. 8; the output signal of the NOT circuit 17), and (f) is the other input end of the AND circuit 61. (B signal in FIG. 8; output signal of level detection IC 19), (g) is the output signal of the clock compensation circuit 60 (signal input to the clock terminal CLK of the latch circuit 18), and (h) is the latch circuit 18. The recognition (latch output) of the clock CLK in the above is shown respectively.

First, at time t1, the control power supply (P110V) rises earlier than the A power supply VCS_A (FIG. 9A), and from that rise until the level detection IC 10 detects the voltage 72V, for example, at time t2 after 34 msec. A high level signal H is input from the level detection IC 10 to the photocoupler 11 (FIG. 9 (c)).

From this time t2, the output of the photocoupler 11 transitions in the low level L direction (FIG. 9D), and at the time t3 when the low level L is established, the output of the NOT circuit 17, that is, to one input end of the AND circuit 61. The input A signal becomes the high level H (FIG. 9 (e)).

Next, at a time t4 when, for example, 182 msec has elapsed from the time t1 when the control power supply (P110V) has started up, the voltage of the power supply A power supply VCS_A starts to rise and starts to rise (FIG. 9 (b)).

Next, at time t6, for example, 3 msec after the voltage of the A power supply VCS_A reaches 30 V at time t5, the level detection IC 19 outputs a high level H signal (FIG. 9 (f)).

The input of the high level H signal from the level detection IC 19 satisfies the AND condition of the AND circuit 61, and the high level H signal is output from the AND circuit 61, but is delayed by the delay circuit including the resistor 62 and the capacitor 63. Therefore, the output of the clock compensation circuit 60 (clock CLK sent to the latch circuit 18) gradually transitions in the high level direction along the delay time constant (FIG. 9 (g)).

Next, at time t7 when the signal reaching the clock terminal CLK of the latch circuit 18 becomes completely high level H, the latch circuit 18 latches the high level H input and outputs the high level H signal to the NAND circuit 21 ( FIG. 9 (h).

As a result, all the inputs of the NAND circuit 21 become high level H, and the FET 201 is turned on by the low level L signal output from the NAND circuit 21.

The resistor 62 and the capacitor 63 constituting the delay circuit are set to values that can realize a delay time such that the clock CLK is input later than the clear release (reset) of the latch circuit 18. ..

As described above, according to the third embodiment, a special case in which the control power supply (P110V) is started first and then the A power supply VCS_A is started by repeating the on / off of the control power supply (P110V) in a short time. Even so, since the clock input of the latch circuit 18 is delayed for a set time by the delay circuit (resistor 62 and capacitor 63), the clear (CLK) input from the level detection IC 19 to the latch circuit 18 is delayed (reset operation is delayed). ) There is no such thing.

Therefore, since the clock CLK always arrives after the reset of the latch circuit 18, the FET 201 can be turned on without any problem.

10, 19, 32 ... Level detection IC
11, 31, 51 ... Photocoupler 12, 16, 18 ... Latch circuit 13 ... Delay circuit 14 ... OR circuit 15 ... 1 second reset pulse circuit 17, 52 ... NOT circuit 21 to 24 ... NAND circuit 60 ... Clock compensation circuit 61 ... AND circuit 62 ... Resistance 63 ... Condenser 101, 102 ... Power supply circuit 201, 202 ... FET

Claims (4)

In a digital protective relay having a first power supply line that converts the voltage of the control power supply into a predetermined voltage by the first power supply circuit and supplies the voltage to the digital circuit via the first power supply switching element.
A power supply that activates the electric circuit connecting the first power supply circuit and the first power supply switching element when the voltage of the control power supply is equal to or higher than the first set voltage, and is used to drive the first sequence control circuit. The power supply for the first sequence control circuit is used, and the electric circuit connecting the first power supply switching element and the digital circuit is used as the power supply for the first digital circuit for driving the digital circuit.
The first sequence control circuit is
A control power supply voltage detection unit that detects the voltage of the control power supply and emits a power supply voltage drop detection signal when the detection voltage is lower than the second set voltage higher than the first set voltage.
A first latch circuit that latches a power supply voltage drop detection signal emitted from the control power supply voltage detection unit, and a first latch circuit.
When the power supply voltage drop detection signal latched by the first latch circuit or the abnormality detection signal is input, a reset pulse is output for a predetermined time to turn off the first power supply switching element. Off control circuit and
A second off control circuit that turns off the first power supply switching element during the period from when the power supply voltage drop detection signal is issued until the control power supply becomes equal to or higher than the second set voltage.
When the second latch circuit for detecting the end of the reset pulse output from the first off control circuit is provided and the power supply voltage drop detection signal is emitted after the end of the reset pulse, the first A third off control circuit that keeps the power supply switching element off,
When the voltage of the control power supply becomes lower than the first set voltage and the power supply for the first sequence control circuit is turned off, the operation of the first off control circuit is reset and the voltage of the control power supply becomes A first reset circuit that resets the operation of the second off control circuit when the voltage exceeds the first set voltage, and
The first latch when the second latch circuit detects the end of the reset pulse, the power supply voltage drop detection signal is not emitted, and the voltage of the control power supply is equal to or higher than the first set voltage. A power sequence control device for a digital protection relay, comprising: a second reset circuit for resetting the circuit and a second latch circuit. A second power supply line is provided which converts the voltage of the control power supply into a predetermined voltage by the second power supply circuit and supplies the voltage to the transmission signal circuit of the digital circuit via the second power supply switching element.
A power supply that activates the electric circuit connecting the second power supply circuit and the second power supply switching element when the voltage of the control power supply is equal to or higher than the first set voltage, and is used to drive the second sequence control circuit. The power supply for the second sequence control circuit is used, and the electric circuit connecting the second power supply switching element and the transmission signal circuit of the digital circuit is used as the power supply for the second digital circuit for driving the digital circuit.
The second sequence control circuit is controlled to turn on the second power supply switching element after a predetermined time has elapsed after the control power supply exceeds the first set voltage, and the control power supply is less than the second set voltage. When it becomes, it is composed of a circuit that controls off the second power supply switching element.
It has a light emitting element driven by the power supply for the first sequence control circuit and a light receiving element to which the power supply for the second digital circuit is applied and receives the light emitted from the light emitting element. The power supply sequence control device for a digital protective relay according to claim 1, further comprising a power supply monitoring circuit that uses a potential as a power supply abnormality detection signal. The invention according to claim 1 or 2, further comprising a delay circuit for delaying the input of the power supply voltage drop detection signal latched by the first latch circuit to the first off control circuit for a predetermined time. Power sequence controller for digital protective relays. The first reset circuit detects the voltage of the control power supply, and when the detected voltage is less than the first set voltage, the low level (L) signal is output, and when the detected voltage is equal to or higher than the first set voltage, the high level (H) signal is detected. ) Equipped with a level detection IC that outputs each signal
The second off control circuit includes an AND circuit that takes a logical product of a signal obtained by inverting the power supply voltage drop detection signal and an output signal of the level detection IC, and a delay circuit that delays the output of the AND circuit for a set time. The output of the delay circuit is used as a clock input, the output of the level detection IC is used as a clear input, the first power supply switching element is turned off by the low level (L) output, and the high level (H) output is used. The power supply sequence of the digital protection relay according to any one of claims 1 to 3, further comprising a third latch circuit for turning on the first power supply switching element. Control device.

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