JP6523733B2 - Binary value conversion circuit and method thereof, AD converter and solid-state imaging device - Google Patents

Description

  The present invention relates to a binary value conversion circuit and method thereof, an AD converter, and a solid-state imaging device.

An image sensor having a solid-state image sensor such as a CMOS image sensor is known. It is known that when performing AD conversion on the output voltage of a solid-state imaging device of an image sensor, AD conversion is performed using a single slope AD converter (see, for example, FIGS. 1 and 2 of Patent Document 1 and its description) . In the single slope type AD converter, the sweep operation of the ramp waveform reference voltage is started at the same time the count operation of the counter is started, and when the reference voltage falls below the output voltage from the solid state imaging device, the output signal of the comparator Invert to stop the counting operation of the counter. The single slope AD converter has various advantages such as easy CDS operation. However, since the single slope AD converter needs to count 2 ⁿ resolutions for n bits, increasing the resolution of AD conversion prolongs the period of count operation for AD conversion and increases the AD conversion resolution. The time required for conversion may increase. For example, when the resolution is 8 bits, it is 256 counts, whereas when the resolution is 10 bits, it is necessary to count 1024.

  In order to shorten the time required for AD conversion, it is known to AD convert the upper bits with a single slope type AD converter and convert the lower bits with TDC (for example, FIGS. And its description). By converting the lower bits with TDC, it is possible to increase the resolution without increasing the count number.

JP, 2010-258806, A

Column parallel single-slope ADC with time to digital converter for CMOS imager, S. Muung, M. Ikebe, IEEE ICECS 2010 "High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor", Yoshikazu Nitta et al., ISSCC, Feb, 2006

  However, in the AD converter described in FIG. 6 and the like of Patent Document 1, the binary value of the lower bit converted by TDC is encoded into the binary value of the upper bit using a counter. In the AD converter described in FIG. 6 and the like of Patent Document 1, since a binary value of lower bits is encoded using a counter, the time required to encode the binary value may increase. In addition, it is required to ensure consistency such as carry-over in the CDS operation between a single slope type AD converter that AD converts the upper bits and TDC that converts the lower bits. For this reason, there is a possibility that the circuit configuration of the binary value conversion circuit that encodes the binary value output from TDC to correspond to the output binary value of the single slope type AD converter may be complicated.

  In one embodiment, it is an object of the present invention to provide a binary value conversion circuit that has a simple circuit configuration and can operate at high speed.

  In one aspect, the binary value conversion circuit according to the present invention receives a plurality of clock signals having edges that are the same in period and out of phase with each other, and a transition signal that transitions from the first level to the second level. A phase detection circuit that outputs a first binary value indicating the timing relationship between the edges of the plurality of clock signals and the transition timing of the transition signal from the first level to the second level, and the binary value storing the plurality of binary values And an encoder having a memory circuit and a selection circuit that selects any one of a plurality of binary values based on the first binary value, wherein an inverted bit obtained by inverting the least significant bit of the first binary value is used. The most significant bit and any one of a plurality of binary values selected based on the first binary value from the least significant bit to the least significant bit of the most significant bits; And it outputs a binary value, characterized in that.

Furthermore, in the binary value conversion circuit according to the present invention, the phase detection circuit responds to the anteroposterior relationship between any one edge of the plurality of clock signals and the transition timing of the transition signal from the first level to the second level. from the first latch circuit for outputting a 1-bit output signal has the 2 ⁿ latch circuits up to the 2 ⁿ latch circuits, a group of output signals, each of the 2 ⁿ latch circuit outputs, respectively The selection circuits are arranged in the order of the phases of the corresponding clock signals and output as a first binary value of 2 ⁿ bits, and the selection circuit has 2 ⁿ selection elements, of the 2 ⁿ selection elements (2 ⁿ -1) select one of a plurality of binary values of n bits when two adjacent bits of the first binary value are input and the two input bits are different; ^n-number of timing detection signal element In the other, the most significant bit and the least significant bit of the first binary value are input, and when the two input bits match, the other one of the multiple binary values of n bits is selected It is preferable to do.

  Furthermore, in the binary value conversion circuit according to the present invention, when the least significant bit of the first binary value is “1”, the binary value storage circuit starts with the least significant bit of the least significant bit of the first binary value. According to the selection of the selection circuit, an n-bit binary value indicating the number of "1" s contained in the upper bits is output, and when the least significant bit of the first binary value is "0", the first binary value is output. It is preferable to output an n-bit binary value indicating the number of “0” s contained in the 1-bit upper bit of the least significant bit to the most significant bit according to the selection of the selection circuit.

  In another aspect, the binary value conversion method according to the present invention inputs a plurality of clock signals having edges that are the same in period and out of phase with each other, and a transition signal that transitions from the first level to the second level. And generates a first binary value indicating the timing relationship between the edges of the plurality of clock signals and the transition timing of the transition signal from the first level to the second level, and based on the first binary value, the binary value storage circuit A plurality of binary values selected based on the first binary value, with any one of the plurality of stored binary values selected and the inverted bit obtained by inverting the least significant bit of the first binary value as the most significant bit And outputting a second binary value in which one of the bits is the least significant bit from the least significant bit of the most significant bit.

  In another aspect, the AD converter according to the present invention is a comparator that compares a reference voltage whose input voltage changes linearly with time with a comparator that compares the input voltage with edges having the same cycle and different phases. A binary value conversion circuit to which a plurality of clock signals having a clock signal and a transition signal transitioning from the first level to the second level in response to a change in the comparison result of the comparator are input. Based on a first binary value, a phase detection circuit that outputs a first binary value indicating a timing relationship between transition timings of the transition signal from the first level to the second level, and a plurality of binary values. And an encoder having a selection circuit for selecting any one of a plurality of binary values, and an inversion bit obtained by inverting the least significant bit of the first binary value is the highest. A binary value conversion circuit for outputting a lower binary value in which bits and any one of a plurality of binary values selected based on the first binary value are regarded as the least significant bit from the least significant bit of the most significant bit; It is characterized by having.

  Furthermore, the AD converter according to the present invention is a lower CDS circuit to which a lower binary value is input, and the first lower binary value is a lower binary value when the first input voltage is input to the comparator as an input voltage. A first register for storing a complement of the second and a second register for storing a second lower binary value which is a lower binary value when a second input voltage different from the first input voltage is input to the comparator as the input voltage; The complement of the first lower binary value stored in the first register and the second lower binary value stored in the second register are added, and a binary value indicating the addition result and a carry signal indicating carry are provided. It is preferable to further include a lower CDS circuit having an output adder.

  Furthermore, the AD converter according to the present invention counts the time from the input of the reference voltage to the change in the comparison result of the comparator with the upper clock signal having the same cycle as the plurality of clock signals to obtain the upper binary value. And the second input voltage is input to the comparator as the input voltage, and the second input voltage is input to the comparator as the upper binary value which is the upper binary value when the first input voltage is input to the comparator as the input voltage. It is preferable to further have an upper counter capable of adding the second upper binary value, which is the upper binary value at the same time.

  Furthermore, in the AD converter according to the present invention, the high-order counter is disposed in the front stage of the plurality of high-order flip flop circuits outputting the respective bits of the high-order binary value and the first high-order flip flop circuit of the plurality of high-order flip flop circuits. When the upper clock signal is input to one input terminal and the complement signal that advances the first stage of the plurality of upper flip-flop circuits by 1 is input to the other input terminal and the number of upper clock signals is counted, When the signal input to the first input terminal is output to the upper flip-flop circuit in the first stage and the complement of the first upper binary value is calculated, the signal input to the other input terminal is input to the first stage of the plurality of upper flip-flop circuits. Outputs adjacent bits of a plurality of high-order flip flop circuits Between the two upper flip-flop circuits, the output signal of the upper flip-flop circuit of the previous stage is input to one input terminal, and the complement signal for advancing the upper flip-flop circuit of the subsequent stage by one count is the other input When counting the number of upper clock signals input to the terminal, the signal input to one of the input terminals is output to the flip-flop circuit in the subsequent stage, and when calculating the complement of the first upper binary value, the other is selected. It is preferable to have a plurality of complement multiplexers that output a signal input to an input terminal to a flip-flop circuit in a subsequent stage.

  Furthermore, in the AD converter according to the present invention, the high-order counter is disposed in the front stage of the first high-order flip-flop circuit of the plurality of high-order flip-flop circuits, the high-order clock signal is input to one input terminal, and the carry signal is When counting the number of upper clock signals input to the other input terminal, the signal input to one of the input terminals is output to the first upper flip-flop circuit and the carry from the lower CDS circuit is added Preferably, the present invention further includes a carry multiplexer that outputs the signal input to the other input terminal to the upper flip-flop circuit of the first stage.

  Furthermore, in the AD converter according to the present invention, the output signals of the flip flop circuits of the first stage of the plurality of upper flip flop circuits are different in the upper signal from the first clock level to the first clock level through the state transition multiplexer. The state transition multiplexer changes in response to the transition to the two clock levels, and the state transition multiplexer counts the first upper binary value and the second upper binary value, and then the second clock level input from the other input terminal. It is preferable to output a signal.

  In another aspect, the AD converter according to the present invention has the same cycle as a comparator that compares the input voltage with a reference voltage of a ramp waveform whose voltage linearly changes with the passage of time, and each other A plurality of clock signals having edges different in phase and a transition signal transitioning from the first level to the second level according to a change in the comparison result of the comparator are input, the edges of the plurality of clock signals, the first level A binary value conversion circuit that generates a lower binary value based on the timing relationship between the transition signal and the second level, and a lower CDS circuit to which a lower binary value is input, the first input voltage being an input voltage A first register storing the complement of the first lower binary value, which is the lower binary value when input to the comparator, and a second input different from the first input voltage A second register storing a second lower binary value, which is a lower binary value when a voltage is input to the comparator as an input voltage, a complement of the first lower binary value stored in the first register, and a second register The low-order CDS circuit has a binary value indicating the addition result by adding the stored second low-order binary value, and an adder that outputs a carry signal indicating a carry.

  In another aspect, the present invention includes a pixel array unit in which a plurality of pixels performing photoelectric conversion according to the present invention are arranged in a matrix, and a pixel information reading unit that reads pixel information from the pixel array unit. The pixel information reading unit includes a comparator that compares the input voltage with a reference voltage of a ramp waveform whose voltage linearly changes with the passage of time, and a plurality of edges having the same cycle and different phases. A binary value conversion circuit to which a clock signal and a transition signal transitioning from a first level to a second level according to a change in comparison result of a comparator are input, which comprises edges of a plurality of clock signals and a first level A phase detection circuit that outputs a first binary value indicating a timing relationship of transition signals to a second level; a binary value storage circuit that stores a plurality of binary values; An encoder having a selection circuit which selects any one of a plurality of binary values based on one binary value, and the inverted bit obtained by inverting the least significant bit of the first binary value is the most significant bit, and An AD having a binary value conversion circuit for outputting a lower binary value in which any one of a plurality of binary values selected based on the first binary value is regarded as the least significant bit from the least significant bit of the most significant bit It is characterized by having a converter.

  In one embodiment, it is possible to provide a binary value conversion circuit that has a simple circuit configuration and can operate at high speed.

(A) is a circuit block diagram of a solid-state imaging device including an example of a binary value conversion circuit, and (b) is an internal circuit block diagram of an AD converter of the binary value conversion circuit shown in (a). (A) is a figure which shows the input signal of the comparator shown in FIG.1 (b), (b) is a figure which shows the output signal of the comparator shown in FIG.1 (b), (c) is FIG.1 (b) It is a figure showing the output signal of the AND element shown in. It is an internal circuit block diagram of the binary value conversion circuit comprised by TDC and encoder which are shown in FIG.1 (b). It is a figure explaining operation | movement of TDC shown in FIG. It is a figure which shows the relationship between the code | cord which deform | transformed the signal also called the thermocode input into the encoder shown in FIG. 3 (Hereafter, it is also called a deformation | transformation thermocode), and the low-order binary value output from an encoder. (A) is a figure which shows the deformation | transformation thermocode input into the encoder shown in FIG. 3, and the low-order binary value corresponding to a deformation | transformation thermocode, (b) is a figure which shows an example of the timing chart of the encoder shown in FIG. It is. (A) is a figure which shows the deformation | transformation thermocode input into the encoder shown in FIG. 3, and the low-order binary value corresponding to a deformation | transformation thermocode, (b) shows the other example of the timing chart of the encoder shown in FIG. FIG. 1 is a circuit block diagram of a solid-state imaging device including a binary value conversion circuit according to an embodiment. It is an internal circuit block diagram of AD converter shown in FIG. It is an internal circuit block diagram of the high-order counter shown in FIG. It is a figure which shows the state of the high-order counter in normal AD conversion operation | movement. FIG. 10 is a block diagram of an internal circuit of a binary value conversion circuit configured of a TDC and an encoder shown in FIG. 9; It is a figure which shows the relationship between the deformation | transformation thermocode input into the encoder shown in FIG. 9, and the low-order binary value output from an encoder. FIG. 10 is a block diagram of an internal circuit of a lower CDS circuit shown in FIG. 9; FIG. 10 is a diagram showing the operation of the lower CDS circuit shown in FIG. 9, (a) is a diagram showing a first lower state, (b) is a diagram showing a second lower state following the first lower state c) is a diagram showing a third lower state following the second lower state. It is a flowchart which shows CDS operation | movement of the high-order counter shown in FIG. It is a figure which shows CDS operation | movement of the high-order counter shown in FIG. 9, (a) shows a 1st high-order state, (b) shows the 2nd high-order state following a 1st high-order state. It is a figure which shows CDS operation | movement of the high-order counter shown in FIG. 9, (a) shows the 3rd high-order state following a 2nd high-order state, (b) shows the 4th high-order state following a 3rd high-order state. It is a figure which shows CDS operation | movement of the high-order counter shown in FIG. 9, (a) shows the 5th high-order state following a 4th high-order state, (b) shows the 6th high-order state following a 5th high-order state.

  The binary value conversion circuit and method thereof, an AD converter, and a solid-state imaging device according to the present invention will be described below with reference to the drawings. However, the technical scope of the present invention is not limited to those embodiments.

(Overview of Binary Value Conversion Circuit According to Embodiment)
The binary value conversion circuit according to the embodiment converts a first binary value output from TDC into a second binary value. Here, the binary conversion circuit according to the embodiment sets the inverted bit obtained by inverting the least significant bit of the first binary value as the most significant bit of the second binary value. The binary value conversion circuit according to the embodiment selects any one of the plurality of binary values stored in the binary value storage circuit based on the first binary value, and selects the most significant bit of the second binary value. It is assumed that the least significant bit is the least significant bit. The binary value conversion circuit according to the embodiment simplifies the circuit configuration by converting the first binary value output from TDC into a second binary value using a plurality of binary values stored in the binary value storage circuit. Can be

(Configuration and Function of Example of Binary Value Conversion Circuit)
Before describing the binary value conversion circuit according to the embodiment and the method thereof, an AD converter, and a solid-state imaging device, an example configuration and function of the binary value conversion circuit and problems in the binary value conversion circuit will be described.
FIG. 1A is a circuit block diagram of a solid-state imaging device including an example of a binary value conversion circuit, and FIG. 1B is an internal circuit block diagram of an AD converter as an example of the binary value conversion circuit.

  The solid-state imaging device 900 includes a pixel array unit 901, a vertical scanning unit 902, a horizontal scanning unit 903, a timing control unit 904, an AD conversion unit 905, a reference voltage generation unit 906, and a signal processing unit 907. . The vertical scanning unit 902, the horizontal scanning unit 903, the timing control unit 904, the AD conversion unit 905, the reference voltage generation unit 906, and the signal processing unit 907 constitute a pixel information reading unit for reading pixel information from the pixel array unit 901. .

  The pixel array unit 901 includes a plurality of solid-state imaging devices arranged in an array. The vertical scanning unit 902 sequentially selects the solid-state imaging devices disposed in the pixel array unit 901 for each row. The horizontal scanning unit 903 sequentially outputs, to the signal processing unit 907, the output signals of the solid-state imaging elements of the pixel array unit 901 that have been subjected to AD conversion collectively for each row in the AD conversion unit 905. The timing control unit 904 outputs a clock signal to the vertical scanning unit 902, the horizontal scanning unit 903, the AD conversion unit 905, and the like, and adjusts the timing of each circuit. The AD conversion unit 905 has a plurality of AD converters 910 arranged corresponding to the respective columns of solid-state imaging devices arranged in the pixel array unit 901. The reference voltage generation unit 906 generates a reference voltage which is a ramp waveform, and outputs the reference voltage to each of the plurality of AD converters 910. The signal processing unit 907 corrects vertical line defects and point defects, and performs parallel-serial conversion, compression, coding, addition, averaging, intermittent operation, etc., using the signal subjected to AD conversion by the AD conversion unit 905. Perform various digital signal processing.

  Each of the plurality of AD converters 910 includes a comparator 911, an AND element 912, an upper counter 913, a time-to-digital converter (TDC) 914, and an encoder 915. The TDC 914 and the encoder 915 constitute a binary value conversion circuit 916 that changes the timing information between the stop signal STOP and the clock signal CLK [0: 7] into a binary value.

  2 (a) is a diagram showing an input signal of the comparator 911; FIG. 2 (b) is a diagram showing an output signal of the comparator 911; and FIG. 2 (c) is a diagram showing an output signal of the AND element 912 is there.

The comparator 911 compares the input voltage V _ana which is an analog signal input from the solid-state imaging device disposed in the pixel array unit 901 to one input terminal with the reference voltage V _slop input from the reference voltage generation unit 906 And outputs the stop signal STOP according to the comparison result. The reference voltage V _slop is a ramp waveform that linearly decreases with the passage of time. The comparator 911 outputs the stop signal STOP as “1” while the reference voltage V _slop is larger than the input voltage V _ana . The comparator 911 _causes the stop signal STOP to transition from “1” to “0” when the reference voltage V _slop gradually decreases and the reference voltage V _slop becomes smaller than the input voltage V _ana .

In the AND element 912, the stop signal STOP is input from the comparator 911 to one input terminal, and the input clock signal CK _in is input from the timing control unit 904 to the other input terminal. While the stop signal STOP input from the comparator 911 to one input terminal is “1”, the AND element 912 outputs the clock signal CK to the upper counter 913 according to the input clock signal CK _in . The AND element 912 stops the output of the clock signal CK when the stop signal STOP input from the comparator 911 to one of the input terminals transitions to “0”.

  The upper counter 913 has an up / down counter circuit, and performs an up-counting operation in response to the rising edge of the clock signal CK input from the AND element 912. Further, the upper counter 913 performs up-counting operation for addition and down-cant operation for subtraction during correlated double sampling (CDS) operation. The upper counter 913 counts the number of input clock signals CK by performing counting operation according to the rising edge of the clock signal CK, and outputs the result as the upper binary value D [4: 11].

  FIG. 3 is an internal circuit block diagram of the binary value conversion circuit 916 configured by the TDC 914 and the encoder 915.

The TDC 914 is a flip flop in one example, and has a first latch 921 to an eighth latch 928. Clock signals CLK [0: 7] having the same cycle as the input clock signal CK _in and having a phase difference of 22.5 ° are provided to the D terminals of the first latch 921 to the eighth latch 928 as a timing control unit. It is input from 904. The D terminal of the first latch 921 receives the first clock signal CLK [0] having a phase of 0 °, and the D terminal of the second latch 922 has a second clock signal CLK [1] having a phase of 22.5 °. Is input. Thereafter, similarly, the D terminals of the third latch 923 to the seventh latch 927 receive the clock signal CLK [2: 6] having a phase difference of 22.5. The eighth clock signal CLK [7] having a phase of 157.5 ° is input to the D terminal of the eighth latch 928. The stop signal STOP is input to the clk terminals of the first latch 921 to the eighth latch 928. Each of the first latch 921 to the eighth latch 928 latches the value of the clock signal CLK [0: 7] when the stop signal STOP makes a falling transition, and outputs the latched value. For example, when the first clock signal CLK [0] input to the D terminal is “1”, the first latch 921 outputs “1” when the stop signal STOP input to the clk terminal transitions. Latch and output "1" from the Q terminal. The first latch 921 latches “0” when the stop signal STOP input to the clk terminal falls and the first clock signal CLK [0] input to the D terminal is “0”. Output "0" from the Q terminal.

FIG. 4 is a diagram for explaining the operation of the TDC 914. The upper part of FIG. 4 shows the input / output signal of the comparator 911 and the cycle of the input clock signal CK _in , and the lower part of FIG. 4 shows the TDC 914 when the stop signal STOP transits from “1” to “0”. The action is shown.

The TDC 914 is a code obtained by modifying a signal referred to as a thermocode according to an anteroposterior relationship between the edge of the clock signal CLK [0: 7] and the falling transition timing of the stop signal STOP (hereinafter referred to as a modified thermocode) Output). In the example shown in FIG. 4 which is a code (hereinafter also referred to as a modified thermo code) obtained by modifying a signal also referred to as a thermo code, the TDC 914 outputs an 8-bit TDC [0: 7] as “11111000”. Further, when the falling of the stop signal STOP is made transition at the time point shown by 0 / 16T _ck in FIG. 4, the TDC 914 outputs TDC [0: 7] as “10000000”.

  The encoder 915 includes a first multiplexer 931, a second multiplexer 932, a first logic unit 933, a second logic unit 934, and first to fourth flip-flops 935 to 938. The encoder 915 converts the TDC 914 8-bit TDC [0: 7] into a 4-bit lower binary value D [0: 3].

  FIG. 5 is a diagram showing the relationship between the modified thermocode input to the encoder 915 and the 4-bit lower binary value D [0: 3] output from the encoder 915. FIG. 6 is a diagram showing an operation of the encoder 915 when the least significant bit (hereinafter also referred to as LSB) TDC [0] of TDC [0: 7] of TDC is “1”. FIG. 6 (a) is a diagram showing the modified thermocode input to the encoder 915 and the lower binary value D [0: 3] corresponding to the modified thermocode, and FIG. 6 (b) is a timing chart of the encoder 915. FIG. FIG. 7 is a diagram showing an operation of the encoder 915 when the least significant bit TDC [0] of TDC [0: 7] of TDC is “0”. FIG. 7 (a) is a diagram showing a modified thermocode input to the encoder 915 and lower binary values D [0: 3] corresponding to the modified thermocode, and FIG. 7 (b) is a timing chart of the encoder 915. FIG.

The encoder 915 indicates that the TDC [0: 7] of the TDC 914 indicating “falling transition of the stop signal STOP at time 0 16 T _ck in FIG. 4” is “10000000”, the lower binary value D [0: 3]. ] Is output as "0000". The encoder 915 indicates that the TDC [0: 7] of the TDC 914 indicating that the stop signal STOP has a falling transition at the time point indicated by 1/16 T _ck in FIG. 4 is “11000000”, the lower binary value D [0: 3 ] Is output as "1000". Subsequently, the lower binary value D [0: 3] is increased each time the number of “1s” included in TDC [0: 7] increases, and when TDC [0: 7] is “11111111”, the lower binary value Output D [0: 3] as "1110".

Next, when the TDC [0: 7] of the TDC 914 indicating “falling transition of the stop signal STOP” at the time point indicated by 8/16 T _ck in FIG. 4 is “01111111”, the encoder 915 determines the lower binary value D [0. : 3] is output as "0001". The encoder 915 indicates the lower binary value D [0: 3] when TDC [0: 7] of the TDC 914 indicating “falling transition” of the stop signal STOP at the time point indicated by 9/16 T _ck in FIG. 4 is “00111111”. ] Is output as "1001". Subsequently, the lower binary value D [0: 3] is increased each time the number of “0s” included in TDC [0: 7] increases, and when TDC [0: 7] is “00000000”, the lower binary value Output D [0: 3] as "1111".

  As shown in FIG. 6, when TDC [0] which is the LSB of TDC [0: 7] of TDC 914 is “1”, the second logic unit 934 and the second multiplexer 932 of the encoder 915 control clock signal CNT_CLK. I will not let it pass. The fourth counter flip-flop 938 of the encoder 915 outputs the MSB D [3] of the lower binary value D [0: 3] as “0” because the control clock signal CNT_CLK is not input to the clk terminal. In addition, when TDC [0] which is the LSB of TDC [0: 7] of TDC 914 is “1”, the first logic unit 933 of the encoder 915 determines the ethics of the output signal of the first multiplexer 931 and the control clock signal CNT_CLK. Output the sum. The first counter flip-flop 935 to the third counter flip-flop 937 constitute a counter, and the ethical sum of the output signal of the first multiplexer 931 and the control clock signal CNT_CLK is input to the clk terminal.

  From this, when the LSB of TDC [0: 7] of the TDC 914 is “1”, the encoder 915 outputs the lower binary value D [3] as “0”. Also, the encoder 915 outputs a binary corresponding to the number obtained by counting the number of “1” s included in TDC [1: 7] as the lower binary value D [0: 2].

  As shown in FIG. 7, when TDC [0], which is the LSB of TDC [0: 7] of TDC 914, is “0”, the second logic unit 934 and the second multiplexer 932 of the encoder 915 generate the control clock signal CNT_CLK. Pass the pulse. When the control clock signal CNT_CLK is input through the second logic unit 934 and the second multiplexer 932, the fourth counter flip-flop 938 of the encoder 915 outputs the lower binary value D [3], which is the MSB, as "1". Do. When TDC [0] which is the LSB of TDC [0: 7] of TDC 914 is “0”, the first logic unit 933 of the encoder 915 outputs the inverted signal of the output signal of the first multiplexer 931 and the control clock signal CNT_CLK. Output the ethics sum with In the first counter flip-flop 935 to the third counter flip-flop 937, the ethical sum of the inverted signal of the output signal of the first multiplexer 931 and the control clock signal CNT_CLK is input to the clk terminal.

  From this, when the LSB of TDC [0: 7] of the TDC 914 is “0”, the encoder 915 outputs the lower binary value D [3] as “1”. Also, the encoder 915 outputs the binary corresponding to the number obtained by counting the number of “0s” included in TDC [1: 7] as the lower binary value D [0: 2].

  The AD converter 910 can increase the resolution without increasing the number of counts by the counter by generating the lower binary value D [0: 3] by the TDC 914 and the binary value conversion circuit.

(Problem of an example of binary value conversion circuit)
However, in the binary conversion circuit 916, the first multiplexer 931 needs to wire eight address lines EBSEL [0: 7] for selecting the respective outputs of the second latch 922 to the eighth latch 928 of the TDC 914. is there. Furthermore, the control line TDC_MSB_CTRL that controls the second multiplexer 932 needs to be wired. There is a problem that it is not easy to reduce the size of the AD converter 910 in order to secure a wiring area for wiring.

  Further, in the binary conversion circuit 916, the control clock signal CNT_CLK needs to be separately prepared separately from the input clock signal CK, so that the structure of the timing control unit 4 becomes complicated.

  In addition, in the binary conversion circuit 916, there is a problem that the structures of the first logic unit 933 and the second logic unit 934 become complicated. In the AD converter 910, the number of "0" s or "1" s included in the outputs of the second latch 922 to the eighth latch 928 of the TDC 914 is counted by a counter configured of the second latch 922 to the eighth latch 928. The logic of the first logic unit 933 is configured to prevent the counter composed of the first counter flip-flop 935 to the third counter flip-flop 937 from operating unintentionally in the operation of the first logic unit 933. The circuit is complicated. In addition, the logic circuit of the second logic unit 934 is complicated in order to prevent the output of the fourth counter flip-flop 938 from changing unintentionally in the operation of the second logic unit 934. Furthermore, since the binary conversion circuit 916 needs an operation to count the number of “0” or “1” included in the outputs of the second latch 922 to the eighth latch 928, the binary conversion operation is performed by a plurality of clocks. Over the period, the operating time becomes longer.

  Further, in the binary conversion circuit 916, there is a problem that transmission and reception of data between the binary conversion circuit 916 and the upper counter 913 becomes complicated when performing subtraction operation and the like required for the CDS operation. . For example, in the case of exchanging data for a subtraction operation or the like by the operations of the first logic unit 933 and the second logic unit 934, the first logic unit 933 and the second logic unit 934 become more complicated.

  The binary value conversion circuit according to the embodiment solves such a problem.

(Structure and Function of Binary Value Conversion Circuit, AD Converter, Solid-State Imaging Device According to Embodiment)
FIG. 8 is a circuit block diagram of a solid-state imaging device including the binary value conversion circuit according to the embodiment.

  The solid-state imaging device 100 includes a pixel array unit 1, a vertical scanning unit 2, a horizontal scanning unit 3, a timing control unit 4, an AD conversion unit 5, a reference voltage generation unit 6, and a signal processing unit 7. . The AD conversion unit 5 has a plurality of AD converters 10 arranged corresponding to respective columns of solid-state imaging devices arranged in the pixel array unit 1. The vertical scanning unit 2, the horizontal scanning unit 3, the timing control unit 4, the AD conversion unit 5, the reference voltage generation unit 6 and the signal processing unit 7 constitute a pixel information reading unit for reading pixel information from the pixel array unit 1. . The pixel array unit 1, the vertical scanning unit 2, the horizontal scanning unit 3, the timing control unit 4, the reference voltage generating unit 6 and the signal processing unit 7 include a pixel array unit 901, a vertical scanning unit 902, a horizontal scanning unit 903, a timing control unit The reference numeral 904 has the same configuration and function as the reference voltage generation unit 906 and the signal processing unit 907, and thus the detailed description is omitted here.

  FIG. 9 is a block diagram of an internal circuit of the AD converter 10.

  Each of the plurality of AD converters 10 includes a comparator 11, an AND element 12, an upper counter 13, a TDC 14, an encoder 15, a lower CDS circuit 16, and a control circuit 17. Each of the comparator 11 and the AND element 12 has the same configuration and function as the comparator 911 and the AND element 912, and thus the detailed description is omitted here. The TDC 14 and the encoder 15 constitute a binary value conversion circuit 18 which changes the timing information between the stop signal STOP and the clock signal CLK [0: 7] into a binary value.

  FIG. 10 is a block diagram of an internal circuit of the upper counter 13.

  The upper counter 13 includes a carry multiplexer 21, a state transition multiplexer 22, a first complement multiplexer 23 to a seventh complement multiplexer 29, and a first upper flip flop 31 to an eighth upper flip flop 38. The first selection signal SEL 0, the second selection signal SEL 1, the signal control signal CTRL_SIG, and the clear signal CNT_CLR are input from the control circuit 17. The clock signal CK is input from the AND element 12, and the carry signal Carry is input from the lower CDS circuit 16.

  The carry multiplexer 21 selectively outputs one of the output signal of the state transition multiplexer 22 and the carry signal Carry according to the first selection signal SEL0. The state transition multiplexer 22 selectively outputs one of the clock signal CK and the signal control signal CTRL_SIG according to the second selection signal SEL1. The first complement multiplexer 23 receives one of the first upper binary value D [4] and the signal control signal CTRL_SIG input from the first upper flip-flop 31 in response to the counter control signal CNT_CTRL as CK of the second upper flip-flop 32. Output to the terminal. Likewise, each of the second to seventh multiplexers 24 to 29 selectively selects one of the high-order binary output from the flip-flop in the previous stage and the signal control signal CTRL_SIG in response to the counter control signal CNT_CTRL. Output to the CK terminal of the subsequent flip-flop.

  The first upper flip-flop 31 outputs an inverted signal from the Q terminal in response to the rising transition of the signal input from the carry multiplexer 21 to the CK terminal. Each of the second upper flip-flop 32 to the eighth upper flip-flop 38 is an inverted signal from the Q terminal in response to the rising transition of the signal input from the first complement multiplexer 23 to the seventh complement multiplexer 29 to the CK terminal. Output When the clear signal CNT_CLR is input, the first upper flip-flop 31 to the eighth upper flip-flop 38 output “0” from the Q terminal.

  The upper counter 13 executes two operations, a normal AD conversion operation for converting an analog signal input from the pixel array unit 1 into a digital signal, and a CDS operation. The CDS operation of the upper counter 13 will be described in detail later, so only the normal AD conversion operation will be described here.

(Normal AD conversion operation of upper counter 13)
FIG. 11 is a diagram showing the state of the upper counter 13 in a normal AD conversion operation.

  In the normal AD conversion operation of the upper counter 13, the upper counter 13 is set by the control circuit 17 to count the clock signal CK. That is, the state transition multiplexer 22 outputs the clock signal CK to the carry multiplexer 21, and the carry multiplexer 21 outputs the clock signal CK input from the state transition multiplexer 22 to the CK terminal of the first upper flip-flop 31. Each of the first complement multiplexer 23 to the seventh complement multiplexer 29 outputs the signal from the Q terminal of the front stage flip flop to the CK terminal of the rear stage flip flop. The upper counter 13 functions as a counter circuit that counts the number of input clock signals CK.

  FIG. 12 is a block diagram of an internal circuit of the binary value conversion circuit 18 configured by the TDC 14 and the encoder 15.

  The TDC 14 has a first lower latch 41 to an eighth lower latch 48. The configuration and function of each of the first lower latch 41 to the eighth lower latch 48 are the same as those of the first latch 921 to the eighth latch 928, and thus the detailed description thereof is omitted here.

  The TDC 14 receives a plurality of clock signals CLK [0: 7] and a stop signal STOP which is a transition signal for transitioning from the first level to the second level. The TDC 14 outputs TDC [0: 7] indicating the sequential relationship between the edge of the clock signal CLK [0: 7] and the timing at which the stop signal STOP transitions from the first level to the second level. TDC [0: 7] is an 8-bit binary in which a group of output signals output from each of the first lower latch 41 to the eighth lower latch 48 are arranged in the order of the phases of clock signals CLK [0: 7]. It is a value.

  The encoder 15 includes a first exclusive OR element 511 to an eighth exclusive OR element 518, a first inverting element 521 to an eighth inverting element 528, a first lower binary value storage unit 53, and a second lower binary A value storage unit 54 and a third lower binary value storage unit 55 are provided. In addition, the encoder 15 further includes a fourth lower binary value inverting element 56. The first lower binary value storage unit 53 includes an eleventh lower binary value storage element 531 to an eighteenth lower binary value storage element 538. The second lower binary value storage unit 54 includes a 21st lower binary value storage element 541 to a 28th lower binary value storage element 548. The third lower binary value storage unit 55 includes a 31st lower binary value storage element 551 to a 38th lower binary value storage element 558.

  The first exclusive OR element 511 receives the output signals from the Q terminals of the first lower latch 41 and the second lower latch 42, and outputs “0” when both output signals match, Output "1" when the output signal is different. The second exclusive OR element 512 receives an output signal from the Q terminal of the second lower latch 42 and the third lower latch 43, and outputs “0” when both output signals match, Output "1" when the output signal is different. Likewise, the output signals of two adjacent lower latches are input to the third exclusive OR element 513 to the seventh exclusive OR element 517, and “0” is output when both output signals match. It outputs “1” when both output signals are different. The eighth exclusive OR element 518 receives an output signal from the Q terminal of the first lower latch 41 and the eighth lower latch 48, and outputs “0” when both output signals match. When both output signals are different, "1" is output.

  In each of the first exclusive OR element 51 1 to the seventh exclusive OR element 517, when the output signals of two adjacent lower latches transit from “0” to “1” or “1” to “0” Output "1" to The eighth exclusive OR element 518 outputs “0” when the output signals of the first lower latch 41 and the eighth lower latch 48 match “0” or “1”.

  Each of the first inversion element 521 to the eighth inversion element 528 outputs an inversion signal of the output signal of each of the first exclusive OR element 511 to the eighth exclusive OR element 518.

  Each of the 11th lower binary value storage element 531, the 13th lower binary value storage element 533, the 15th lower binary value storage element 535, and the 17th lower binary value storage element 537 is an nMOS transistor whose source is grounded. On the other hand, each of the 12th lower binary value storage element 532, the 14th lower binary value storage element 534, the 16th lower binary value storage element 536 and the 18th lower binary value storage element 538 has a source connected to the power supply voltage. It is a transistor. The gate of the eleventh lower binary value storage element 531 is connected to the output terminal of the first exclusive OR element 511, and the gate of the twelfth lower binary value storage element 532 is connected to the output terminal of the second inverting element 522. The gate of the thirteenth lower binary value storage element 533 is connected to the output terminal of the third exclusive OR element 513, and the gate of the fourteenth lower binary value storage element 534 is connected to the output terminal of the fourth inverting element 524. The gate of the fifteenth lower binary value storage element 535 is connected to the output terminal of the fifth exclusive OR element 515, and the gate of the sixteenth lower binary value storage element 536 is connected to the output terminal of the sixth inverting element 526. The gate of the seventeenth lower binary value storage element 537 is connected to the output terminal of the seventh exclusive OR element 517, and the gate of the eighteenth lower binary value storage element 538 is connected to the output terminal of the eighth inversion element 528. The drains of the eleventh lower binary value storage element 531 to the eighteenth lower binary value storage element 538 are connected together to output the lower binary value D [0].

  Each of the 21st lower binary value storage element 541, the 22nd lower binary value storage element 542, the 25th lower binary value storage element 545, and the 26th lower binary value storage element 546 is an nMOS transistor whose source is grounded. On the other hand, each of the 23rd lower binary value storage element 543, the 24th lower binary value storage element 544, the 27th lower binary value storage element 547 and the 28th lower binary value storage element 548 is a pMOS whose source is connected to the power supply voltage It is a transistor. The gate of the 21st lower binary value storage element 541 is connected to the output terminal of the first exclusive OR element 511, and the gate of the 22nd lower binary value storage element 542 is connected to the output terminal of the second exclusive OR element 512. Be done. The gate of the twenty third lower binary value storage element 543 is connected to the output terminal of the third inversion element 523, and the gate of the twenty fourth lower binary value storage element 544 is connected to the output terminal of the fourth inversion element 524. The gate of the 25th lower binary value storage element 545 is connected to the output terminal of the fifth exclusive OR element 515, and the gate of the 26th lower binary value storage element 546 is connected to the output terminal of the sixth exclusive OR element 516 Be done. The gate of the twenty seventh lower binary value storage element 547 is connected to the output terminal of the output terminal of the seventh inversion element 527, and the gate of the twenty eighth lower binary value storage element 548 is connected to the output terminal of the eighth inversion element 528. The drains of the 21st lower binary value storage element 541 to the 28th lower binary value storage element 548 are connected together to output the lower binary value D [1].

  Each of the 31st lower binary value storage element 551, the 32nd lower binary value storage element 552, the 33rd lower binary value storage element 553 and the 34th lower binary value storage element 554 is an nMOS transistor whose source is grounded. On the other hand, each of the 35th lower binary value storage element 555, the 36th lower binary value storage element 556, the 37th lower binary value storage element 557 and the 38th lower binary value storage element 558 is a pMOS in which the source is connected to the power supply voltage. It is a transistor. The gate of the 31st lower binary value storage element 551 is connected to the output terminal of the first exclusive OR element 511, and the gate of the 32nd lower binary value storage element 552 is connected to the output terminal of the second exclusive OR element 512. Be done. The gate of the 33rd lower binary value storage element 553 is connected to the output terminal of the third exclusive OR element 513, and the gate of the 34th lower binary value storage element 554 is connected to the output terminal of the fourth exclusive OR element 514. Be done. The gate of the 35th lower binary value storage element 555 is connected to the output terminal of the fifth inversion element 525, and the gate of the 36th lower binary value storage element 556 is connected to the output terminal of the sixth inversion element 526. The gate of the 37th lower binary value storage element 557 is connected to the output terminal of the output terminal of the seventh inversion element 527, and the gate of the 38th lower binary value storage element 558 is connected to the output terminal of the eighth inversion element 528. The drains of the 31st lower binary value storage element 551 to the 38th lower binary value storage element 558 are connected together to output the lower binary value D [2].

  The first exclusive OR element 511 to the eighth exclusive OR element 518 and the first inverting element 521 to the eighth inverting element 528 have a plurality of binary values D based on TDC [0: 7] input from the TDC 14 A selection circuit is configured to select any one of [0: 2]. The first lower binary value storage unit 53, the second lower binary value storage unit 54, and the third lower binary value storage unit 55 constitute binary value storage circuits for storing a plurality of 3-bit binary values D [0: 2]. Do. Each of the first exclusive OR element 511 to the seventh exclusive OR element 517 and the first inverting element 521 to the seventh inverting element 527 receives two adjacent bits of TDC [0: 7] and is input. Select one of the binary values when the two bits being processed differ. The eighth exclusive OR element 518 and the eighth inverting element 528 receive the binary value D when the most significant bit and the least significant bit of TDC [0: 7] are input and the two input bits match. Select the other one of [0: 2].

  FIG. 13 is a diagram showing the relationship between the modified thermocode input to the encoder 15 and the 4-bit lower binary value D [0: 3] output from the encoder 15.

  The output signal of the first exclusive OR element 511 is “1” when TDC [0: 7] is “10000000” and “01111111”, and the lower binary value D [0: 2] excluding the MSB is “000”. "become. The output signal of the second exclusive OR element 512 is “1” when TDC [0: 7] is “11000000” and “00111111”, and the lower binary value D [0: 2] excluding the MSB is “100”. "become. Likewise, the output signals of the third exclusive OR element 513 to the seventh exclusive OR element 517 are "1" in accordance with the transition timing of TDC [0: 7], and the lower binary value D [ 0: 2] changes in accordance with the timing of transition of TDC [0: 7]. The lower binary value D [0: 2] changes from “000” to “011” according to the first exclusive OR element 511 to the seventh exclusive OR element 517 outputting “1”. Also, the output signal of the eighth exclusive OR element 518 is “0” when TDC [0: 7] is “11111111” and “00000000”, and the lower binary value D [0: 2] excluding the MSB is It will be "111".

  The encoder 15 has a lower binary value indicating that the lower binary value D [0: 2] indicates that the stop signal STOP transitions from “0” to “1”, which indicates when the stop signal STOP transitions from “1” to “0”. It utilizes that the values D [0: 2] are identical except for the MSB. For example, the first exclusive OR element 511 outputs “1” only when TDC [0] and TDC [1] are different, and outputs “0” otherwise. Similarly, each of the second exclusive OR element 512 to the seventh exclusive OR element 517 is “1” only when TDC [0: 7] input to the two connected latches is different. Outputs and outputs "0" otherwise. Also, the eighth exclusive OR element 518 outputs “0” only when TDC [0] and TDC [8] match.

  In the encoder 15, the fourth lower binary value D [3] which is the MSB of the lower binary value uses a bit / TDC [0] obtained by inverting TDC [0] by the fourth lower binary value inverting element 56.

(Function and effect of binary value conversion circuit 18)
The binary conversion circuit 18 generates the lower binary by the inverted signal of the output signal of the first lower latch 41 and the binary value selected according to any two output signals of the first lower latch 41 to the eighth lower latch 48. Define the value D [0: 3]. The lower binary value D [3] is an output signal of the fourth lower binary value inverting element 56, and the lower binary value D [0: 2] is a ROM formed of MOS transistors. Therefore, the encoder 15 has a circuit configuration It will be very easy. Thus, the binary conversion circuit 18 can be reduced in size and can perform binary conversion with a single clock signal.

  Also, since the binary conversion circuit 18 does not need a counter circuit for converting binary values, it can convert binary values in a single clock cycle. Further, the binary value conversion circuit 18 reads the values stored in the first lower binary value storage unit 53 to the third lower binary value storage unit 55 of the ROM structure to determine the lower binary value D [0: 2]. The operation is possible with a simple control circuit.

  Further, the binary conversion circuit 18 determines the lower binary value D [0: 2] according to the transition timing of the stop signal STOP detected by the first exclusive OR element 511 to the seventh exclusive OR element 517. . Compared with the case where the binary conversion circuit 18 arranges the memory element to determine the lower binary value D [0: 2] according to the number of “1” and “0” included in TDC [0: 7]. Thus, the number of storage elements can be halved. That is, in the binary value conversion circuit 18, when only TDC [0], which is the LSB, differs between two TDC [0: 7], only D [3] in which the converted D [0: 3] is the MSB Differently, the number of memory elements is halved by utilizing the fact that D [0: 2] are identical.

  Further, in the binary conversion circuit 18, while the lower binary value D [0: 2] is output from the encoder 15, a path is formed in which a through current flows from the power supply voltage to the ground by turning on the nMOS transistor and the pMOS transistor simultaneously. It will not be done. In the binary conversion circuit 18, since no through current flows when outputting the lower binary value D [0: 2], power consumption can be suppressed low.

(Configuration, Function, and Operation of Lower CDS Circuit 16)
FIG. 14 is a block diagram of an internal circuit of the lower CDS circuit 16.

  The lower CDS circuit 16 has an output selection circuit 61, a reset register 62, a signal register 63, and an adder 64. The output selection circuit 61 outputs the lower binary value D [0: 3] input from the encoder 15 to either the reset register 62 or the signal register 63 in response to the selection signal select input from the control circuit 17. The reset register 62 stores the complement of the lower binary value D [0: 3] indicating the reset value input through the output selection circuit 61. In the present specification, "complement" refers to so-called one's complement obtained by inverting a binary value unless otherwise noted. The signal register 63 stores lower binary values D [0: 3] indicating the signal values inputted through the output selection circuit 61. When the reset signal reset is input from the control circuit 17, the reset register 62 and the signal register 63 set the stored value to “0”. The adder 64 adds the value stored in the reset register 62 and the value stored in the signal register 63 and outputs the lower binary value D [0: 3] subjected to the CDS operation and the carry signal Carry. .

  FIG. 15 shows the operation of the lower CDS circuit 16. FIG. 15 (a) shows a first lower state, and FIG. 15 (b) shows a second lower state following the first lower state. It is a figure and FIG.15 (c) is a figure which shows the 3rd lower state following a 2nd lower state.

  First, as shown in FIG. 15A, the lower CDS circuit 16 sets the values stored in the reset register 62 and the signal register 63 to “0” in response to the reset signal reset being input from the control circuit 17. Make it Next, as shown in FIG. 15B, the lower CDS circuit 16 selects the reset register 62 from the control circuit 17 while the lower binary value D [0: 3] indicating reset is input from the encoder 15. The select signal select is input. The lower CDS circuit 16 stores the complement of the lower binary value D [0: 3] indicating the reset input from the encoder 15 in the reset register 62. Next, as shown in FIG. 15C, the lower CDS circuit 16 selects the signal register 63 from the control circuit 17 while the lower binary value D [0: 3] indicating a signal is input from the encoder 15. The select signal select is input. The lower CDS circuit 16 stores the lower binary value D [0: 3] indicating the signal input from the encoder 15 in the reset register 62. The adder 64 adds the complement of the lower binary value D [0: 3] indicating reset stored in the reset register 62 and the lower binary value D [0: 3] indicating a signal stored in the signal register 63. Do. The adder 64 adds the complement of the lower binary value D [0: 3] indicating reset and the lower binary value D [0: 3] indicating the signal to generate the lower binary value D [0: 3] indicating the signal. ] Subtracts the lower binary value D [0: 3] indicating reset. The adder 64 is a lower binary value D [0:] on which the CDS operation is performed, which is an added value of the complement of the lower binary value D [0: 3] indicating reset and the lower binary value D [0: 3] indicating a signal. 3], and outputs the carry signal Carry to the upper counter 13.

(CDS operation of upper counter 13)
FIG. 16 is a flowchart showing the CDS operation of the upper counter 13. FIG. 17 shows the CDS operation of the upper counter 13. FIG. 17 (a) shows a first upper state, and FIG. 17 (b) shows a second upper state following the first upper state. FIG. 18 shows the CDS operation of the upper counter 13. FIG. 18 (a) shows the third upper state following the second upper state, and FIG. 18 (b) shows the fourth upper state following the third upper state. Indicates FIG. 19 shows the CDS operation of the upper counter 13. FIG. 19 (a) shows the fifth upper state following the fourth upper state, and FIG. 19 (b) shows the sixth upper state following the fifth upper state. Indicates

  First, before the CDS operation, the first upper flip-flop 31 to the eighth upper flip-flop 38 receive the clear signal CNT_CLR, and the first upper flip-flop 31 to the eighth upper flip-flop 38 are reset. Next, the upper counter 13 counts the upper binary value D [4:11] indicating reset (S101). At this time, the control circuit 17 sets the upper counter 13 so as to count the clock signal CK as shown in FIG. 17 (a). The case of setting the upper counter 13 so as to count the clock signal CK has already been described with reference to FIG. 11, so the detailed description will be omitted here.

  Next, the control circuit 17 causes the signal control signal CTRL_SIG to transition from "0" to "1" (S102). At this time, as shown in FIG. 17B, the control circuit 17 controls the state transition multiplexer 22 to select the signal control signal CTRL_SIG, and changes the signal control signal CTRL_SIG from “0” to “1”. Let When the signal control signal CTRL_SIG transits from “0” to “1”, the signal input to the CK terminal of the first upper flip-flop 31 rises and transits, and the upper counter 13 advances its count operation by one. Also, the CK terminal of the upper flip-flop 31 is in a state in which "1" is input. When “1” is input to the CK terminal of the upper flip-flop 31, even if a signal that transitions from “0” to “1” is input to the CK terminal via the carry multiplexer 21, the upper The flip flop 31 does not count. Therefore, the upper counter 13 can prevent the occurrence of a malfunction due to an unexpected transition of the signal control signal CTRL_SIG by causing the signal control signal CTRL_SIG to transition from “0” to “1”.

  Next, the control circuit 17 complements the upper binary value D [4:11] indicating the counted reset (S103). At this time, as shown in FIG. 18A, the control circuit 17 controls the state transition multiplexer 22 and the first complement multiplexer 23 to the seventh complement multiplexer 29 so as to select the signal control signal CTRL_SIG. Then, the control circuit 17 causes the signal control signal CTRL_SIG to transition from “0” to “1”. The rising transition of the signal control signal CTRL_SIG causes a rising transition of a signal input to the CK terminal of the first upper flip-flop 31 to the eighth upper flip-flop 38, and the first upper flip-flop 31 to the eighth upper flip-flop 38 The output signal is inverted. Since the output signals of the first upper flip-flop 31 to the eighth upper flip-flop 38 are inverted, the upper counter 13 stores the complement of the upper binary value D [4: 11] indicating reset.

  Next, the upper counter 13 counts the upper binary value D [4:11] indicating a signal (S104). At this time, the control circuit 17 sets the upper counter 13 so as to count the clock signal CK, as shown in FIG. 18 (b). The case of setting the upper counter 13 so as to count the clock signal CK has already been described with reference to FIG. 11, so the detailed description will be omitted here.

  By the operation of S104, the upper counter 13 outputs the upper binary value D indicating a signal to the first upper flip flop 31 to the eighth upper flip flop 38 in which the complement of the upper binary value D [4: 11] indicating reset is stored. Count [4:11]. Thus, the upper counter 13 performs an operation of subtracting the upper binary value D [4:11] indicating reset from the upper binary value D [4:11] indicating a signal.

  Next, the control circuit 17 causes the signal control signal CTRL_SIG to transition from "0" to "1" (S105). At this time, as shown in FIG. 19A, the control circuit 17 controls the state transition multiplexer 22 to select the signal control signal CTRL_SIG, and changes the signal control signal CTRL_SIG from “0” to “1”. Let The case where the upper counter 13 is set to cause the signal control signal CTRL_SIG to transition from “0” to “1” has already been described with reference to FIG. 17B, and thus detailed description will be omitted here. Do.

  Then, the control circuit 17 adds the carry signal Carry (S105). At this time, the control circuit 17 controls the carry multiplexer 21 so as to select the carry signal Carry, as shown in FIG. 19B, and the carry terminal of the upper counter 13 and the digit of the lower CDS circuit 16 Connect with the raising terminal. When the carry signal Carry of the lower CDS circuit 16 is “1”, when the upper counter 13 and the lower CDS circuit 16 are connected, the signal is input to the CK terminal of the first upper flip-flop 31 via the carry multiplexer 21. Signal to rise.

  The CDS operation of the lower CDS circuit 16 and the upper counter 13 has been described above. In the CDS operation of the AD converter 10, offset is performed by using the one's complement of the lower binary value D [0: 3] and the upper binary value D [4:11] indicating reset, and the counting operation in S102 and S103. Will occur. The offset generated in the CDS operation of the AD converter 10 is appropriately processed by the signal processing unit 7.

(Operation effect by CDS operation of AD converter 10)
In the AD converter 10, since the carry signal Carry output from the adder 64 of the lower CDS circuit 16 is used as a clock signal of the upper counter, a simple circuit such as a register and an adder generates a digit of the CDS operation of the lower counter. A carry signal can be generated to indicate a rise. In addition, since the lower CDS circuit 16 does not require control of the up counter, the down counter, etc., the control of the CDS operation is easy. Further, since the lower CDS circuit 16 can generate the carry signal with the adder that can be realized by the combinational circuit, it can generate the carry signal with a single clock cycle.

  Further, in the AD converter 10, the upper counter 13 complements the upper binary value D [4: 11] indicating the counted reset using the state transition multiplexer 22 and the first complement multiplexer 23 to the seventh complement multiplexer 29. Make it Next, the upper counter 13 counts the upper binary value D [4:11] indicating the signal. In the AD converter 10, the CDS operation is realized only by the up counter without using the down counter by using the upper binary value D [4: 11] indicating the reset in complement.

(Modification of AD converter according to the embodiment)
In the AD converter 10, the input clock signal CK _in is input from the timing control unit 4 separately from the first clock signal CLK [0], but the input clock signal CK _in is identical to the first clock signal CLK [0]. The clock signal of may be used. By using the same clock signal is inputted to the first clock signal CLK [0] and the input clock signal CK _in, synchronization between the upper counter 13 and TDC14 is facilitated. In the AD converter 10, the clock signal CK input to the upper counter 13 is generated by the AND element 12, but the clock signal CK input to the upper counter 13 is the output of the first lower latch 41 of the TDC 14. The signal may be shaped. By using the output signal of the first lower latch 41 as the clock signal CK, the AND element 12 can be omitted.

DESCRIPTION OF SYMBOLS 1 pixel array part 5 AD conversion part 6 reference voltage generation part 10 AD converter 11 comparator 13 high-order counter 14 TDC (phase detection circuit)
15 encoder 16 lower CDS circuit 17 control circuit 18 binary value conversion circuit

Claims (12)

A plurality of clock signals having the same period and having edges out of phase with each other, and a transition signal transitioning from a first level to a second level are input, the edges of the plurality of clock signals, and the first level A phase detection circuit that outputs a first binary value indicating the timing relationship between the transition of the transition signal to the second level and the second level;
An encoder having a binary value storage circuit storing a plurality of binary values, and a selection circuit selecting any one of the plurality of binary values based on the first binary value,
The inverted bit obtained by inverting the least significant bit of the first binary value is the most significant bit, and any one of the plurality of binary values selected based on the first binary value is one bit of the most significant bit A binary value conversion circuit characterized by outputting a second binary value from the lower bits to the least significant bit. Each of the phase detection circuits is an output signal of 1 bit according to an anteroposterior relationship between any one edge of the plurality of clock signals and the transition timing of the transition signal from the first level to the second level. It has 2n latch circuits from the 1st latch circuit to 2n latch circuits to output, and the output signal of the group which each of said 2n latch circuits outputs is the order order of the phase of said clock signal which each corresponds , And outputs as the 2n bits of the first binary value,
The selection circuit has 2n selection elements,
Among the 2n selection elements, (2n-1) of the plurality of n bits are input when two adjacent bits of the first binary value are input and the two input bits are different. Select any one of the binary values,
The other one of the 2n timing detection signal elements receives the most significant bit and the least significant bit of the first binary value, and the plurality of n bits when the two inputted bits match. The binary value conversion circuit according to claim 1, wherein one other binary value is selected. The binary value storage circuit is
When the least significant bit of the first binary value is “1”, n bits indicating the number of “1” s included in the 1-bit upper bit to the most significant bit of the least significant bit of the first binary value Outputting a binary value according to the selection of the selection circuit,
When the least significant bit of the first binary value is “0”, n bits indicating the number of “0” s included in the 1-bit upper bit to the most significant bit of the least significant bit of the first binary value The binary value conversion circuit according to claim 2, wherein a binary value is output according to the selection of the selection circuit. A plurality of clock signals having the same period and having edges out of phase with each other, and a transition signal transitioning from a first level to a second level are input, the edges of the plurality of clock signals, and the first level Generating a first binary value indicating the timing relationship of the transition of the transition signal to the second level,
Selecting one of a plurality of binary values stored in the binary value storage circuit based on the first binary value;
The inverted bit obtained by inverting the least significant bit of the first binary value is the most significant bit, and any one of the plurality of binary values selected based on the first binary value is one bit of the most significant bit Output a second binary value with the least significant bit as the least significant bit,
A binary value conversion method characterized in that it includes. A comparator that compares an input voltage with a reference voltage whose voltage linearly changes with the passage of time;
Binary value conversion in which a plurality of clock signals having the same period and having edges different from each other and a transition signal transitioning from the first level to the second level according to a change in the comparison result of the comparator are input A circuit,
A phase detection circuit that outputs a first binary value indicating an anteroposterior relationship between the edges of the plurality of clock signals and the timing at which the transition signal transitions from the first level to the second level;
An encoder having a binary value storage circuit storing a plurality of binary values, and a selection circuit selecting any one of the plurality of binary values based on the first binary value,
The inverted bit obtained by inverting the least significant bit of the first binary value is the most significant bit, and any one of the plurality of binary values selected based on the first binary value is one bit of the most significant bit A binary value conversion circuit that outputs a lower binary value from the lower bit to the least significant bit;
AD converter characterized by having. A lower CDS circuit to which the lower binary value is input,
A first register storing a complement of a first lower binary value which is the lower binary value when a first input voltage is input to the comparator as the input voltage;
A second register that stores a second lower binary value that is the lower binary value when a second input voltage different from the first input voltage is input to the comparator as the input voltage;
The complement of the first lower binary value stored in the first register and the second lower binary value stored in the second register are added to indicate a binary value indicating the result of addition and carry. The AD converter according to claim 5, further comprising a lower CDS circuit having an adder for outputting a carry signal. The upper counter generates an upper binary value by counting an upper clock signal having the same cycle as that of the plurality of clock signals, from the time when the reference voltage is input until the comparison result of the comparator changes. ,
When the complement of the first upper binary value, which is the upper binary value when the first input voltage is input to the comparator as the input voltage, and the second input voltage is input to the comparator as the input voltage The AD converter according to claim 6, further comprising an upper counter capable of adding the second upper binary value which is the upper binary value of. The upper counter is
A plurality of upper flip-flop circuits outputting respective bits of the upper binary value;
The complement signal is arranged in the front stage of the first upper flip-flop circuit of the plurality of upper flip-flop circuits, the upper clock signal is input to one input terminal, and advances the first stage of the plurality of upper flip-flop circuits by one count. When counting the number of upper clock signals input to the other input terminal, the signal input to the one input terminal is output to the upper stage flip-flop circuit of the first stage, and the complement of the first upper binary value is calculated A state transition multiplexer that outputs the signal input to the other input terminal to the first stage of the plurality of upper flip-flop circuits;
It is disposed between any two upper flip-flop circuits that respectively output adjacent bits of a plurality of upper flip-flop circuits, and the output signal of the upper flip-flop circuit of the previous stage is input to one input terminal. When the complement signal for advancing the flip flop circuit by one count is input to the other input terminal and the number of the upper clock signals is counted, the signal input to the one input terminal is output to the flip flop circuit in the subsequent stage 8. The AD according to claim 7, further comprising: a plurality of complement multiplexers for outputting the signal input to the other input terminal to the flip-flop circuit in the subsequent stage when calculating the complement of the first upper binary value. converter. The upper counter is
The high-order clock signal is input to one input terminal and the carry signal is input to the other input terminal, and the high-order clock signal is arranged in the front stage of the first high-order flip-flop circuit of the plurality of high-order flip flop circuits. When counting the number of signals, the signal input to the one input terminal is output to the upper stage flip-flop circuit of the first stage, and when adding the carry from the lower CDS circuit, the signal is input to the other input terminal. 9. The AD converter according to claim 8 , further comprising a carry multiplexer for outputting the input signal to the upper stage flip flop circuit of the first stage. The output signal of the first flip-flop circuit of said plurality of upper flip-flop circuit, the upper clock signal through the state transition multiplexer is changed to the second clock level different from the first clock level from the first clock level Change according to things,
The state transition multiplexer outputs the signal of the second clock level input from the other input terminal after the upper counter counts the first upper binary value and the second upper binary value. AD converter as described in 8. A comparator that compares the input voltage with a reference voltage of a ramp waveform whose voltage linearly changes with the passage of time;
A plurality of clock signals having the same period and having edges that are out of phase with each other, and a transition signal that transitions from the first level to the second level according to a change in the comparison result of the comparator are input. A binary value conversion circuit that generates a lower binary value based on an anteroposterior relationship between an edge of a clock signal and timing of transition of the transition signal from the first level to the second level;
A lower CDS circuit to which the lower binary value is input,
A first register storing a complement of a first lower binary value which is the lower binary value when a first input voltage is input to the comparator as the input voltage;
A second register that stores a second lower binary value that is the lower binary value when a second input voltage different from the first input voltage is input to the comparator as the input voltage;
The complement of the first lower binary value stored in the first register and the second lower binary value stored in the second register are added to indicate a binary value indicating the result of addition and carry. A lower CDS circuit having an adder for outputting a carry signal;
AD converter characterized by having. A pixel array unit in which a plurality of pixels for performing photoelectric conversion are arranged in a matrix;
A pixel information reading unit for reading pixel information from the pixel array unit;
The pixel information reading unit
A comparator that compares the input voltage with a reference voltage of a ramp waveform whose voltage linearly changes with the passage of time;
Binary value conversion in which a plurality of clock signals having the same period and having edges different from each other and a transition signal transitioning from the first level to the second level according to a change in the comparison result of the comparator are input A circuit,
A phase detection circuit that outputs a first binary value indicating an anteroposterior relationship between the edges of the plurality of clock signals and the timing at which the transition signal transitions from the first level to the second level;
An encoder having a binary value storage circuit storing a plurality of binary values, and a selection circuit selecting any one of the plurality of binary values based on the first binary value,
The inverted bit obtained by inverting the least significant bit of the first binary value is the most significant bit, and any one of the plurality of binary values selected based on the first binary value is one bit of the most significant bit What is claimed is: 1. A solid-state imaging device comprising: an AD converter including: a binary value conversion circuit that outputs a lower binary value from lower bits to the least significant bit.

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