JP6513535B2 - Self injection phase locked loop - Google Patents

Description

  The present invention relates to a self injection phase lock circuit that performs self injection so as to provide negative feedback in the phase lock circuit.

  Heretofore, there has been known an injection lock in which the oscillator is subjected to a perturbation very close to the oscillation frequency and synchronized to the applied signal, and in the integrated circuit, there is a study of Adler et al.

  In recent years, an oscillation circuit using self-injection has also been studied, and self-injection locking is also performed in a phase locked circuit (PLL: Phase Locked Loop) (see Non-Patent Document 2). ). In the self injection locking described in the non-patent document 2, the oscillation signal from the oscillator is delayed by a delay cable, and the feedback phase is adjusted by a phase shifter and then injected into the oscillator.

R. Adler, "A Study of Locking Phenomena in Oscillators," Proc. IEEE, vol. 61, pp. 1380-1385, Oct. 1973 Tsuneji Tsutsumi, Masato Tsuru, Eiji Taniguchi, “PLL-IC with self-injection locked VCO with SiGe BiCMOS,” 2012 Electronics Society Conference of the Institute of Electronics, Information and Communication Engineers, C-2-2, p.28, 2012

  However, in the self injection locking described in the non-patent document 2, it is necessary to manually adjust the phase by the phase shifter. Therefore, it is necessary to adjust the phase shifter for each phase synchronization circuit, or to adjust the phase shifter every time the oscillation frequency is changed, and there is a problem that the work for the adjustment is complicated. . In addition, when the adjustment is inappropriate, for example, when injection by positive feedback is performed, there is a problem that the effect of injection can not be obtained.

  The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a self-injection phase lock circuit capable of automatically realizing self-injection with an appropriate phase.

In order to achieve the above object, the self injection phase synchronization circuit according to the present invention compares the phase and frequency of the oscillation output signal and the reference signal with a voltage controlled oscillator that outputs an oscillation output signal of the oscillation frequency corresponding to the control voltage. A phase frequency comparator that outputs a comparison result signal indicating a comparison result, a voltage generator that generates a control voltage according to the comparison result signal and outputs the control voltage to a voltage controlled oscillator, and an oscillation output signal with variable delay time The variable delay device for outputting a delayed injection signal, and a delay controller for controlling the delay time of the variable delay device, the injection signal is injected into the voltage controlled oscillator, and the delay controller controls the voltage controlled oscillator. The delay time is controlled such that the injected injection signal is negatively fed back.
With such a configuration, the injection of the injection signal into the voltage control oscillator by negative feedback can be realized automatically by the delay controller, and the work of the phase adjustment by the operator or the like becomes unnecessary. Also, by performing such self injection, it is possible to reduce the phase noise of the oscillation output signal. The oscillation output signal output from the voltage control oscillator may be input to the phase frequency comparator without being divided, or may be input to the phase frequency comparator after being divided. In the latter case, it is possible to output an oscillation output signal of a frequency obtained by multiplying the frequency of the reference signal by the division ratio.

Further, in the self injection phase synchronization circuit according to the present invention, the switch for switching whether the injection signal is injected into the voltage controlled oscillator and the injection signal are not injected until the oscillation output signal is synchronized with the reference signal. And an injection controller for controlling the switch to be injected later.
With such a configuration, it is possible to prevent the oscillation output signal from becoming unstable by performing self injection in a situation where the oscillation frequency is not stable.

The self-injection phase-locked loop according to the present invention may further include a pulse generator for outputting an injection signal in which at least one of the strength and the pulse width of the injection signal output from the variable delayer is changed.
Such a configuration allows, for example, the intensity and pulse width of the injection signal to be changed in order to achieve appropriate self-injection.

The self-injection phase-locked loop according to the present invention further includes a divider that divides the oscillation output signal and outputs the divided oscillation output signal to the phase frequency comparator and the variable delay unit. The pulse width of the injection signal output from the variable delay device may at least be changed.
With such a configuration, for example, simplification of a circuit and power saving can be realized by performing self injection using a signal divided by a divider. Also, although the pulse width changes with division, the pulse width can be made appropriate by the pulse generator. As a result, for example, spurious noise can be reduced.

Further, in the self injection phase synchronization circuit according to the present invention, the pulse generator at least changes the strength of the injection signal output from the variable delay device, and a noise detector that detects the noise amount using the oscillation output signal. And an intensity controller for controlling the pulse generator to output an injection signal having an intensity corresponding to the noise amount detected by the noise detector, and the intensity of the injection signal output from the pulse generator May be controlled by the intensity controller to increase as the detected noise amount increases and decreases as the detected noise amount decreases.
With such a configuration, when the amount of noise is large, the influence of injection can be increased by increasing the strength of the injection signal, and as a result, phase noise can be reduced. On the other hand, when the intensity of the injection signal is increased, spurious noise is generated. Therefore, when the amount of noise is small, the influence of the injection can be reduced by reducing the intensity of the injection signal, thereby reducing the spurious noise. Can.

  According to the self injection phase locked loop according to the present invention, self injection with an appropriate phase can be realized automatically.

Block diagram showing the configuration of a self injection phase locked loop according to an embodiment of the present invention Block diagram showing the configuration of the delay controller in the same embodiment Graph showing influence of external noise in the same embodiment Graph showing frequency characteristics of oscillation output signal with respect to reference signal in the same embodiment Block diagram showing another configuration of the self injection phase locked loop according to the same embodiment

  Hereinafter, a self injection phase locked loop according to the present invention will be described using an embodiment. In the following embodiments, the components denoted by the same reference numerals are the same or correspond to each other, and the description thereof may not be repeated. The self injection phase synchronization circuit according to the present embodiment performs self injection (self injection) so as to provide negative feedback in the phase synchronization circuit, and automatically controls the phase of the injection signal used for the self injection. It is.

  FIG. 1 is a block diagram showing a configuration of a self injection phase synchronization circuit 1 according to the present embodiment. The self injection phase locked loop 1 according to the present embodiment includes a voltage controlled oscillator (VCO) 11, a frequency divider 12, a phase frequency detector (PFD) 13, and a voltage generator 14. , A delay controller 15, a variable delay 16, a switch 17, and an injection controller 18.

The voltage control oscillator 11 outputs an oscillation output signal of an oscillation frequency corresponding to the control voltage from the voltage generator 14. Although there is no limitation on the type of the voltage controlled oscillator 11, for example, it may be an LC tank oscillator, an LC cross-coupled oscillator, or any other type of voltage controlled oscillator. Further, an injection signal for self injection is injected into the voltage control oscillator 11. There is no limitation on the method of injecting the injection signal into the voltage control oscillator 11. As a method of injecting the injection signal into the voltage controlled oscillator 11, for example, a method (direct current injection) of directly injecting the current of the injection signal into the voltage controlled oscillator 11, or injecting a pulse of the injection signal into the voltage controlled oscillator 11. There is a method (capacitive coupling injection) and the like. For specific examples of the injection method, see, for example, the following documents.
Article: S. Morishita, S. Shimizu, T. Kihara, T. Yoshimura, "Subharmonically Injection-Locked PLL with Variable Pulse-Width Injections," ISCAS 2015, pp. 557-560, May 2015

  The frequency divider 12 divides the oscillation output signal output from the voltage control oscillator 11 by a predetermined division ratio n, and outputs the divided oscillation output signal to the phase frequency comparator 13 and the injection controller 18. Output. The frequency of the oscillation output signal is reduced to 1 / n by this frequency divider 12. Here, n is a positive integer. The divider 12 may or may not be able to change the division ratio n.

  The phase frequency comparator 13 compares the phase and frequency of the oscillation output signal with that of the reference signal, and outputs a comparison result signal indicating the result of the comparison. The reference signal is a signal (reference signal) to be synchronized with the oscillation output signal in the self injection phase synchronization circuit, and is preferably, for example, a stable low phase noise signal oscillated by a crystal oscillator or the like. is there. Since self-injection phase synchronization circuit 1 has frequency divider 12, the oscillation output signal to be compared with the reference signal becomes the oscillation output signal divided by frequency divider 12. Although the configuration of the phase frequency comparator 13 is not particularly limited, for example, a comparison result signal indicating the difference between the rising edge of the oscillation output signal and the reference signal may be output.

  The voltage generator 14 generates a control voltage according to the comparison result signal output from the phase frequency comparator 13 and outputs the control voltage to the voltage control oscillator 11. The voltage generator 14 includes a charge pump (CP) 19 and a loop filter (LPF) 20.

  The charge pump 19 converts the comparison result signal output from the phase frequency comparator 13 into a current or a voltage and outputs the current or voltage to the loop filter 20. That is, the charge pump may be current charge type or voltage charge type. The charge pump 19 converts the comparison result of the two signals detected by the phase frequency comparator 13 into a current pulse or a voltage pulse.

  The loop filter 20 generates a control voltage according to the current or voltage converted by the charge pump 19 and outputs the control voltage to the voltage control oscillator 11. The loop filter 20 is a low pass filter that smoothes the output from the charge pump 19 and outputs the smoothed output.

  In the present embodiment, the case where the voltage generator 14 includes the charge pump 19 and the loop filter 20 will be described, but this may not be the case. The voltage generator 14 only needs to output the control voltage corresponding to the comparison result signal to the voltage control oscillator 11, and the configuration is not limited. That is, in the PLL, the configuration existing between the phase frequency comparator 13 and the voltage control oscillator 11 may be considered to be the voltage generator 14. When the PLL is configured on an integrated circuit, the voltage generator 14 usually includes the charge pump 19 and the loop filter 20 in many cases, but when the PLL is configured discretely, the charge pump 19 A circuit that operates as an integrator (active filter) using an OP amplifier and that samples and holds a voltage corresponding to a comparison result signal can also be used as the voltage generator 14 other than having the above and loop filter 20. . When the loop filter is an active filter using an operational amplifier or the like, internal noise of the transistor constituting the operational amplifier may cause phase noise of the output clock of the PLL. In addition, when the PLL is configured on an integrated circuit, it is considered that the operational amplifier is also in the circuit and thus susceptible to power supply noise accompanying the operation of the PLL. On the other hand, in the case of the charge pump system, the loop filter can be configured by a combination of simple resistance and capacitance. By simplifying the loop filter as such, it is considered that the filter circuit is less susceptible to the above-mentioned noise. From such a point of view, the charge pump method is particularly preferable when the circuit including the PLL is configured on an integrated circuit.

  Further, the configurations of the phase frequency comparator 13 and the charge pump 19 of the PLL shown in FIG. 1 are described as such for convenience, and any two or more configurations may be integrally configured. For example, the phase frequency comparator 13 and the charge pump 19 may be integrally configured, or the charge pump 19 and the loop filter 20 may be integrally configured.

  The delay controller 15 controls the delay time of the variable delay unit 16. That is, the delay controller 15 controls the delay time so that the injection signal injected into the voltage control oscillator 11 has negative feedback. When the injection signal injected into the voltage controlled oscillator 11 is delayed by a phase larger than π / 2 and smaller than 3π / 2 with respect to the oscillation output signal, injection of negative feedback is performed. Therefore, it is preferable that the delay controller 15 control the delay time to be within the range. As will be described later, when the injection signal injected into the voltage control oscillator 11 is delayed in phase by π with respect to the oscillation output signal, the injection becomes the optimum negative feedback. Therefore, the delay controller 15 may control the variable delay unit 16 so that the phase of the injection signal is delayed by π with respect to the oscillation output signal. A specific control method will be described later with reference to FIG.

  The variable delay unit 16 outputs an injection signal obtained by delaying the oscillation output signal output from the voltage control oscillator 11 by a variable delay time. The delay time is controlled by the delay controller 15. Further, the injection signal output from the variable delay 16 is injected into the voltage control oscillator 11 via the switch 17. The variable delay unit 16 may, for example, delay the oscillation output signal by a delay time corresponding to the control voltage.

  The delay controller 15 and the variable delay device 16 may or may not be configured similarly to a so-called DLL (Delay-Locked Loop). In this embodiment, the case where the delay controller 15 and the variable delay 16 are configured in the same manner as the DLL will be mainly described.

  The switch 17 switches whether to inject the injection signal from the variable delay 16 into the voltage control oscillator 11. The switching is performed under the control of the injection controller 18. Assuming that the switch 17 is configured by an AND circuit as shown in FIG. 1, if the injection enable signal from the injection controller 18 is “1”, the injection signal from the variable delay 16 is a voltage. The injection signal is not injected into the voltage controlled oscillator 11 when the injection enable signal is “0”, that is, when the injection enable signal is not output. Needless to say, the switch 17 may be configured of a switch other than the AND circuit.

  The injection controller 18 does not inject the injection signal into the voltage control oscillator 11 until the oscillation output signal synchronizes with the reference signal, and after the oscillation output signal synchronizes with the reference signal, the injection signal is injected into the voltage control oscillator 11 Control the switch 17 so that The injection controller 18 prevents self-injection from occurring when the oscillation frequency is not yet stable, by allowing self-injection to occur after the PLL has locked to the reference signal. As a result, injection is performed when the oscillation frequency is unstable, and the oscillation output signal can be prevented from becoming unstable. As described above, when the switch 17 is an AND circuit, the injection controller 18 outputs the injection enable signal “0” until the oscillation output signal is synchronized with the reference signal, and after synchronization, injection is performed. The enable signal "1" may be output. Also, outputting the injection enable signal “0” may be considered as not outputting the injection enable signal. Also, the method by which the injection controller 18 determines whether the oscillation output signal is synchronized with the reference signal does not matter. For example, the injection controller 18 may detect that both are synchronized in accordance with the comparison result of the oscillation output signal and the reference signal. The comparison result may use the comparison result by the phase frequency comparator 13 or the injection controller 18 may perform the comparison. In the present embodiment, the latter case will be mainly described. Also, for example, the injection controller 18 may synchronize the two when a predetermined time has elapsed since the PLL started to operate. Specifically, the injection controller 18 may assume that a predetermined time has elapsed when the clock count value of the reference signal from the start of operation of the PLL reaches a predetermined value. When the divider 12 can change the division ratio during operation of the circuit, the injection controller 18 can reference the oscillation output signal even after the divider 12 changes the division ratio. The switch 17 may be controlled such that the injection signal is not injected into the voltage control oscillator 11 until it is synchronized with the signal, and the injection signal is injected into the voltage control oscillator 11 after the oscillation output signal is synchronized with the reference signal. It is suitable. When the injection controller 18 performs control in response to the detection of synchronization, injection will not be performed until synchronization occurs even when the division ratio is changed. On the other hand, when the control is performed according to the elapsed time from the start of the operation, the injection controller 18 does not inject the injection signal into the voltage control oscillator 11, for example, when the division ratio is changed. Even if the switch 17 is controlled so that both are synchronized after a predetermined time has elapsed since the change, the switch 17 is controlled so that the injection signal is injected into the voltage controlled oscillator 11 Good. Further, to control the injection signal not to be injected into the voltage control oscillator 11 means to control so as not to be self injection. Therefore, the control is usually to prevent the injection signal from being input to voltage controlled oscillator 11, but the injection signal to the extent that self injection is not obtained, ie, an injection signal with very small intensity is input to voltage controlled oscillator 11. May be considered to include.

  FIG. 2 is a block diagram showing the configuration of the delay controller 15 according to the present embodiment. In FIG. 2, the delay controller 15 includes a NOT circuit 21, a phase detector (PD: Phase Detector) 22, and a loop filter (LPF) 23.

  The NOT circuit 21 inverts the oscillation output signal output from the voltage control oscillator 11. By this inversion, the phase of the oscillation output signal is shifted by π (180 °). The oscillation output signal is inverted so that the phase of the injection signal injected into the voltage control oscillator 11 and the phase of the oscillation output signal output from the voltage control oscillator 11 differ by π. By setting the phase difference between the two signals to π, the injection signal can be injected by negative feedback, and as described later, optimal injection can be achieved.

  The phase comparator 22 compares the phase of the oscillation output signal output from the voltage control oscillator 11 and inverted by the NOT circuit 21 with the injection signal output from the variable delay device 16, and indicates the result of the comparison. Output Although the phase comparator 22 may be a phase frequency comparator, it is sufficient here to compare the phases of both signals, so that frequency comparison may not be performed. The phase comparator 22 may be, for example, a phase detector such as a mixer.

  The loop filter 23 generates a signal for controlling the variable delay 16 in accordance with the signal output from the phase comparator 22 and outputs the signal to the variable delay 16. The signal output from the loop filter 23 may be the control voltage of the variable delay unit 16.

  Of the delay controller 15 and the variable delay device 16 shown in FIG. 2, the DLL is configured by the configuration other than the NOT circuit 21. Further, the presence of the NOT circuit 21 causes a phase difference of π between the oscillation output signal and the injection signal, unlike in a normal DLL. Further, in the delay controller 15, a charge pump may be provided between the phase comparator 22 and the loop filter 23 as in the PLL. Although FIG. 2 shows the configuration in which the oscillation output signal is inverted by the NOT circuit 21, the injection signal may be inverted by the NOT circuit 21. Also in this case, the phase of the injection signal can be shifted by π with respect to the oscillation output signal. When the NOT circuit 21 is used, the phase difference between the injection signal and the oscillation output signal is π. Therefore, when it is desired to make a phase difference other than that, instead of the NOT circuit 21 or together with the NOT circuit 21, a delayer or a phase shifter is used to delay at least one of the inputs to the phase comparator 22. You may Even when the phase difference between the injection signal and the oscillation output signal is controlled to be other than π, at least the injection signal is controlled to be a phase difference in a range where it is injected by negative feedback.

  Next, the operation of the self injection phase locked loop 1 will be briefly described. When the processing in the self injection phase synchronization circuit 1 is started, in the PLL, the oscillation output signal output by the voltage control oscillator 11 is controlled to be locked to the reference signal. Since the injection enable signal output from the injection controller 18 is “0” at the start time, the output of the switch 17 is also “0” and injection to the voltage control oscillator 11 is not performed. It will be.

  Thereafter, when the oscillation output signal output from the voltage control oscillator 11 is synchronized with the reference signal, the injection controller 18 switches the injection enable signal from “0” to “1”. As a result, the injection signal output from the variable delay 16 is injected into the voltage control oscillator 11. Since the injection signal is the result of the DLL using the signal in which the phase of the oscillation output signal is shifted by π as described above, the phase differs from the oscillation output signal by π, and the voltage control oscillator is negative feedback. 11 will be injected. In the voltage control oscillator 11, an oscillation output signal is output according to the control voltage output from the voltage generator 14 and the negative feedback injection signal output from the variable delay device 16. As a result, phase noise is reduced.

Here, a simulation result in which external noise is applied to a node corresponding to between the loop filter 20 and the voltage control oscillator 11 will be described. FIG. 3 is a graph showing the relationship between the offset angular frequency (horizontal axis) of external noise in the simulation and the degree of phase fluctuation (vertical axis) in the oscillation output signal with respect to external noise to the loop filter LPF of the PLL. Note that θ _n in the graph of FIG. 3 is a phase (deg) delayed by the variable delay device 16. In addition, it diverged when (theta) _n became larger than -63 degrees. From the results of FIG. 3, it can be seen that the output error can be suppressed in the case of negative feedback as compared with the case of no feedback (θ _n = −90 °). On the other hand, in the case of positive feedback, the error is larger than in the case of no feedback. From this, it can be understood that phase control (control of delay time) by the delay controller 15 for negative feedback is important. In addition, it is understood that the optimum negative feedback is obtained when the phase difference between the oscillation output signal and the injection signal is π. Therefore, in the present embodiment, in the delay controller 15, one of the signals input to the phase comparator 22 is inverted by the NOT circuit 21.

Next, simulation results on the frequency characteristics of the oscillation output signal with respect to the reference signal will also be described. FIG. 4 is a graph showing the relationship between the offset angular frequency (horizontal axis) of the reference signal and the phase response (vertical axis) of the oscillation output signal with respect to the reference signal in the simulation. Θ _n in the graph of FIG. 4 is also similar to the graph of FIG. In the graph of FIG. 4, peaks occur in the input / output characteristics at θ _n = −90 ° and −60 °. Since the presence of such a peak causes noise, the peak is generally increased by increasing the capacity of components such as a capacitor constituting the loop filter 20, that is, by increasing the size of the loop filter 20. It will be lowered. On the other hand, when self injection is performed by negative feedback as in the self injection phase locked loop 1 according to the present embodiment, such peak gain can be suppressed. In this simulation result, no peak occurs particularly when the phase difference between the reference signal and the oscillation output signal is 120 ° or more. Therefore, freedom is created in the design of the loop filter 20. Specifically, even if the loop filter 20 having a small damping factor is used, the peak gain can be suppressed by self injection, so that the capacity of the components constituting the loop filter 20 can be reduced. The size of the loop filter 20 can be reduced.

  In the self-injection phase synchronization circuit 1 according to the present embodiment, the strength and pulse width of the injection signal injected into the voltage control oscillator 11 may be changed. FIG. 5 is a block diagram showing an example of the configuration of such a self injection phase synchronization circuit 1. In FIG. 5, the self injection phase locked loop 1 switches the voltage control oscillator 11, the frequency divider 12, the phase frequency comparator 13, the voltage generator 14, the delay controller 15, the variable delay 16, and And an injection controller 18, a frequency divider 31, a pulse generator 32, a noise detector 33, and an intensity controller 34. The configurations and operations other than the frequency divider 31, the pulse generator 32, the noise detector 33, and the intensity controller 34 are the same as those described above, and the detailed description thereof will be omitted.

  The divider 31 divides the oscillation output signal output from the voltage control oscillator 11 by a predetermined division ratio m, and outputs the divided oscillation output signal to the divider 12 and the variable delay unit 16 Do. In this case, since the frequency is divided by the frequency divider 31 and the frequency divider 12, the frequency of the oscillation output signal is 1 / (n × m) and is input to the phase frequency comparator 13. . Here, m is a positive integer. Preferably, m is not a large value. For example, when the injection according to the injection signal obtained by delaying the oscillation output signal divided by the frequency divider 31 is performed, it is injected into the voltage control oscillator 11 as compared with the case where the frequency divider 31 does not exist Pulse frequency is 1 / m. If the frequency is too low, it will be difficult to synchronize with the injection signal. m is preferably 8 or less, more preferably 4 or less. By providing this frequency divider 31, it becomes possible to determine the frequency of self injection independently of the oscillation output signal. When an injection signal corresponding to the oscillation output signal divided by the frequency divider 31 is injected into the voltage control oscillator 11, the injection of the injection signal is not performed for every cycle of the oscillation output signal. , Will be done in a leap. Therefore, in that case, it is preferable that injection to the voltage controlled oscillator 11 be performed by a method (capacitive coupling injection) of injecting a pulse of injection signal. The divider 31 may or may not be capable of changing the division ratio m.

  The pulse generator 32 outputs an injection signal in which at least one of the intensity and the pulse width of the injection signal output from the variable delay 16 is changed. The strength of the injection signal is the amplitude of the pulse contained in the injection signal. The pulse width of the injection signal is the length of time from the rise time point of the pulse included in the injection signal to the fall time point. Preferably, the phases of the injection signal input to the pulse generator 32 and the injection signal output from the pulse generator 32 are the same. The same phase may mean that the rising timings of the pulses included in the injection signal coincide with each other. In the present embodiment, the case where the pulse generator 32 adjusts both the intensity and pulse width of the injection signal will be mainly described.

  In the case where the pulse generator 32 changes the pulse width, it is preferable that the changed pulse width has a half integer length of the period of the oscillation output signal. By doing so, it is possible to reduce spurious noise. For example, the pulse width after the change may be a half cycle length of the oscillation output signal. If the frequency divider 31 is present, the pulse width of the injection signal output from the variable delay device 16 becomes large due to the frequency division, so that the pulse width is adjusted by the pulse generator 32 to be small. It is also good.

The noise detector 33 detects the amount of noise using at least the oscillation output signal output from the voltage control oscillator 11. The noise detector 33 may also detect the amount of noise using the reference signal as shown in FIG. The noise amount can be used to know the degree of noise, and may be, for example, the jitter amount of the oscillation output signal, and in the frequency spectrum of the oscillation output signal, a frequency separated by a predetermined offset frequency from the center frequency Or the other value which can know the amount of noise. The center frequency is an ideal frequency of the oscillation output signal, and assuming that the center frequency is f ₀ and the frequency of the reference signal is f ₁ , f ₀ = f ₁ × n × m. Here, n and m are the above-described division ratios. Therefore, assuming that the offset frequency is f _m , the noise amount is the value of f ₀ ± f _m in the frequency spectrum. Note that only one of the two values may be used as the noise amount, or both may be used. In the latter case, for example, a representative value of two values may be used as the noise amount, or a sum of two values may be used as the noise amount. The representative value may be, for example, an average value, a maximum value, or a minimum value. If the noise amount is a jitter amount, the noise detector 33 may be a device capable of measuring jitter, for example, an oscilloscope (jitter monitor). In the case where the noise detector 33 is an oscilloscope, it is preferable that a reference signal is also input to the noise detector 33. Also, if the noise amount is a value of f ₀ ± f _m in the frequency spectrum, the noise detector 33 measures f ₀ ± in the spectrum analyzer that acquires the frequency spectrum and in the frequency spectrum acquired by the spectrum analyzer. It may have a configuration for acquiring the noise amount of f _m .

  The intensity controller 34 controls the pulse generator 32 so that an injection signal having an intensity corresponding to the amount of noise detected by the noise detector 33 is output. In the control, the intensity controller 34 increases the intensity of the injection signal injected into the voltage control oscillator 11 as the detected noise amount increases, and injects the voltage control oscillator 11 as the detected noise amount decreases. Control may be performed to reduce the intensity of the injected signal. When the intensity controller 34 specifies the intensity of the injection signal corresponding to the detected noise amount, for example, information such as a table that associates the noise amount with the intensity of the injection signal may be used. You may use a function that In the information for correlating the amount of noise with the strength of the injection signal, it is assumed that both are correlated so that the strength of the injection signal increases as the amount of noise increases. Further, it is preferable that the function having the amount of noise as an argument is an increase function to the amount of noise, and the value of the function is the strength of the injection signal. Note that the increasing function may be considered to be a monotonous non-decreasing function. By performing such control, the influence of injection can be increased when there is much noise such as external noise, and as a result, phase noise can be reduced. On the other hand, when the intensity of the injection signal is increased, the spurious noise is increased. Therefore, when the noise such as the external noise is small, the spurious noise can be reduced by reducing the influence of the injection. In addition, control regarding the strength of such an injection signal is considered to be effective also for reducing phase noise caused by other than external noise, that is, phase noise of the PLL itself. Also, it may be possible to reduce the capacity of the loop filter 20 in response to such stabilization of the PLL.

  As a method of monitoring the oscillation output signal to optimize the response of the PLL, it is conceivable to change the loop band of the PLL or the operation timing of a noise source (for example, an output driver). However, the loop band of the PLL needs to be determined in consideration of the jitter suppression effect of the reference signal, the setting of the division ratio, and the like, and the adjustment range is limited. In addition, although the timing change of the noise source can be performed to some extent when the noise source is clarified, in many cases it is difficult to identify the noise source, and it is realistically performed. Is difficult. On the other hand, there is an advantage that by controlling the strength of the injection signal by the strength controller 34, it is possible to adjust the response to external noise without changing the loop band of the PLL or the operation timing of the noise source.

  Further, in the self-injection phase-locked loop 1 shown in FIG. 5, since the oscillation output signal input to the variable delay unit 16 is divided, in the delay controller 15, injection is performed as shown in FIG. It is preferable that the oscillation output signal is inverted and input to the phase comparator 22 instead of the signal. Further, in the case of changing the pulse width by the pulse generator 32 in the self-injection phase synchronization circuit 1 shown in FIG. 5, the duty ratio (ratio of H to L) of the injection signal input to the delay controller 15 Is not 50%, the phase comparator 22 is preferably not of the mixer type.

  Although FIG. 5 describes the case where the self-injection phase synchronization circuit 1 includes the frequency divider 31, this may not be the case. The self injection phase synchronization circuit 1 may not have the divider 31. In that case, the pulse width may not be adjusted in the pulse generator 32. The pulse generator 32 may adjust the pulse width even when the frequency divider 31 does not exist. In that case, for example, the operator or the like may adjust (set) the pulse width of the pulse generated by the pulse generator 32.

Although FIG. 5 describes the case where the self injection phase synchronization circuit 1 includes the noise detector 33 and the intensity controller 34, this may not be the case. The self injection phase synchronization circuit 1 may not include the noise detector 33 and the intensity controller 34. In that case, the pulse generator 32 may not adjust the intensity of the pulse. Note that even if the noise detector 33 and the intensity controller 34 are not present, the pulse generator 32 may adjust the intensity of the pulse. In that case, for example, the operator or the like may adjust (set) the intensity of the pulse generated by the pulse generator 32. For example, in the case of negative feedback at θ _n = −180 °, if an injection signal having a higher intensity than that obtained when obtaining the phase response of FIG. 4 is injected, a corner is more than the characteristic curve at θ _n = −180 ° in The characteristic curve of the lower side (in the direction in which the response becomes smaller) is obtained at the point of, and the noise suppression effect is further enhanced. Therefore, the pulse generator 32 may be adjusted to generate a pulse of an intensity corresponding to the degree of suppression of noise required.

  As described above, according to the self-injection phase synchronization circuit 1 according to the present embodiment, phase noise can be reduced by performing self-injection of negative feedback in the phase synchronization circuit. Also, it can be seen that the negative feedback self-injection improves the robustness to external noise. Furthermore, since the peak gain in the frequency characteristic can be suppressed, the capacity of the loop filter 20 can also be reduced. Further, in the synchronous circuit having the self-injecting VCO, the delay amount of the injection signal with respect to the oscillation output signal, that is, the phase of the injection signal can be automatically adjusted, so that the operator does not need to adjust the phase. The burden on people is reduced. In particular, even when the division ratio of the PLL or the frequency of the reference signal is changed, the delay ratio according to the changed frequency is automatically adjusted appropriately so that the division ratio or the frequency is changed. There is no need to manually adjust the amount of delay each time it is changed. Also, by performing such automatic adjustment of the delay amount, even if the period of the oscillation output signal changes by a very small amount due to the influence of phase noise etc., the delay amount is changed accordingly. Thus, for example, it is possible to inject an injection signal whose phase shift amount with respect to the oscillation output signal is π. As a result, the phase noise reduction effect is enhanced. Further, by providing the injection controller 18, it is possible to prevent the oscillation output signal from becoming unstable due to self injection being performed in a situation where the oscillation frequency is not stable. Further, when the oscillation output signal input to the variable delay unit 16 is divided, simplification of the circuit and power saving can be realized. Also, by injecting an injection signal of an intensity corresponding to the detected noise amount, even if the noise amount is large, phase noise can be reduced, and spurious noise in the case where the noise amount is small can be reduced. It can be reduced.

  The self injection phase synchronization circuit 1 according to the present embodiment can be used, for example, as a noise reduction method of a loop band in the Integer-N and Fractional-N clock generation circuits. In the Integer-N clock generation circuit, it is necessary to suppress the loop bandwidth of the PLL to less than one tenth to several tenths of the frequency of the reference signal. This is because if the loop bandwidth is made larger than this, the output fluctuation of the phase frequency comparator affects the operation of the PLL and the clock output becomes unstable. Specifically, the clock output periodically fluctuates in time, and noise caused by the reference signal is generated in the vicinity of the loop band. The same applies to the fractional-N clock generation circuit, and the restriction on the loop bandwidth is further increased. On the other hand, since self-injection phase-locked loop 1 according to the present embodiment has such a suppression effect on noise in the vicinity of the loop band of the PLL, the output clock fluctuates without reducing the loop band of PLL. Can be expected not to happen. In addition, the self-injection phase-locked loop 1 according to the present embodiment is generally used in a synchronization circuit using an LC tank oscillator that may be resistant to high frequency noise, a transceiver circuit operating in the chip at the same frequency, etc. Is also possible. Specifically, the transceiver circuit can be used as a clock recovery circuit or a PLL for a local oscillator.

  Further, although the case where the self injection phase synchronization circuit 1 includes the switch 17 and the injection controller 18 has been described in the present embodiment, this may not be the case. The self injection phase synchronization circuit 1 may not have the switch 17 and the injection controller 18. In that case, the period until the PLL locks may be long, but after locking, it is similar to the self-injection phase-locked loop 1 described above.

  Moreover, although the case where the self injection phase synchronization circuit 1 is provided with the frequency divider 12 has been described in the present embodiment, this may not be the case. The self injection phase synchronization circuit 1 may not have the divider 12. In that case, in FIG. 1, the oscillation output signal output from the voltage control oscillator 11 may be input to the phase frequency comparator 13 and the injection controller 18, and in FIG. The oscillation output signal after frequency division may be input to the phase frequency comparator 13, the variable delay device 16 and the injection controller 18.

Further, in the present embodiment, as described above, the case where one of the oscillation output signal and the injection signal is inverted by the NOT circuit 21 and input to the phase comparator 22 in the delay controller 15 shown in FIG. 2 will be described. Yes, but it does not have to be. As described above, it is preferable that the phase of the oscillation output signal and the phase of the injection signal differ by π, but when the phases of the two are different by π at the previous stage of the phase comparator 22 The phase of the oscillation output signal and the injection signal may differ by π or more at the time of injection into the voltage control oscillator 11 according to a delay or the like in the subsequent circuits. In such a case, the delay time in the circuit subsequent to the phase comparator 22 is also taken into consideration so that the phase difference between the oscillation output signal and the injection signal becomes π at the time of injection into the voltage controlled oscillator 11. Processing such as inversion at the front stage of the phase comparator 22 may be performed. Specifically, the injection signal may be delayed by time T _{d at} a stage before the phase comparator 22. When the NOT circuit 21 is present on the injection signal side, the delay may be performed in the front stage or the rear stage of the NOT circuit 21. Further, it is preferable that the time _Td be a time corresponding to a delay time in a circuit downstream of the phase comparator 22. In the present embodiment, since the delay amount of the injection signal can be automatically adjusted, optimal timing adjustment can also be performed by setting the offset (T _d ) in this manner.

  In the self-injection phase-locked loop 1 according to the present embodiment, it is needless to say that one of the components that can be realized either analog or digital may be realized.

  Also, in the above embodiment, each processing or each function may be realized by centralized processing by a single device or a single system, or distributed processing by a plurality of devices or a plurality of systems. It may be realized by

  Further, in the above embodiment, the transfer of information performed between the components is performed by, for example, one of the components if the two components performing the transfer of information are physically different. It may be performed by the output of the information and the reception of the information by the other component, or if the two components that exchange the information are physically the same, one of the components It may be performed by moving from the phase of processing corresponding to to the phase of processing corresponding to the other component.

  Further, in the above embodiment, information related to processing executed by each component, for example, information received, acquired, selected, generated, transmitted, or received by each component Also, information such as threshold values, mathematical expressions, addresses and the like used by each component in processing may be held temporarily or for a long time in a recording medium (not shown), even if not specified in the above description. Further, each component or a storage unit (not shown) may store information in the recording medium (not shown). Each component or a reading unit (not shown) may read information from the recording medium (not shown).

  Further, in the above embodiment, when the information used in each component or the like, for example, information such as a threshold or an address used in processing by each component or various setting values may be changed by the user, Although not explicitly stated in the description, the user may or may not be able to change the information as appropriate. When the user can change such information, the change is realized, for example, by a receiving unit (not shown) that receives a change instruction from the user and a change unit (not shown) that changes the information according to the change instruction. May be The acceptance of the change instruction by the acceptance unit (not shown) may be, for example, acceptance from an input device, reception of information transmitted via a communication line, or acceptance of information read from a predetermined recording medium .

  Further, in the above embodiment, each component may be configured by dedicated hardware, or a component that can be realized by software may be realized by executing a program. For example, each component can be realized by a program execution unit such as a CPU reading and executing a software program recorded on a recording medium such as a hard disk or a semiconductor memory. At the time of the execution, the program execution unit may execute the program while accessing the storage unit or the recording medium. This program may be executed by being downloaded from a server or the like, and executed by reading a program recorded on a predetermined recording medium (for example, an optical disk such as a CD-ROM, a magnetic disk, a semiconductor memory, etc.) It may be done. Also, this program may be used as a program that constitutes a program product. Moreover, the computer that executes this program may be singular or plural. That is, centralized processing may be performed, or distributed processing may be performed.

  Further, it is needless to say that the present invention is not limited to the above embodiments, and various modifications are possible, which are also included in the scope of the present invention.

  From the above, according to the self injection phase locked loop according to the present invention, an effect of reducing the phase noise can be obtained, which is useful as a phase locked loop (PLL).

1 self injection phase locked loop circuit 11 voltage controlled oscillator (VCO)
12, 31 divider 13 phase frequency comparator (PFD)
14 Voltage Generator 15 Delay Controller 16 Variable Delay Device 17 Switch 18 Injection Controller 19 Charge Pump (CP)
20, 23 loop filter (LPF)
21 NOT circuit 22 Phase comparator (PD)
32 pulse generator 33 noise detector 34 intensity controller

Claims (5)

A voltage control oscillator that outputs an oscillation output signal of an oscillation frequency corresponding to the control voltage;
A phase frequency comparator that compares the phase and frequency of the oscillation output signal with a reference signal and outputs a comparison result signal indicating the result of the comparison;
A voltage generator that generates the control voltage according to the comparison result signal and outputs the control voltage to the voltage controlled oscillator;
A variable delay that outputs an injection signal obtained by delaying the oscillation output signal by a variable delay time;
A delay controller for controlling the delay time of the variable delay device;
The injection signal is injected into the voltage controlled oscillator,
The delay controller controls a delay time such that an injection signal injected into the voltage controlled oscillator is delayed by a phase larger than π / 2 and smaller than 3π / 2 with respect to the oscillation output signal. Synchronous circuit. A switch for switching whether to inject the injection signal into the voltage controlled oscillator;
The injection controller according to claim 1, further comprising: an injection controller for controlling the switch so that the injection signal is not injected until the oscillation output signal is synchronized with the reference signal but is injected after synchronization. Self injection phase locked loop circuit. The self-injection phase-locked loop according to claim 1 or 2, further comprising a pulse generator that outputs an injection signal in which at least one of the intensity and the pulse width of the injection signal output from the variable delayer is changed. It further comprises a frequency divider that divides the oscillation output signal and outputs the divided oscillation output signal to the phase frequency comparator and the variable delay device.
The self injection phase synchronization circuit according to claim 3, wherein the pulse generator changes at least a pulse width of an injection signal output from the variable delay device. The pulse generator at least changes the strength of the injection signal output from the variable delay device,
A noise detector that detects a noise amount using the oscillation output signal;
And an intensity controller for controlling the pulse generator to output an injection signal of an intensity corresponding to the noise amount detected by the noise detector.
The intensity controller controls the intensity of the injection signal output from the pulse generator to be larger as the detected noise amount is larger and smaller as the detected noise amount is smaller. The self injection phase locked loop according to claim 4.

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