JP6372185B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device using a switching element.

  A method for controlling a motor without using a sensor for detecting the rotor position is known. For this purpose, it is necessary to detect the phase current of the motor. As an inexpensive detection method, a method is known in which a current supplied from a converter circuit to an inverter circuit is detected by a resistor. For example, the current of each phase can be obtained from information on switching in the inverter circuit and current values detected before and after the switching (see, for example, Non-Patent Document 1).

  Further, as a power conversion device having a converter circuit and an inverter circuit, a device having a relatively small capacitor and pulsating an input voltage to the inverter circuit is known (see, for example, Patent Document 1). In this apparatus, the power factor and the harmonics of the power source are improved by controlling the motor torque at a frequency twice the power source frequency.

JP 2002-51589 A

Yasuhiko Tanizawa and two others, "Method for detecting the three-phase output current of a PWM inverter on the DC side", July 15, 1994, The Institute of Electrical Engineers of Japan, Vol. 12-22, pp. 45 -49

  In such a detection method, it is assumed that a current flows only through the circuit of one arm among the circuit of the upper arm and the circuit of the lower arm corresponding to a certain phase. However, when the input voltage of the inverter circuit is greatly reduced, current flows in the circuit of the arm where current should not flow. For example, when a relatively small capacitor is used as in the power conversion device of Patent Document 1, such a decrease in the input voltage of the inverter circuit frequently occurs. Further, even if the capacitance of the capacitor is not so small, the input voltage of the inverter circuit can be lowered.

  This will be described more specifically. FIG. 1 is a circuit diagram showing a circuit corresponding to the U phase of a general inverter circuit. The circuit of FIG. 1 has an upper arm switching circuit (934) and a lower arm switching circuit (936). The upper arm switching circuit (934) includes a switching element (941) and a diode (947). The lower arm switching circuit (936) includes a switching element (943) and a diode (949). A relatively small capacitor (24) is connected between the input nodes of the inverter circuit. The input voltage (Vdc) of the inverter circuit is assumed to be sufficiently high. No current flows through the element indicated by the broken line.

  FIG. 2 is a graph showing operating points of the switching element (941) of the upper arm and the diode (949) of the lower arm in FIG. In FIG. 2, the characteristic of the switching element (941) of the upper arm is indicated by a solid line, and the characteristic of the diode (949) of the lower arm is indicated by a broken line. A voltage (VCH) is applied between the collector and emitter of the switching element (941), and a current (IU) flows. Since the voltage (VCL) applied to the diode (949) is a reverse voltage, no current flows through the diode (949). Thus, when the input voltage (Vdc) of the inverter circuit is sufficiently high, no current flows in the lower arm switching circuit (936) when the upper arm switching element (941) is conducting. . For this reason, when the input current (Idc) of the inverter circuit is detected, the phase current (IU) can be obtained.

  FIG. 3 is a circuit diagram showing the circuit of FIG. 1 when the input voltage (Vdc) of the inverter circuit is lower than the collector-emitter voltage (VCH) of the switching element (941) of the upper arm. FIG. 4 is a graph showing operating points of the switching element (941) of the upper arm and the diode (949) of the lower arm in FIG. Thus, when the input voltage (Vdc) of the inverter circuit is not sufficient, the voltage at the output node to which the switching circuit (934) of the upper arm and the switching circuit (936) of the lower arm are connected becomes negative. A forward voltage is applied to the lower arm diode (949). For this reason, a current (IUL) flows through the diode (949). The current flows as shown in FIGS. 3 and 4 because the energy stored in the inductance of the motor driven by the inverter circuit is released.

  The current flowing in the switching element (941) and the current flowing in the diode (949) are the phase current (IU), the voltage-current characteristics of the switching element (941), the voltage-current characteristics of the diode (949), and the input of the inverter circuit It depends on the voltage (Vdc). The U-phase current (IU) is the sum of the current (IUH) of the switching element (941) and the current (IUL). The current (IUL) is a part of the V-phase current (IV) and the W-phase current (IW) returned from the motor. Since the input current (Idc) of the inverter circuit and the amount of change thereof are different from the phase current of any phase, it is difficult to obtain the phase current (IU) from the input current (Idc) of the inverter circuit. The same can be said for the V-phase and W-phase circuits and currents.

  An object of the present invention is to more accurately obtain a phase current output from an inverter circuit even when the input voltage of the inverter circuit is lowered.

A first power conversion device according to the present disclosure includes a converter circuit (16) that rectifies and converts an alternating current from an alternating current power supply (92) to a direct current, and outputs the converter circuit (16) based on a drive signal. An inverter circuit (30) that converts the output direct current into alternating current and outputs, a capacitor (24) connected between output nodes of the converter circuit (16), the converter circuit (16), and the inverter circuit A current detection unit (28) that detects a current between the current detection unit (30) and a drive signal generation unit (60) that generates the drive signal based on the current detected by the current detection unit (28). . The inverter circuit (30) has a plurality of legs (32U, 32V, 32W; 232U; 332U ) . The plurality of legs (32U, 32V, 32W; 232U; 332U ) are respectively connected to the upper arm switching circuit (34; 234; 334 ) and the upper arm switching circuit (34; 234; 334 ) . switching circuits of the lower arm connected in series (36; 236; 33 6) and to have a. The upper arm switching circuit (34; 234; 334) is connected to the leg between the upper arm switching circuit (34; 234; 334) and the lower arm switching circuit (36; 236; 336). A first switching circuit for controlling a current to the output node and a second switching circuit for controlling a current from the output node of the leg, the lower arm switching circuit (36; 236; 336), A third switching circuit that controls a current from the output node of the leg; and a fourth switching circuit that controls a current to the output node of the leg.

According to this, when the input voltage of the inverter circuit (30) is lowered also, from the detected current by the current detection unit (28), it becomes possible to obtain a more accurate phase current. Also , undesired current flows into the output node through the lower arm switching circuit (36; 236; 336) and from the output node through the upper arm switching circuit (34; 234; 334). Current can be prevented from flowing out.

In the second power conversion device according to the present disclosure, in the first power conversion device, the first switching circuit includes a first switching element (41) , and the second switching circuit includes the first switching element. (41) having a second switching element (42 ) connected in parallel, the third switching circuit has a third switching element (43) , and the fourth switching circuit has the third switching element. (43) has a fourth switching element (44 ) connected in parallel.

  According to this, the switching circuit (34; 234) of the upper arm has the second switching element (42) for flowing current from the output node, and the switching circuit (36; 236) of the lower arm is connected to the output node. And a fourth switching element (44) through which a current flows. This prevents unwanted current from flowing into or out of the output node.

In the third power conversion device according to the present disclosure, in the second power conversion device, the first switching circuit further includes a first diode (46) connected in series to the first switching element (41). and, said second switching circuit further includes a second diode (47) connected in series to said second switching element (42), said third switching circuit, the third switching element (43) further comprising a third diode (48) connected in series, the fourth switching circuit further comprises a fourth diode (49) connected in series to said fourth switching element (44).

  According to this, the diodes (46-49) are connected in series to the switching elements (41-44), respectively. For this reason, the reverse withstand voltage of the switching elements (41-44) may not be so large.

In the fourth power converter according to the present disclosure, in the first power converter, the first switching circuit is connected in series to the first switching element (41) and the first switching element (41). The second switching circuit has a second switching element (42) and a second diode (46) connected in series to the second switching element (42). The node between the first switching element (41) and the first diode (47) is the same as the node between the second switching element (42) and the second diode (46). The third switching circuit includes a third switching element (43) and a third diode (49) connected in series to the third switching element (43). The fourth switching circuit includes: 4 switches Grayed an element (44), the fourth and a fourth diode connected in series to the switching element (44) (48), between the third switching element (43) and said third diode (49) The node in between is common to the node between the fourth switching element (44) and the fourth diode (48).

  According to this, the diodes (46-49) are respectively connected in antiparallel to the switching elements (41-44). For this reason, the reverse withstand voltage of the switching elements (41-44) may not be so large.

In the fifth power converter according to the present disclosure, in the first power converter, the capacitor (24) pulsates an input voltage of the inverter circuit (30) according to a voltage of the AC power supply (92). To smooth.

  According to this, although the input voltage of an inverter circuit (30) falls frequently, nevertheless, it becomes possible to obtain a more correct phase current from the current detected by the current detector (28).

  According to the present disclosure, it is possible to limit undesired current flowing into or out of the output node through the switching circuit. Therefore, even if the input voltage of the inverter circuit decreases, the phase current output from the inverter circuit can be obtained more correctly.

FIG. 1 is a circuit diagram showing a circuit corresponding to the U phase of a general inverter circuit. FIG. 2 is a graph showing an example of operating points of the switching element of the upper arm and the diode of the lower arm in FIG. FIG. 3 is a circuit diagram showing the circuit of FIG. 1 when the input voltage of the inverter circuit is lower than the collector-emitter voltage of the switching element of the upper arm. FIG. 4 is a graph showing an example of operating points of the switching element of the upper arm and the diode of the lower arm in FIG. FIG. 5 is a block diagram illustrating a configuration example of the power conversion device according to the embodiment of the present invention. FIG. 6 is a graph showing an example of the voltage of the capacitor of FIG. FIG. 7 is a circuit diagram illustrating a configuration example of the U-phase leg of FIG. 5. FIG. 8 is a graph showing an example of a signal given to the switching element of FIG. 7 and a current flowing through the circuit of FIG. FIG. 9 is a circuit diagram showing another configuration example of the U-phase leg of FIG. FIG. 10 is a circuit diagram showing still another configuration example of the U-phase leg of FIG. FIG. 11 is a circuit diagram showing still another configuration example of the U-phase leg of FIG. FIG. 12 is a block diagram illustrating another configuration example of the power conversion device in FIG. 5. FIG. 13 is a block diagram illustrating still another configuration example of the power conversion device in FIG. 5.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the components indicated by the same reference numerals in the last two digits correspond to each other and are the same or similar components.

  FIG. 5 is a block diagram illustrating a configuration example of the power conversion device according to the embodiment of the present invention. 5 includes a reactor (12), a converter circuit (16), a capacitor (24), a voltage detection unit (26), a current detection unit (28), and an inverter circuit (30 ) And a drive signal generation unit (60). The power conversion device (100) converts the AC power supplied from the AC power source (92) into three-phase AC power and drives the motor (94). As the motor (94), for example, a so-called IPM (interior permanent magnet) motor is employed. A motor (94) drives the compressor of an air conditioning apparatus, for example.

  The converter circuit (16) is connected to the AC power source (92) via the reactor (12). In this example, the converter circuit (16) is a diode bridge circuit in which four diodes are connected in a bridge shape. These diodes convert the alternating current from the alternating current power source (92) into a direct current by full-wave rectification and output the direct current. The capacitor (24) is connected between the output nodes (N1, N2) of the converter circuit (16).

  The voltage detector (26) is connected between the node (N1) and the node (N2), detects the voltage (Vdc) of the capacitor (24), and drives the detected voltage value (vc) as a drive signal. Output to the generator (60). The current detector (28) has a resistor connected between the node (N2) and the node (N3), and detects the input current (Idc) of the inverter circuit (30). More specifically, the current detection unit (28) converts the voltage of the resistor into the value of the input current (Idc) flowing through the resistor, and the result is detected as the detected current value (ic). Output to (60). The current detection unit (28) may output the voltage of the resistor, and the drive signal generation unit (60) may obtain the current value (ic) from this voltage.

  The drive signal generator (60) generates a drive signal (DS) for driving the inverter circuit (30) based on the speed command value (ωref), the voltage value (vc), and the current value (ic). And output to the inverter circuit (30). The drive signal (DS) includes a plurality of U-phase signals (S1, S2, S3, S4). Similarly, the drive signal (DS) includes a plurality of signals for the V phase and a plurality of signals for the W phase. Each V-phase signal is delayed in phase by, for example, 120 degrees (electrical angle) from the corresponding U-phase signal. Each W-phase signal is delayed in phase by, for example, 240 degrees (electrical angle) from the corresponding U-phase signal.

  Nodes (N1, N3) are input nodes of the inverter circuit (30). The voltage drop of the current detection unit (28) is small, and the voltage (Vdc) between the node (N1) and the node (N2) is almost the same as the voltage between the node (N1) and the node (N3). . The capacitor (24) has a capacitance capable of smoothing a ripple voltage (voltage fluctuation) generated when a switching element (described later) of the inverter circuit (30) performs a switching operation. However, the capacitor (24) has only a relatively small capacity, and does not have a capacity that sufficiently smoothes voltage fluctuations that occur according to the voltage of the AC power supply (92). That is, the capacitor (24) smoothes the input voltage of the inverter circuit (30) so as to pulsate according to the voltage of the AC power supply (92). At this time, the capacitor (24) smoothes the ripple generated in the input voltage of the inverter circuit (30) by switching in the inverter circuit (30). More specifically, the input voltage of the inverter circuit (30) and the voltage (Vdc) of the capacitor (24) have a pulsating component, and the frequency of this pulsating component is an integral multiple of the output voltage of the AC power source (92) ( 2 times here). The input voltage and voltage (Vdc) of the inverter circuit (30) pulsate so that, for example, the maximum value is twice or more the minimum value.

  FIG. 6 is a graph showing an example of the voltage (Vdc) of the capacitor (24) in FIG. Since the capacity of the capacitor (24) is relatively small, the current flowing through the nodes (N1, N2) becomes a pulsating current, and the voltage between the nodes (N1, N2) varies greatly as shown in FIG. In the case of FIG. 6, the maximum value (VM) of the voltage (Vdc) is the maximum value of the voltage of the AC power supply (92) (for example, about 311V when the effective value of the voltage of the AC power supply (92) is 220V), and the voltage (Vdc ) Is 0V.

  The inverter circuit (30) converts the direct current output from the converter circuit (16) into alternating current and outputs the alternating current to the motor (94). The inverter circuit (30) has a plurality of legs (32U, 32V, 32W) connected in parallel. The U-phase leg (32U) includes an upper arm switching circuit (34) and a lower arm switching circuit (36) connected in series to the upper arm switching circuit (34). The leg (32U) outputs a phase current (IU) to the motor (94) from the output node (NU) to which the upper arm switching circuit (34) and the lower arm switching circuit (36) are connected.

  The V-phase leg (32V) and the W-phase leg (32W) are configured in the same manner as the U-phase leg (32U). The leg (32V) outputs the phase current (IV) from its output node (NV) to the motor (94). The leg (32W) outputs a phase current (IW) from the output node (NW) to the motor (94).

  The drive signal generator (60) includes a position and speed estimator (62), a three-phase / two-phase converter (64), a subtractor (66), a speed controller (68), a current controller ( 72), a two-phase / three-phase converter (74), and a PWM (pulse width modulation) modulator (76). The position and speed estimation unit (62) includes the voltage value (vc) detected by the voltage detection unit (26), the voltage (vu, vv, vw) of each phase output from the PWM modulation unit (76), and three Based on the two-phase current (id, iq) output from the phase / two-phase converter (64), the rotational speed (ωm) and position (θe) of the rotor of the motor (94) are estimated and output.

  The three-phase / two-phase converter (64) obtains the current value of each phase based on the rotor position (θe) and the current value (ic) or voltage detected by the current detector (28). The three-phase current is converted into a two-phase current (id, iq) and output. The subtracter (66) subtracts the rotational speed (ωm) of the rotor from the speed command value (ωref) input from the outside of the drive signal generator (60), and outputs the subtraction result. The speed control unit (68) obtains and outputs a torque command value (Tmr) based on the subtraction result of the subtracter (66).

  The current control unit (72) obtains and outputs a voltage command value (vdr, vqr) based on the torque command value (Tmr) and the current (id, iq). The two-phase / three-phase converter (74) obtains and outputs a voltage command value (vur, vvr, vwr) based on the voltage command value (vdr, vqr) and the rotor position (θe). Based on the voltage command value (vur, vvr, vwr) and the voltage value (vc) detected by the voltage detection unit (26), the PWM modulation unit (76) determines the drive signal (DS) and the voltage of each phase (vu , vv, vw) and output. Each signal included in the drive signal (DS) is amplified as necessary and provided to the corresponding switching element of the inverter circuit (30).

  FIG. 7 is a circuit diagram showing a configuration example of the U-phase leg (32U) of FIG. The U-phase circuit will be described below, but the V-phase and W-phase circuits are configured similarly. The operations of the V-phase and W-phase circuits are the same as those of the U-phase circuit except that the phases are different. These points are the same in the following other configuration examples.

  The upper arm switching circuit (34) includes switching elements (41, 42). The lower arm switching circuit (36) includes switching elements (43, 44). The circuit of FIG. 7 is used when the reverse withstand voltage of the switching elements (41-44) is sufficient. Each of the switching elements (41-44) is, for example, an IGBT (insulated gate bipolar transistor). The current (IU) that is the sum of the current (IU1) flowing from the switching circuit (34) to the output node (NU) and the current (IU2) flowing from the switching circuit (36) to the output node (NU) is the motor (94). Flowing into.

  The collector and emitter of the switching element (41) are connected to the node (N1) and the output node (NU), respectively. The signal (S1) is input to the gate as the control terminal of the switching element (41). The collector and emitter of the switching element (42) are connected to the output node (NU) and the node (N1), respectively. The signal (S2) is input to the gate of the switching element (42).

  The collector and emitter of the switching element (43) are connected to the output node (NU) and the node (N3), respectively. The signal (S3) is input to the gate of the switching element (43). The collector and emitter of the switching element (44) are connected to the node (N3) and the output node (NU), respectively. The signal (S4) is input to the gate of the switching element (44).

  FIG. 8 is a graph showing an example of signals (S1-S4) given to the switching elements (41-44) of FIG. 7 and currents (IU1, IU2) flowing through the circuit of FIG. FIG. 8 shows a case where a current of magnitude (II) should be flowed as a phase current (IU) in a period (TU) or a period (TL). The switching elements (41-44) are turned on when the signals (S1-S4) input to the respective gates are at a high potential (H), and are turned off when the signals are at a low potential (L).

  The PWM modulation unit (76) of the drive signal generation unit (60) is connected to the switching circuit (34) when the upper arm switching circuit (34) is turned on to pass the phase current (IU) to the output node (NU). Signals (S1-S4) are generated so that no current flows to the output node (NU) through the lower arm switching circuit (36) in the same leg as in (34). The PWM modulation unit (76) is connected to the same leg as the switching circuit (36) when the lower arm switching circuit (36) is conducting to flow the phase current (IU) from the output node (NU). The signal (S1-S4) is generated so that no current flows from the output node (NU) through the switching circuit (34) of the upper arm in FIG.

  In a period (TL) between time (T1) and time (T2), the signals (S3, S4) are at a high potential. At this time, a current (IU2) flows from the output node (NU) to the node (N3) via the switching element (43). In this period, since the signal (S2) is at a low potential, the switching element (42) is non-conductive. That is, even if the input voltage of the inverter circuit (30) is greatly reduced, the lower arm switching circuit (36) generates a phase current (IU) of magnitude (II) from the output node (NU) to the node (N3). When conducting to flow (period (TL)), the upper arm switching circuit (34) in the same leg as the switching circuit (36) passes through the upper arm switching circuit (34) to the output node. Prevent unwanted current from flowing from (NU) to node (N1).

  Between the time (T2) and the time (T3) is a transition period (TA). During this period, a current flows through the switching element (42) depending on the input voltage of the inverter circuit (30), so that the values of the currents (IU1, IU2) are indefinite values (VR). Between the time (T3) and the time (T4) is a dead time (TD) for preventing a through current. During this period, only a reflux current flows. Between the time (T4) and the time (T5) is a transition period (TB). During this period, a current flows through the switching element (44) depending on the input voltage of the inverter circuit (30), so that the values of the currents (IU1, IU2) are indefinite values (VR).

  In a period (TU) between time (T5) and time (T6), the signals (S1, S2) are at a high potential. At this time, a current (IU1) flows from the node (N1) to the output node (NU) via the switching element (41). During this period, since the signal (S4) is at a low potential, the switching element (44) is non-conductive. In other words, even if the input voltage of the inverter circuit (30) drops significantly, the upper arm switching circuit (34) generates a phase current (IU) of magnitude (II) from the node (N1) to the output node (NU). When conducting to flow (period (TU)), the lower arm switching circuit (36) in the same leg as the switching circuit (34) passes through the lower arm switching circuit (36) to the node (N3 ) To the output node (NU). In each period after time (T6), the same signal (S1-S4) as that in the corresponding period already described is supplied, and thus the description thereof is omitted.

  Thus, according to the circuit of FIG. 7, for example, no current flows through the switching element (42) in the period (TL) between time (T1) and time (T2). In addition, for example, during the period (TU) between time (T5) and time (T6), no current flows through the switching element (44). Therefore, if the input current (Idc) of the inverter circuit (30) is detected by the current detector (28) during these periods, the phase current can be obtained even when the input voltage of the inverter circuit (30) is greatly reduced. Is possible.

  FIG. 9 is a circuit diagram showing another configuration example of the U-phase leg (32U) of FIG. The U-phase leg (232U) in FIG. 9 has an upper arm switching circuit (234) and a lower arm switching circuit (236). The upper arm switching circuit (234) includes switching elements (41, 42) and diodes (46, 47). The lower arm switching circuit (236) includes switching elements (43, 44) and diodes (48, 49).

  Signals (S1-S4) are respectively supplied to the control terminals of the switching elements (41-44) as in the circuit of FIG. The circuit of FIG. 9 operates in substantially the same manner as the circuit of FIG. In the circuit of FIG. 9, diodes (46, 47, 48, 49) are connected in series to the switching elements (41, 42, 43, 44), respectively. For this reason, the reverse withstand voltage of the switching elements (41-44) may not be as large as in the case of the circuit of FIG.

  FIG. 10 is a circuit diagram showing still another configuration example of the U-phase leg (32U) of FIG. The U-phase leg (332U) in FIG. 10 includes an upper arm switching circuit (334) and a lower arm switching circuit (336). The upper arm switching circuit (334) has antiparallel circuits (35A, 35B). The antiparallel circuits (35A, 35B) are connected in series with each other. The lower arm switching circuit (336) has antiparallel circuits (37A, 37B). The antiparallel circuits (37A, 37B) are connected to each other in series.

  The anti-parallel circuit (35A) includes a switching element (41) for supplying current to the output node (NU) and a diode (46) connected in anti-parallel to the switching element (41) for supplying current from the output node (NU). ). The anti-parallel circuit (35B) includes a switching element (42) for supplying current from the output node (NU) and a diode (47) connected in anti-parallel to the switching element (42) and supplying current to the output node (NU). ).

  The anti-parallel circuit (37A) includes a switching element (43) that supplies current from the output node (NU) and a diode (48) that is connected in anti-parallel to the switching element (43) and supplies current to the output node (NU). ). The anti-parallel circuit (37B) includes a switching element (44) for supplying current to the output node (NU) and a diode (49) connected in anti-parallel to the switching element (44) for supplying current from the output node (NU). ).

  Signals (S1-S4) are respectively supplied to the control terminals of the switching elements (41-44) as in the circuit of FIG. The circuit of FIG. 10 operates in substantially the same manner as the circuit of FIG. In the circuit of FIG. 10, since the diode (46) is connected in antiparallel to the switching element (41), the reverse withstand voltage of the switching element (41) does not have to be as high as that of the circuit of FIG. . Similarly, since the diodes (47, 48, 49) are connected in antiparallel to the switching elements (42, 43, 44), the reverse withstand voltage of the switching elements (42, 43, 44) is shown in FIG. It may not be as large as in the case of this circuit.

  FIG. 11 is a circuit diagram showing still another configuration example of the U-phase leg (32U) of FIG. The U-phase leg (432U) in FIG. 11 has an upper arm switching circuit (434) and a lower arm switching circuit (436). The upper arm switching circuit (434) includes a switching element (41) and a current limiting circuit (56) connected in antiparallel thereto. The current limiting circuit (56) includes a diode (47) and a resistor (57) connected in series with the diode (47), and limits the current from the output node (NU) to flow to the node (N1).

  The lower arm switching circuit (436) includes a switching element (43) and a current limiting circuit (58) connected in antiparallel thereto. The current limiting circuit (58) includes a diode (49) and a resistor (59) connected in series to the diode (49), and restricts a current from the node (N3) to the output node (NU).

  Signals (S1, S3) are applied to the control terminals of the switching elements (41, 43), as in the circuit of FIG. The resistance value of the current limiting circuit (56) when the return current flows through the current limiting circuit (56) is, for example, about 10 times the resistance value when the switching element (41) is conductive. The resistance value of the current limiting circuit (58) when the return current flows through the current limiting circuit (58) is, for example, about 10 times the resistance value when the switching element (43) is conductive.

  In the circuit of FIG. 11, since the resistance value of the current limiting circuit (58) is relatively large, the upper arm switching circuit (434) is conducting to flow the phase current (IU) to the output node (NU). In addition, the lower arm switching circuit (436) in the same leg as the switching circuit (434) limits the current flowing through the switching circuit (436) to the output node (NU). In addition, since the resistance value of the current limiting circuit (56) is relatively large, the switching circuit (436) when the lower arm switching circuit (436) is conducting to flow the phase current (IU) from the output node (NU). The upper arm switching circuit (434) in the same leg as (436) limits the current flowing from the output node (NU) through the switching circuit (434). For this reason, even when the input voltage of the inverter circuit (30) decreases, the phase current of the motor (94) driven by the inverter circuit (30) can be obtained more correctly.

  Although the case where the current is detected only at one place has been described above, more current may be detected. FIG. 12 is a block diagram illustrating another configuration example of the power conversion device in FIG. 5. The power conversion device (200) of FIG. 12 is configured in the same manner as the power conversion device (100) of FIG. 5 except that a current detection unit (228) is provided instead of the current detection unit (28). The current detector (228) has a resistor (29U, 29V).

  The resistor (29U) is connected between the switching circuit (36) of the lower arm of the U-phase leg (32U) and the node (N2). The resistor (29V) is connected between the switching circuit of the lower arm of the V-phase leg (32V) and the node (N2). The current detector (228) detects the current flowing through the resistor (29U, 29V). Specifically, the current detection unit (228) converts the voltage of the resistor (29U, 29V) into a value of a current flowing through each resistor, and the result is detected as a detected current value (ic). Output to the three-phase / two-phase converter (64) of 60). By using the signals (S1-S4) as shown in FIG. 8, the phase currents of the U phase and the V phase are obtained, and the sum of the phase currents of the U phase, the V phase, and the W phase is zero. Phase current is required.

  In FIG. 12, the resistor (29V) may be connected between the switching circuit of the lower arm of the W-phase leg (32W) and the node (N2) instead of the V-phase. In FIG. 12, the resistor (29U) may be connected between the switching circuit of the lower arm of the W-phase leg (32W) and the node (N2) instead of the U-phase. The current detection unit (228) may output the voltages of the two resistors, and the three-phase / two-phase conversion unit (64) may obtain the current value of each resistor from these voltages.

  FIG. 13 is a block diagram illustrating still another configuration example of the power conversion device in FIG. 5. The power conversion device (300) of FIG. 13 is configured in the same manner as the power conversion device (100) of FIG. 5 except that a current detection unit (328) is provided instead of the current detection unit (28). The current detection unit (328) has resistors (29U, 29V, 29W).

  The resistor (29U) is connected between the switching circuit (36) of the lower arm of the U-phase leg (32U) and the node (N2). The resistor (29V) is connected between the switching circuit of the lower arm of the V-phase leg (32V) and the node (N2). The resistor (29W) is connected between the switching circuit of the lower arm of the W-phase leg (32W) and the node (N2). The current detector (328) detects the current flowing through the resistor (29U, 29V, 29W). Specifically, the current detection unit (328) converts the voltage of the resistor (29U, 29V, 29W) into the value of the current flowing through each resistor, and generates the drive signal as the detected current value (ic) Output to the three-phase / two-phase conversion section (64) of the section (60). By using the signals (S1-S4) as shown in FIG. 8, the phase currents of the U phase, the V phase, and the W phase are obtained. The current detector (328) may output the voltages of the three resistors, and the three-phase / two-phase converter (64) may obtain the current value of each resistor from these voltages.

  The capacitor (24) in the above power converters (100, 200, 300) may have a larger capacity. Even if the capacitor (24) has a capacity that can sufficiently smooth the input voltage of the inverter circuit (30), the input voltage of the inverter circuit (30) is increased due to the voltage drop of the AC power supply (92). May decrease. Even in such a case, the power conversion device (100, 200, 300) can more accurately determine the phase current output from the inverter circuit (30).

  In the above embodiment, the case where the IGBT is used as the switching element (41-44) has been described. Instead of this, if possible, a MOSFET (metal oxide semiconductor field-effect transistor), a bipolar transistor, or the like is used. It may be used.

  Each functional block in this specification may typically be realized by hardware. Alternatively, some or all of each functional block can be implemented in software. For example, such a functional block can be realized by a processor and a program executed on the processor. In other words, each functional block described in the present specification may be realized by hardware, may be realized by software, or may be realized by any combination of hardware and software.

  The above embodiments are essentially preferable examples, and are not intended to limit the scope of the present invention, its application, or its use.

  As described above, the present invention is useful for power converters and the like.

16 Converter circuit
24 capacitors
28, 228, 328 Current detector
30 Inverter circuit
32U, 32V, 32W, 232U, 332U, 432U leg
34, 234, 334, 434, 36, 236, 336, 436 Switching circuit
35A, 35B, 37A, 37B reverse parallel circuit
41-44 Switching element
46-49 Diode
56, 58 Current limit circuit
60 Drive signal generator
100, 200, 300 Power converter

Claims (5)

A converter circuit (16) that rectifies and converts the alternating current from the alternating current power source (92) to direct current;
An inverter circuit (30) for converting the direct current output from the converter circuit (16) into an alternating current based on the drive signal and outputting the alternating current;
A capacitor (24) connected between output nodes of the converter circuit (16);
A current detector (28) for detecting a current between the converter circuit (16) and the inverter circuit (30);
A drive signal generator (60) that generates the drive signal based on the current detected by the current detector (28);
The inverter circuit (30) has a plurality of legs (32U, 32V, 32W; 232U; 332U ) ,
The plurality of legs (32U, 32V, 32W; 232U; 332U )
Upper arm switching circuit (34; 234; 33 4) ,
A lower arm switching circuit (36; 236; 33 6) connected in series to the upper arm switching circuit (34; 234; 33 4) ,
The upper arm switching circuit (34; 234; 334)
A first switching circuit for controlling a current to an output node of the leg between the upper arm switching circuit (34; 234; 334) and the lower arm switching circuit (36; 236; 336);
A second switching circuit for controlling a current from the output node of the leg,
The lower arm switching circuit (36; 236; 336)
A third switching circuit for controlling the current from the output node of the leg;
A power conversion device comprising: a fourth switching circuit that controls a current to the output node of the leg . In claim 1 ,
It said first switching circuit includes a first switching element (41),
Said second switching circuit includes a second switching element connected in parallel with said first switching element (41) (42),
The third switching circuit has a third switching element (43),
The fourth switching circuit, power conversion device, characterized in that it comprises a fourth switching element (44) connected in parallel to the third switching element (43). In claim 2 ,
Said first switching circuit further includes a first diode (46) connected in series with said first switching element (41),
The second switching circuit further includes a second diode (47 ) connected in series to the second switching element (42),
The third switching circuit further comprises a third diode (48) connected in series with the third switching element (43),
The fourth switching circuit further includes a fourth diode (49 ) connected in series to the fourth switching element (44). In claim 1,
The first switching circuit includes:
A first switching element (41);
A first diode (47) connected in series to the first switching element (41);
The second switching circuit includes:
A second switching element (42);
A second diode (46) connected in series to the second switching element (42);
The node between the first switching element (41) and the first diode (47) is the same as the node between the second switching element (42) and the second diode (46).
The third switching circuit includes:
A third switching element (43);
A third diode (49) connected in series to the third switching element (43);
The fourth switching circuit includes:
A fourth switching element (44);
A fourth diode (48) connected in series to the fourth switching element (44);
A node between the third switching element (43) and the third diode (49) is common with a node between the fourth switching element (44) and the fourth diode (48). A power conversion device characterized by the above. In claim 1,
The said capacitor | condenser (24) smoothes the input voltage of the said inverter circuit (30) so that it may pulsate according to the voltage of the said AC power supply (92), The power converter device characterized by the above-mentioned.

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