JP6326235B2 - Power conversion conversion and power conversion method - Google Patents

Description

The present invention relates to a power conversion device and a power conversion method, and more particularly to a power conversion device and a power conversion method suitable for dealing with anti-bias resistance of a transformer.

  In recent years, power converters are used in many technical fields. This power converter will be described by taking as an example a modular multilevel cascade converter (MMCC) known in the field of handling high voltages.

An MMCC is an “arm” configured by connecting a plurality of unit converters in series with a bidirectional chopper circuit or full bridge circuit as a unit converter (hereinafter referred to as an “arm” as a series circuit of one or more unit converters). A voltage-type power conversion circuit (hereinafter referred to as a voltage-type power conversion circuit) that can directly output a high voltage that is close to a sine wave and that exceeds the breakdown voltage of the semiconductor switching element used inside the unit converter. Simply referred to as a conversion circuit).

  Non-Patent Document 1 classifies the four methods of MMCC and discloses the features and applicability of each method.

  For example, Non-Patent Document 1 describes two of the four methods, namely, MMCC-SSBC (single-star bridge cells) and MMCC-SDBC (single-delta bridge cells) as methods suitable for STATCOM. ing.

  The MMCC-SSBC is a system in which three arms configured by connecting a full bridge circuit in series as a unit converter are Y-connected.

On the other hand, the MMCC-SDBC is a system in which three circuits in which the arm and the reactor are connected in series are Δ-connected.

H. Akagi, “Classification, terminology, and application of the modular multilevel cascade converter (MMCC),” IEEE Transactions on Power Electronics, vol. 26, no. 11, Nov. 2011, pp. 3119-3129.

  In order to explain the bias of the transformer used in the power converter, for example, when taking a conversion circuit such as MMCC and connecting it to a power transmission / distribution system (hereinafter referred to as an AC system) as STATCOM, Generally, a transformer is installed between the AC system and the conversion circuit. By installing the transformer, it is possible to ensure voltage step-up / step-down and electrical insulation.

  In this case, the output voltage of the conversion circuit is applied to the winding of the transformer, but it is preferable that the voltage contains only an AC component and no DC component.

  Thus, not only in STATCOM using the MMCC technology, in a power converter using a wide transformer, when a DC voltage is applied to the winding of the transformer, a current proportional to the time integral of the DC voltage is applied. Flows into the windings and generates a DC component in the magnetic flux density of the transformer core.

  In this specification, the generation of a DC component in the magnetic flux density of the transformer core is referred to as DC magnetization.

  If excessive DC bias is generated, the magnetic flux density of the transformer core approaches or exceeds the saturation magnetic flux density of the iron core material, which hinders normal operation as a transformer.

  In this specification, the permissible value of the direct current component of the current flowing through the winding of the transformer is referred to as a biased magnetic resistance.

  In order to prevent excessive DC bias, the output voltage of the converter circuit and the current flowing between the converter circuit and the transformer are detected by a sensor, etc., and the voltage and current contain only AC components, Although a method of performing feedback control so that it does not contain is also conceivable, if there is an offset error in the detection value of the sensor or the means for performing the feedback control, there is still a possibility that excessive DC bias is generated. There is.

  Therefore, for transformers installed between the AC system and the converter circuit, it is common to use transformers with increased demagnetization resistance by enlarging the cross-sectional area of the core, assuming the existence of the aforementioned offset errors, etc. Met.

  Thus, the transformer with increased magnetic resistance has a large iron core cross-sectional area, which increases the volume, weight, and installation area of the entire power converter.

An object of the present invention is to provide a power conversion device and a power conversion method capable of withstanding anti-magnetization of a transformer without increasing volume, weight, and installation area.

  To achieve the above object, the present invention provides a first capacitor, a second capacitor, and a first switching element capable of outputting the voltage of the first capacitor to a circuit passing through a winding of a transformer. And a second switching element capable of outputting the voltage of the second capacitor, and when a DC component current flows in a circuit passing through the winding of the transformer, the second switching element is attenuated. The first switching element and the second switching element are configured to operate.

  Alternatively, three series circuits of an arm and a reactor constituted by connecting one or more unit converters of at least two terminals each including a capacitor and a switching element in series are Δ-connected, and the Δ-connected points are transformed. When the power conversion operation is performed by connecting to the converter, the current flowing in the arm must flow through one of the capacitors of the unit converter.

  Alternatively, three arms composed of one or more unit converters each having at least two terminals including a capacitor and a switching element are connected in series, and the Y-connected points are connected to a transformer. During the conversion operation, the current flowing through the arm is sure to flow through one of the unit converter capacitors.

  Alternatively, a plurality of legs connected in parallel with two series circuits of an arm and a reactor configured by connecting in series one or more unit converters of at least two terminals each having an energy storage element and a switching element. The additional unit converter is arranged in the path between the two series-connected points in the series circuit and the transformer, and the additional unit converter is configured so that the current flowing through the transformer always flows through one of the capacitors. did.

  Alternatively, three series circuits of an arm and a reactor constituted by connecting one or more unit converters of at least two terminals each including a capacitor and a switching element in series are Δ-connected, and the Δ-connected points are transformed. At least one of the unit converters is configured to be configured such that the current flowing through the arm flows through the capacitor of the unit converter regardless of the on / off state of the switching element.

  Alternatively, at least two terminal converters each having a capacitor and a switching element are connected in series with one or more three arms, and Y-connected, and the Y-connected point is connected to a transformer. At least one of the converters is configured such that the current flowing through the arm flows through the capacitor of the unit converter regardless of the on / off state of the switching element.

Alternatively, a plurality of legs connected in parallel with two series circuits of an arm and a reactor configured by connecting in series one or more unit converters of at least two terminals each having an energy storage element and a switching element. In the power converter, an additional unit converter is arranged in a path between two series-connected points of the series circuit and the transformer, and the unit converter has a current flowing through the arm regardless of the on / off state of the switching element. The unit converter was configured to flow.

1st form of the power converter device by this invention Half-bridge type unit converter Full-bridge type unit converter 2nd form of the power converter device by this invention 3rd form of the power converter device by this invention Double half bridge type unit converter 4th form of the power converter device by this invention 5th form of the power converter device by this invention Bidirectional chopper type unit converter Schematic waveform of half-bridge type unit converter 1 Schematic waveform of half-bridge unit converter 2 Schematic waveform of half-bridge unit converter 3 Control block diagram for correcting the output voltage command value based on the capacitor voltage Control block diagram for correcting the current detection value based on the capacitor voltage Control block diagram for correcting the current command value based on the capacitor voltage

  A first embodiment of the present invention will be described.

  The first embodiment is a power conversion device in which three series circuits of an arm and a reactor configured by connecting one or a plurality of unit converters in series are Δ-connected and linked to an AC system via a transformer. STATCOM is connected to the AC system.

  The feature of the first embodiment is that at least one of the unit converters included in each arm is a half-bridge circuit.

  In other words, among the unit converters used in the MMCC-SDBC described in Non-Patent Document 1, at least one of the unit converters included in each arm is changed from a full bridge circuit to a half bridge circuit. This is a replacement configuration.

  According to the present embodiment, it is possible to obtain an effect that it is possible to prevent excessive DC bias of the transformer with a simple circuit configuration.

  Hereinafter, after describing the overall configuration of the first embodiment, the configuration of the unit converter, the output voltage and current path of the unit converter will be described, and the operation of the control means for synthesizing the output voltage as the arm will be described. In addition, it will be explained that the power conversion device of the present invention functions as STATCOM, and finally, the principle by which the present invention can prevent DC bias of the transformer.

  First, the overall configuration of the first embodiment will be described with reference to FIG.

  The power conversion device 104 is connected to the interconnection bus 103 via the transformer 105. A system impedance 102 exists between the interconnection bus 103 and the AC system 101.

  Hereinafter, the internal configuration of the power conversion device 104 will be described.

  The power converter 104 includes a reactor 106 and an arm 107 uv series circuit, a reactor 106 and an arm 107 vw series circuit, and a reactor 106 and an arm 107 wu series circuit at Δ points U, V, and W shown in FIG. This is a connected configuration.

  In the present specification, the arms 107uv, vw, and wu are collectively referred to as “arm 107” unless it is necessary to distinguish between them.

  Each arm 107 is a series circuit of a half bridge type unit converter 108 and a full bridge type unit converter 109. The internal configuration of the half bridge type unit converter 108 and the full bridge type unit converter 109 will be described later.

  A feature of the present invention is that a half-bridge type unit converter is used for each arm 107.

  In the following, a case will be described in which each arm 107 includes one half-bridge type converter 108 and a plurality of full-bridge type unit converters 109 as illustrated in FIG. 1 as an example.

  However, the number of half-bridge type unit converters 108 included in each arm 107 is not necessarily one, and the effect of the present invention can be obtained even if there are a plurality of half-bridge type unit converters 108. Furthermore, even when each arm 107 includes only the half-bridge type unit converter 108 and does not include the full-bridge type unit converter 109, the effect of the present invention can be obtained.

  In this embodiment, the total of the number of half-bridge type unit converters 108 and the number of full-bridge type unit converters 109 is expressed as N.

  In this specification, when it is not necessary to distinguish between them, the half-bridge unit converter 108 and the full-bridge unit converter 109, and a double half-bridge unit converter 503, which will be described later with reference to FIGS. The bidirectional chopper type unit converter 804 is simply referred to as a “unit converter”.

  The operation principle of the power conversion device 104 and the central control unit 110, the transmission communication line 111, and the reception communication line 112 will be described after the internal configuration of the unit converters 108 and 109 is described.

  Hereinafter, the voltage and current of each part depicted in FIG. 1 are defined.

  The phases of AC system 101 and interconnection bus 103 are referred to as A phase, B phase, and C phase, the line voltage of AC system 101 is represented as VSab, VSbc, and VSca, and the line voltage of interconnection bus 103 is represented by VRab. , VRbc, VRca.

  Further, currents flowing from the interconnection bus to the power converter 104 are denoted as Ia, Ib, and Ic.

  The phases on the arm 107 side of the transformer 105 are referred to as U phase, V phase, and W phase, and currents flowing from the transformer 105 to the U point, V point, and W point are denoted as IU, IV, and IW.

  Furthermore, the output voltages of the arms 107uv, vw, and wu are denoted as Vuv, Vvw, and Vwu, respectively, and the currents flowing through the arms 107uv, vw, and wu are denoted as Iuv, Ivw, and Iwu, respectively.

  Hereinafter, the internal configuration of the half-bridge unit converter 108 will be described with reference to FIG.

  The anti-parallel circuit of the X-phase upper switching element 201XP and the X-phase upper free-wheeling diode 202XP and the anti-parallel circuit of the X-phase lower switching element 201XN and the X-phase lower free-wheeling diode 202XN are connected in series at the point x. This is referred to as a first series circuit.

  The half-bridge unit converter 108 includes two capacitors, an upper capacitor 203P and a lower capacitor 203N, as energy storage elements.

  The upper capacitor 203P and the lower capacitor 203N are connected in series at m points. This is referred to as a second series circuit.

  The half-bridge type unit converter 108 has a configuration in which the first and second series circuits are connected in parallel at the p point and the n point.

  Hereinafter, the voltage / current in the half-bridge type unit converter 108 is defined.

  The voltage at the point x with respect to the point m is referred to as the output voltage of the half-bridge unit converter 108 and is denoted as Vjk.

  Here, j represents the arm 107 to which the half bridge unit converter 108 belongs, and j = uv, vw, wu. K represents a number in the arm 107 of the half bridge unit converter 108, and k = 1, 2,. Hereinafter, in this specification, j and k added to each voltage of the unit converter have the same meaning.

  The voltage of the upper capacitor 203P is expressed as VCPjk, and the voltage of the lower capacitor 203N is expressed as VCNjk.

  In the present specification, unless it is particularly necessary to distinguish, the X-phase upper switching element 201XP, the X-phase lower switching element 201XN in FIG. 2 and other unit converters described later (see FIGS. 3, 6, and 9). The switching elements 201XP, XN, YP, and YN used for reference) are also simply referred to as “switching element 201”.

  Further, in the present specification, when there is no need to distinguish between them, the X-phase upper freewheeling diode 202XP, the X-phase lower freewheeling diode 202XN in FIG. 2 and other unit converters described later (FIGS. 3, 6 and 6). 9), the free-wheeling diodes 202XP, XN, YP, and YN used in FIG.

  2, FIG. 3, FIG. 6 and FIG. 9, the IGBT (insulated-gate bipolar transistor) symbol is drawn as the switching element. However, the present invention is not limited to this, and the on / off control type switching is performed. If it is an element, other types of switching elements such as BJT (bipolar junction transistor), MOSFET (metal-oxide-semiconductor field-effect transistor), GTO (gate turn-off) thyristor, IGCT (integrated gate-commutated thyristor), etc. The effect of the present invention can also be obtained when using.

  Hereinafter, the relationship between the on / off state of the switching element and the output voltage Vjk will be described. A path through which the current Ij flows will also be described.

  When the X-phase upper switching element 201XP is on and the X-phase lower switching element 201XN is off, the voltage at the point x with respect to the point m is substantially equal to the voltage VCPjk of the upper capacitor 203P. That is, Vjk = VCPjk. In this case, the current Ij flowing through the unit converter flows through the upper capacitor 203P.

  When the X-phase upper switching element 201XP is off and the X-phase lower switching element 201XN is on, the voltage at the x point with respect to the m point is approximately equal to the voltage VCNjk of the lower capacitor 203P, and The voltage has a reverse polarity. That is, Vjk = −VCNjk. In this case, the current Ij flowing through the unit converter flows through the lower capacitor 203N.

  From the above, it can be seen that the output voltage Vjk of the half-bridge unit converter 108 can be controlled by controlling on / off of the switching element.

  In the half-bridge unit converter 108, it can be seen that the current Ij passes through one of the capacitors 203P and N regardless of the on / off state of the switching element.

  The half-bridge type unit converter 108 includes half-bridge type unit converter control means 204, the operation of which will be described later.

  Hereinafter, the internal configuration of the full-bridge unit converter 109 will be described with reference to FIG.

  The anti-parallel circuit of the X-phase upper switching element 201XP and the X-phase upper free-wheeling diode 202XP and the anti-parallel circuit of the X-phase lower switching element 201XN and the X-phase lower free-wheeling diode 202XN are connected in series at the point x. This is referred to as a first series circuit.

  The anti-parallel circuit of the Y-phase upper switching element 201YP and the Y-phase upper circulating diode 202YP and the anti-parallel circuit of the Y-phase lower switching element 201YN and the Y-phase lower circulating diode 202XN are connected in series at the y point. This is referred to as a second series circuit. The full bridge type unit converter 109 includes a capacitor 203 as an energy storage element.

  The full-bridge unit converter 109 has a configuration in which the first and second series circuits and the capacitor 203 are connected in parallel at the p point and the n point.

  Hereinafter, the voltage / current in the full-bridge unit converter 109 is defined.

  The voltage at point x with respect to point y is referred to as the output voltage of full-bridge unit converter 109 and is denoted as Vjk.

  In addition, the voltage of the capacitor 203 is expressed as VCjk.

  Hereinafter, the relationship between the on / off state of the switching element and the output voltage Vjk will be described. A path through which the current Ij flows will also be described.

  When the X-phase upper switching element 201XP is on, the X-phase lower switching element 201XN is off, the Y-phase upper switching element 201YP is on, and the Y-phase lower switching element 201YN is off, The voltage is almost zero. That is, Vjk = 0. In this case, the current Ij flowing through the unit converter does not pass through the capacitor 203.

  When the X-phase upper switching element 201XP is on, the X-phase lower switching element 201XN is off, the Y-phase upper switching element 201YP is off, and the Y-phase lower switching element 201YN is on, The voltage is approximately equal to the voltage VCjk of the capacitor 203. That is, Vjk = VCjk. In this case, the current Ij flowing through the unit converter passes through the capacitor 203.

  When the X-phase upper switching element 201XP is off, the X-phase lower switching element 201XN is on, the Y-phase upper switching element 201YP is on, and the Y-phase lower switching element 201YN is off, The voltage is approximately equal in magnitude to the voltage VCjk of the capacitor 203 and has a reverse polarity. That is, Vjk = −VCjk. In this case, the current Ij flowing through the unit converter passes through the capacitor 203.

  When the X-phase upper switching element 201XP is off, the X-phase lower switching element 201XN is on, the Y-phase upper switching element 201YP is off, and the Y-phase lower switching element 201YN is on, The voltage is almost zero. That is, Vjk = 0. In this case, the current Ij flowing through the unit converter passes through the capacitor 203.

  From the above, it can be seen that the output voltage Vjk of the full-bridge unit converter 109 can be controlled by controlling on / off of the switching element.

  Further, in the full-bridge unit converter 109, there are cases where the current Ij passes through the capacitor 203 and does not pass depending on the on / off state of the switching element.

  On the other hand, as described above, in the half-bridge unit converter 108, the current Ij always passes through one of the capacitors 203P and N.

  This is one of the differences between the half bridge type unit converter 108 and the full bridge type unit converter 109.

  In other words, focusing on the current Ij of the arm 107, the current Ij flowing through the arm 107 always passes through at least one capacitor included in the arm 107.

  In the present embodiment and FIG. 1, the case where the half-bridge unit converter 108 is used is described, but the present invention is not limited to this, and the current flowing through each arm is at least one power of a capacitor or the like. If the storage element always passes, the same effect as in this embodiment can be obtained.

  Hereinafter, the control means of the power converter 104 will be described. A method of synthesizing the output voltages Vuv, Vvw, Vwu of the arms 107uv, vw, wu by the control means will be described.

  The central control means 110 sends, for example, gate signals gjk (j = uv, vw, wu, k = 1, 2,..., N) to the unit converters 108 and 109 via the transmission communication path 111. Send.

  Each of the unit converters 108 and 109 controls on / off of each switching element based on gjk received from the central control unit 110, and controls the output voltage Vjk.

  Further, the central control means 110 receives the capacitor voltage VCjk (j = uv, vw, wu, detected from the unit converters 108 and 109 via the reception communication path 112, for example, via the voltage detection means 205P and N, for example. The detection value of k = 1, 2,..., N) is received.

  The transmission communication path 111 and the reception communication path 112 are, for example, communication paths such as electric wires, optical fibers, or radio.

  The output voltages Vuv, Vvw, and Vwu of each arm 107 are the sum of the output voltages Vjk of the unit converters 108 and 109 that constitute each arm 107. Therefore, the output voltages Vuv, Vvw, Vwu as the arm 107 can be synthesized by controlling Vjk by the operation of the control means described above.

  For example, by applying phase shift PWM (pulse-width modulation) as disclosed in Non-Patent Document 1, Vuv, Vvw, and Vwu can be made into multilevel voltage waveforms that are close to sine waves.

  Hereinafter, the principle that the power converter 104 functions as STATCOM will be described. For the sake of simplicity, description will be made assuming that the turns ratio of the transformer 105 is 1: 1 and that there is no phase shift between the interconnecting bus 103 side and the arm 107 side.

  In the following, only the fundamental wave components of the output voltages Vuv, Vvw, and Vwu of each arm will be described, and the harmonic components will be ignored for the sake of simplicity.

  First, the principle by which the power converter 104 outputs capacitive reactive power will be described.

  By the operation of the control means described above, the output voltages Vuv, Vvw, Vwu of each arm 107 are controlled to have the same phase as the line voltages VRab, VRbc, VRca of the interconnection bus 103 and a larger amplitude. .

  In this case, the voltage applied to the leakage inductance of the reactor 106 and the transformer 105 is a voltage having a phase opposite to the line voltages VRab, VRbc, VRca of the interconnection bus 103.

  When a sinusoidal steady state is assumed, the current flowing through the leakage inductance of the reactor 105 and the transformer 105 is delayed by 90 ° from the applied voltage.

  In this case, the currents Iuv, Ivw, and Iwu flowing through the arms 107uv, vw, and wu are voltages that are delayed by 90 ° from the voltages that are in reverse phase with VRab, VRbc, and VRca, in other words, only 90 ° from VRab, VRbc, and VRca. The current is advanced in phase.

  Further, the currents Ia, Ib, Ic flowing from the interconnection bus 103 to the power converter 104 become currents whose phases are advanced by 90 ° from the phase voltages VRa, VRb, VRc of the interconnection bus 103.

  Further, the currents Iuv, Ivw, Iwu and Ia, Ib, Ic are controlled by controlling the difference in amplitude between the line voltages VRab, VRbc, VRca of the interconnection bus 103 and the output voltages Vuv, Vvw, Vwu of each arm 107. Can be controlled. In other words, the amount of capacitive reactive power can be controlled.

  Next, the principle that the power conversion device 104 outputs inductive reactive power will be described.

  By the operation of the aforementioned control means, the output voltages Vuv, Vvw, Vwu of each arm 107 are controlled to have the same phase as the line voltages VRab, VRbc, VRca of the interconnection bus 103 and a smaller amplitude. .

  In this case, the voltage applied to the leakage inductance of the reactor 106 and the transformer 105 is a voltage having the same phase as the line voltages VRab, VRbc, VRca of the interconnection bus 103.

  When a sinusoidal steady state is assumed, the current flowing through the leakage inductance of the reactor 105 and the transformer 105 is delayed by 90 ° from the applied voltage.

  In this case, the currents Iuv, Ivw, and Iwu flowing through the arms 107uv, vw, and wu are currents that are delayed in phase by 90 ° from VRab, VRbc, and VRca.

  In addition, currents Ia, Ib, and Ic that flow from interconnection bus 103 to power conversion device 104 are currents that are delayed in phase by 90 ° from phase voltages VRa, VRb, and VRc of interconnection bus 103.

  From the above, it can be seen that the power converter 104 can output inductive reactive power.

  Further, the currents Iuv, Ivw, Iwu and Ia, Ib, Ic are controlled by controlling the difference in amplitude between the line voltages VRab, VRbc, VRca of the interconnection bus 103 and the output voltages Vuv, Vvw, Vwu of each arm 107. Can be controlled. In other words, the amount of capacitive reactive power can be controlled.

  From the above, by controlling the magnitude relationship between the line voltages VRab, VRbc, VRca of the interconnection bus 103 and the amplitudes of the output voltages Vuv, Vvw, Vwu of each arm 107, the power converter 104 is capacitive or inductive. It can be seen that the reactive power can be output arbitrarily and the magnitude can be controlled arbitrarily. In other words, the power conversion device 104 functions as STATCOM.

  In the above description, the case where the three arms 107uv, vw, and wu output reactive power having the same magnitude has been described. However, the magnitude relationship between the amplitudes of VRab and Vuv, the magnitude relationship between the amplitudes of VRbc and Vvw, and VRca. It is also possible for the three arms 107uv, vw, and wu to output different reactive powers by individually controlling the magnitude relationship between the amplitudes of VRw and VRwu.

  Next, a principle that can prevent excessive DC bias of the transformer 105 by providing the half-bridge type unit converter 108 in the arm 107, which is a feature of the present invention, will be described.

  First, a schematic waveform of the output voltage Vjk of the half-bridge type unit converter 108 when the voltage VCPjk of the upper capacitor 203P is equal to the voltage VCNjk of the lower capacitor 203N (VCPjk = VCNjk) will be described with reference to FIG. To do.

  FIG. 10 shows a case where a pulse train of Vjk is generated by PWM, for example, so that the fundamental wave component becomes Vjkfund.

  When VCPjk = VCNjk as shown in FIG. 10, Vjk contains the fundamental wave component Vjkfund but no DC component.

  As described above, in the half-bridge unit converter 108, the arm current Ij (j = uv, vw, wu) always passes through either the upper capacitor 203P or the lower capacitor 203N.

  By the way, when the transformer 105 is DC-magnetized, the arm current Ij contains a DC component. Therefore, if the DC component contained in Ij can be attenuated, excessive DC bias can be prevented.

  If the current Ij (j = uv, vw, wu) contains the DC component Ijdc and Ijdc> 0, Ijdc charges the upper capacitor 203P depending on the on / off state of the switching element, Alternatively, it takes either path of discharging the lower capacitor 203N.

  In other words, VCPjk rises and VCNjk falls due to the positive DC component Ijdc. Therefore, VCPjk> VCNjk. This will be described later with reference to FIG.

  Further, when the current Ij contains the DC component Ijdc and Ijdc <0, Ijkdc discharges the upper capacitor 203P or charges the lower capacitor 203N depending on the on / off state of the switching element. Take either route.

  In other words, VCPjk decreases and VCNjk increases due to the negative DC component Ijdc. Therefore, VCPjk <VCNjk. This will be described later with reference to FIG.

  When VCPjk> VCNjk is satisfied by positive Ijkdc, the schematic waveform shown in FIG. 10 changes as shown in FIG.

  Since VCPjk> VCNjk, the magnitude of the positive voltage pulse of Vjk is larger than that of the negative voltage pulse. Therefore, Vjk contains a positive DC component Vjkdc in addition to the fundamental wave component Vjkfund.

When the DC component Vjkdc of the output voltage of the unit converter 108 is positive (Vjkdc> 0), the voltage has a polarity that hinders the positive DC component (Ijdc> 0) of the arm current Ij.

In summary, a positive Vjkdc is generated by the positive DC component Ijdc of Ij, and the generated positive Vjkdc attenuates the positive Ijdc.

  Further, when VCPjk <VCNjk due to negative Ijdc, the schematic waveform shown in FIG. 10 changes as shown in FIG.

  Since VCPjk <VCNjk, the magnitude of the positive voltage pulse of Vjk is smaller than that of the negative voltage pulse. Therefore, Vjk contains a negative DC component Vjkdc in addition to the fundamental wave component Vjkfund.

When the DC component Vjkdc of the output voltage of the unit converter 108 is negative (Vjkdc <0), the voltage has a polarity that hinders the negative DC component (Ijdc <0) of the arm current Ij.

In summary, a negative Vjkdc is generated by the negative DC component Ijdc of Ij, and the generated negative Vjkdc attenuates the negative Ijdc.

From the above, it can be seen that the capacitors 203P, N included in the half-bridge type unit converter 108 can attenuate either the positive or negative DC component Ijkdc of the arm current Ij by charging / discharging thereof.

Therefore, excessive direct current bias of the transformer 105 can be prevented.

  As described above, the advantage of the half-bridge type unit converter 108 is that the current flowing through the arm 107 always passes through at least one capacitor, thereby preventing an excessive DC bias of the transformer 105. It is done.

  In the above description, the case where the series circuit of the three arms 107 and the reactor 106 is Δ-connected (FIG. 1) has been described as an example.

  As shown in FIG. 4, the present invention can be applied to a case where three arms are Y-connected, and similar effects can be obtained.

  4 shows a circuit diagram in which the arms 107u, v, w and the transformer 105 are directly connected, but a reactor may be provided between the arms 107u, v, w and the transformer 105. Similar effects can be obtained.

  A second embodiment of the present invention will be described.

  In the second embodiment, as in the first embodiment, three series circuits of an arm and a reactor configured by connecting one or more unit converters in series are connected by Δ and connected to an AC system via a transformer. It is a power conversion device to be connected, and is connected to an AC system as STATCOM.

  A feature of the second embodiment is that at least one of the unit converters included in each arm is a double half bridge circuit in which two half bridge circuits are connected in reverse series.

  In other words, among the unit converters used in the MMCC-SDBC described in Non-Patent Document 1, at least one of the unit converters included in each arm is replaced with a double half bridge circuit. It is.

  According to the present embodiment, as in the first embodiment, it is possible to obtain an effect that it is possible to prevent excessive DC bias of the transformer with a simple circuit configuration.

  Further, in a unit converter using a double half bridge circuit (hereinafter referred to as a double half bridge type unit converter), it is approximately twice as large as the half bridge type unit converter 108 (substantially the same as the full bridge type unit converter 109). The effect of being able to output the voltage of

  Hereinafter, after describing the overall configuration of the first embodiment, the configuration of the unit converter, the output voltage and current path of the unit converter will be described, and the operation of the control means for synthesizing the output voltage as the arm will be described. In addition, it will be explained that the power conversion device of the present invention functions as STATCOM, and finally, the principle by which the present invention can prevent DC bias of the transformer.

  First, the overall configuration of the first embodiment will be described with reference to FIG. 5, but only the differences of the first embodiment from FIG. 1 will be described.

  The power converter 501 shown in FIG. 5 of the present embodiment is characterized in that each arm 502 uv, vw, wu includes at least one double half bridge unit converter 503, unlike FIG. 1.

  The double half bridge type unit converter 503 is a circuit in which two half bridge circuits are connected in reverse series, and details will be described later with reference to FIG.

  The principle that the power converter 501 in this embodiment functions as STATCOM and the principle that the DC component Ijdc of the arm current Ij can be attenuated to prevent the transformer 105 from being demagnetized are substantially the same as in the first embodiment.

  Hereinafter, the internal configuration of the double half bridge type unit converter 503 will be described with reference to FIG.

  The double half-bridge type unit converter 503 has a configuration in which an X-phase half bridge 601X and a Y-phase half bridge 601Y are connected in reverse series at m points. Further, a double half bridge type unit converter control means 602 for controlling the X phase half bridge 601X and the Y phase half bridge 601Y is provided.

  In the present specification, when it is not necessary to distinguish between them, the X-phase half bridge 601X and the Y-phase half bridge 601Y are collectively referred to as “half bridge 601”.

  Hereinafter, the internal configuration of the half bridge 601X will be described.

  The anti-parallel circuit of the X-phase upper switching element 201XP and the X-phase upper free-wheeling diode 202XP and the anti-parallel circuit of the X-phase lower switching element 201XN and the X-phase lower free-wheeling diode 202XN are connected in series at the point x. This is referred to as a first series circuit.

  The half bridge 601X includes two capacitors, an X-phase upper capacitor 203XP and an X-phase lower capacitor 203XN, as energy storage elements.

  The X-phase upper capacitor 203YP and the X-phase lower capacitor 203YN are connected in series at m points. This is referred to as a second series circuit.

  The half bridge 601X has a configuration in which the first and second series circuits are connected in parallel at the px point and the nx point.

  Next, the internal configuration of the half bridge 601Y will be described.

  The antiparallel circuit of the Y phase upper switching element 201YP and the Y phase upper freewheeling diode 202YP and the antiparallel circuit of the Y phase lower switching element 201YN and the Y phase lower freewheeling diode 202YN are connected in series at the point y. This is referred to as a first series circuit.

  The half bridge 601Y includes two capacitors, an Y-phase upper capacitor 203YP and a Y-phase lower capacitor 203YN, as energy storage elements.

  Y-phase upper capacitor 203YP and X-phase lower capacitor 203YN are connected in series at m points. This is referred to as a second series circuit. The m point is common with the m point of the X-phase half bridge 601.

  The half bridge 601Y has a configuration in which the first and second series circuits are connected in parallel at the py point and the ny point.

  As described above, the m points of the X-phase half bridge 601X and the Y-phase half bridge 601Y are connected.

  Hereinafter, the voltage / current in the double half bridge type unit converter 503 is defined.

  The voltage at the point x with respect to the point y is referred to as the output voltage of the double half bridge unit converter 503 and is denoted as Vjk.

  Here, j represents the arm 502 to which the double half bridge unit converter 503 belongs, and j = uv, vw, wu. K represents a number in the arm 502 of the double half bridge type unit converter 504, and k = 1, 2,. Hereinafter, in this specification, j and k added to each voltage of the unit converter have the same meaning.

  The voltage of the X-phase upper capacitor 203XP is expressed as VCXPjk, and the voltage of the X-phase lower capacitor 203XN is expressed as VCXNjk.

  Similarly, the voltage of the Y-phase upper capacitor 203YP is expressed as VCYPjk, and the voltage of the X-phase lower capacitor 203YN is expressed as VCYNjk.

  Hereinafter, the relationship between the on / off state of the switching element and the output voltage Vjk will be described. A path through which the current Ij flows will also be described.

  However, in the following description, it is assumed that the voltages of the four capacitors 203 are substantially equal, and the description will be made by approximating VCXPjk = VCXNjk = VCYPjk = VCYNjk = VCjk.

  When the X-phase upper switching element 201XP is on, the X-phase lower switching element 201XN is off, the Y-phase upper switching element 201YP is on, and the Y-phase lower switching element 201YN is off, The voltage is the difference between the voltage of the X-phase upper capacitor 203XP and the voltage of the Y-phase upper capacitor 203YP, that is, approximately Vjk = 0. In this case, the current Ij flowing through the unit converter passes through the X-phase upper capacitor 203XP and the Y-phase upper capacitor 203YP.

  When the X-phase upper switching element 201XP is on, the X-phase lower switching element 201XN is off, the Y-phase upper switching element 201YP is off, and the Y-phase lower switching element 201YN is on, The voltage is the sum of the voltage of the X-phase upper capacitor 203XP and the voltage of the Y-phase lower capacitor 203YN, that is, approximately Vjk = 2VCjk. In this case, the current Ij flowing through the unit converter passes through the X-phase upper capacitor 203XP and the Y-phase lower capacitor 203YN.

  When the X-phase upper switching element 201XP is off, the X-phase lower switching element 201XN is on, the Y-phase upper switching element 201YP is on, and the Y-phase lower switching element 201YN is off, The voltage is a voltage having a polarity opposite to the sum of the voltage of the X-phase lower capacitor 203XN and the voltage of the Y-phase upper capacitor 203YP, that is, approximately Vjk = −2VCjk. In this case, the current Ij flowing through the unit converter passes through the X-phase lower capacitor 203XN and the Y-phase upper capacitor 203YP.

  When the X-phase upper switching element 201XP is off, the X-phase lower switching element 201XN is on, the Y-phase upper switching element 201YP is off, and the Y-phase lower switching element 201YN is on, The voltage is the difference between the voltage of the X-phase lower capacitor 203XP and the voltage of the Y-phase lower capacitor 203YN, that is, approximately Vjk = 0. In this case, the current Ij flowing through the unit converter passes through the X-phase lower capacitor 203XN and the Y-phase lower capacitor 203YN.

  From the above, it can be seen that the output voltage Vjk of the double half bridge type unit converter 503 can be controlled by controlling on / off of the switching element.

  In the double-bridge unit converter 109, it can be seen that the current Ij passes through any two capacitors 203 regardless of the on / off state of the switching element.

  Due to the features of the double half bridge type unit converter 503, the current flowing through the arm 107 always passes through at least two capacitors. Thereby, according to the principle demonstrated using FIGS. 10-12 of Example 1, the effect that the excessive direct current | flow magnetism of the transformer 105 can be prevented is acquired.

  Hereinafter, another effect obtained by connecting the m points of the two half bridges 601X and Y in the double half bridge type unit converter 503 will be described with reference to FIG.

  As shown in FIG. 6, the double half bridge type unit converter 503 includes double half bridge type unit converter control means 602 for controlling two half bridges 601X and Y.

  The double half bridge type unit converter control means 602 controls the four switching elements 201XP, XN, YP, and YN.

  Here, as shown in FIG. 6, when the reference potential of the double half bridge type unit converter control means 602 and the potential at the point m are set to the equipotential Gc, the double half bridge type unit converter control means 602 and each switching The potential differences from the elements 201XP, XN, YP, and YN are approximately equal to the voltages of the capacitors 203XP, XN, YP, and YN, respectively, at maximum.

  That is, the electrical insulation between the double half bridge type unit converter control means 602 and each switching element 201 only needs to withstand the voltage of one capacitor 203, and the four control elements can be controlled by one control means. The effect of being able to control on / off is obtained.

  On the other hand, when two half-bridge unit converters 108 shown in FIG. 2 in the first embodiment are used, two switching elements are controlled by one control means, and switching elements that can be controlled per control means. The number of is small.

  Further, when two half-bridge unit converters 108 shown in FIG. 2 are connected in series and four switching elements included in the two half-bridge unit converters are to be controlled by one control means, the control is performed. The electrical insulation between the means and the four switching elements needs to withstand the sum of the voltages of the two capacitors 203.

  As described above, the double half bridge type unit converter 503 doubles the number of switching elements that can be controlled per control means as compared to using only two half bridge type unit converters 108. In addition, it is possible to obtain an effect that the dielectric strength between the control means and each switching element can be set to a voltage equivalent to one capacitor.

  In the above description, the case where the series circuit of the three arms 502 and the reactor 106 is Δ-connected (FIG. 5) has been described as an example.

  The present invention can be applied to the case where three arms are Y-connected as shown in FIG. 7, and the same effect can be obtained.

  In FIG. 7, a circuit diagram in which the arms 502u, v, and w are directly connected to the transformer 105 is illustrated. However, a reactor may be provided between the arms 502u, v, and w and the transformer 105. Similar effects can be obtained.

  A third embodiment of the present invention will be described.

  In the first embodiment, three legs composed of two series circuits of an arm and a reactor configured by connecting one or a plurality of unit converters in series are connected in parallel, and the connection points of the two series circuits are further connected. A power converter connected to an AC system via a transformer as an AC terminal of the leg, wherein at least one half-bridge unit converter is provided for each phase between the AC terminal of the leg and the transformer. Is connected.

  The power converter of the present embodiment is linked to an AC system as, for example, a direct current power transmission (HVDC) system.

  In other words, the feature of the third embodiment is that a half-bridge unit converter is connected in series between the AC output terminal of MMCC-DSCC (double-star chopper cells) described in Non-Patent Document 1 and the transformer. This is the point.

  According to the present embodiment, the simple circuit configuration as in the first embodiment can provide the effect of preventing excessive DC bias of the transformer, and also the effect of enabling AC / DC power conversion. It is done.

  Hereinafter, the overall configuration of the present embodiment will be described with reference to FIG.

  The power converter 801 includes a transformer 105, a half-bridge unit converter 108, and legs 802u, v, and w.

  The U phase will be described. A leg 802u is a series circuit of an arm 803up, two reactors 803, and an arm 803un. As shown in FIG. 8, a connection point between the two reactors 803 is referred to as a U 'point. .

  A half-bridge type unit converter 108 is connected in series between the U point of the transformer 105 and the U 'point of the leg 802u.

  Similarly, the leg 802v is a series circuit of an arm 803vp, two reactors 803, and an arm 803vn. As shown in FIG. 8, a connection point between the two reactors 803 is referred to as a V 'point.

  A half-bridge unit converter 108 is connected in series between the V point of the transformer 105 and the V ′ point of the leg 802v.

  The leg 802w is a series circuit of an arm 803wp, two reactors 803, and an arm 803wn. As shown in FIG. 8, the connection point of the two reactors 803 is referred to as a W 'point.

  A half-bridge type unit converter 108 is connected in series between the W point of the transformer 105 and the W ′ point of the leg 802w.

  Legs 802u, v, and w are connected in parallel at point P and point N as shown in FIG.

  A DC device 805 is connected between the P point and the N point. The DC device 805 is, for example, a DC load, a DC power source, another AC / DC converter, or the like. For example, if another AC / DC converter is connected via a DC power transmission line, the power converter 801 and the DC device 805 constitute an HVDC system.

  In the present specification, when there is no need to distinguish between them, the legs 802u, v, and w are collectively referred to as “legs 802”. Similarly, the arms 803up, un, vp, vn, wp, wn are collectively referred to simply as “arm 803”.

  Hereinafter, the internal configuration of the bidirectional chopper type unit converter 805 will be described with reference to FIG.

  The anti-parallel circuit of the X-phase upper switching element 201XP and the X-phase upper free-wheeling diode 202XP and the anti-parallel circuit of the X-phase lower switching element 201XN and the X-phase lower free-wheeling diode 202XN are connected in series at the point x.

  In addition, the bidirectional chopper type unit converter 805 includes a capacitor 203 as an energy storage element.

  The bidirectional chopper type unit converter 805 has a configuration in which the series circuit and the capacitor 203 are connected in parallel at the p point and the n point.

  The voltage at the point x with respect to the point n is referred to as the output voltage of the bidirectional chopper type unit converter 805 and is expressed as Vjk.

  In addition, the voltage of the capacitor 203 is expressed as VCjk.

  Hereinafter, the relationship between the on / off state of the switching element and the output voltage Vjk will be described. A path through which the current Ij flows will also be described.

  When the X-phase upper switching element 201XP is on and the X-phase lower switching element 201XN is off, the voltage at the x point with respect to the n point is substantially equal to the voltage VCjk of the capacitor 203. That is, Vjk = VCjk.

  When the X-phase upper switching element 201XP is off and the X-phase lower switching element 201XN is on, the voltage at the x point with respect to the n point is substantially zero. That is, Vjk = 0.

  From the above, it can be seen that the output voltage Vjk of the bidirectional chopper type unit converter 805 can be controlled by controlling on / off of the switching element.

  The internal configuration and operation of the half-bridge unit converter 108 are as described in the first embodiment.

  In the following description, currents flowing through the U point, V point, and W point of the transformer 105 are referred to as Iu, Iv, and Iw as shown in FIG.

  When the currents Iu, Iv, and Iw contain a direct current component, direct current magnetization is generated in the transformer 105. Moreover, if the DC component contained in Iu, Iv, and Iw can be attenuated, the magnetism of the transformer 105 can be prevented.

  Now, Iu, Iv, and Iw pass through the half-bridge type unit converter 108. That is, Iu, Iv, and Iw always pass through either the capacitor 203P or 203N inside the half-bridge unit converter 108.

  In other words, the currents Iu, Iv, Iw flowing through the transformer 105 always pass through the half-bridge unit converter 108.

  Therefore, in the first embodiment, the DC component included in Iu, Iv, and Iw can be attenuated by the same principle as that described with reference to FIGS.

  That is, by connecting the half-bridge unit converter 108 in series between the point U-U ', the point V-V', and the point W-W ', it is possible to prevent the DC bias of the transformer 105. The effect can be obtained.

  In FIG. 8, the number of U, V, and W half-bridge unit converters 108 connected in series is depicted as one, but the same effect can be obtained by connecting a plurality of U, V, and W phase converters 108 in series.

  In FIG. 8, the same effect can be obtained by using a double half bridge type unit converter (FIG. 6) instead of the half bridge type unit converter 108 of each phase of U, V, and W.

  A fourth embodiment of the present invention will be described.

  In the first embodiment, the principle that the direct current flowing through the winding of the transformer can be attenuated by the action of charging and discharging the capacitor of the half-bridge type unit converter has been described with reference to the schematic waveforms shown in FIGS.

  In addition to this, the present embodiment is characterized in that a means for measuring the voltages of the two capacitors of the half-bridge type unit converter and controlling it so as to balance it is added.

  As a result, the direct current can be positively attenuated without directly sensing the direct current component of the current flowing through the transformer winding.

  Hereinafter, the configuration of the central control unit 110 of this embodiment in which the balance control of the two capacitors 203P and 203 of the half-bridge type unit converter 108 is added to the power conversion device 104 of FIG. 1 described in the first embodiment will be described.

  Hereinafter, the internal configuration and operation of the central control means 110 in this embodiment will be described with reference to FIG.

  FIG. 13 shows an example of the internal configuration of the central control means 110 in FIG. Hereinafter, FIG. 13 will be referred to as “central control means 110a” for distinction from FIG. 14 described later.

  FIG. 13 has a function of correcting the voltage command values of the arms 107uv, vw, wu based on the voltages of the two capacitors 203P, 203 provided in the half-bridge type unit converter 108.

  The central control unit 110a includes an all-capacitor voltage control unit 1301, a power control unit 1302, a current control unit 1303, a capacitor voltage balance control unit 1304, and a gate pulse generation unit 1305.

  A feature of the present invention is that the central control means 110 a includes a capacitor voltage balance control means 1304.

  The function of each part will be described below.

  The total capacitor voltage control means 1301 generates, for example, an active power command value P * in order to make the average value or the total value VC of the capacitor voltages VCjk of the unit converters 108 and 109 coincide with the command value VC * as much as possible.

  The central control means 110a receives the reactive power command value Q * from an external control system not shown. Alternatively, the effect of this embodiment can be obtained even if Q * is generated inside the central control means 110a.

  The power control unit 1302 generates, for example, arm current command values Iuv *, Ivw *, and Iwu * in order to realize P * and Q *.

  For example, the current control means 1303 calculates the arm voltage command value from the measured values of the arm currents Iuv, Ivw, Iwu, the line voltages VRab, VRbc, VRca at the connection point, and the arm current command values Iuv *, Ivw *, Iwu * Vuv *, Vvw *, and Vwu * are generated.

  The capacitor voltage balance control means 1304, which is a feature of the present invention, will be described below. However, in the following, each arm 107 is provided with only one half-bridge type unit converter 108 and the number is 1 (that is, k = 1).

  For the half-bridge type unit converter 108 included in the arm 107uv, a subtractor 1305 obtains the difference between the voltage VCPuv1 of the upper capacitor 203P and the voltage VCNuv1 of the lower capacitor 203N.

  Similarly, with respect to the half bridge type unit converter 108 included in the arm 107vw, a subtractor 1305 obtains a difference between the voltage VCPvw1 of the upper capacitor 203P and the voltage VCNvw1 of the lower capacitor 203N.

  Further, for the half-bridge unit converter 108 included in the arm 107 wu, a difference between the voltage VCPwu1 of the upper capacitor 203P and the voltage VCNwu1 of the lower capacitor 203N is obtained by a subtractor 1305.

  The three differences obtained above, that is, the correction voltages VDCCuv, VDCCvw, and VDCCwu are each multiplied by a gain 1306, and the adder 1307 adds the result to the arm voltage command values Vuv *, Vvw *, and Vwu *, respectively, and Vuv. Calculate '*, Vvw' *, Vwu '*.

  In FIG. 13, the proportional gain KDCCb is drawn as the gain 1306. However, the gain 1306 is not limited to the proportional (P) gain, but is also proportional / integral (PI) gain, proportional / integral / derivative (PID) gain, Even in such a combination, the effects of the present invention can be obtained.

  The gate pulse generation means calculates gate pulses uvk, gvwk, and gwuk to the unit converters 108 and 109 from, for example, Vuv ′ *, Vvw ′ *, and Vwu ′ * and the voltage VCjk of each capacitor.

  The central control means 110 transmits the calculated gate pulses guvk, gvwk, gwuk to the unit converter control means 204, 301 of the unit converters 108, 109 via the transmission communication path 111 shown in FIG. .

  In this embodiment, the correction voltages VDCCuv, VDCCvw, and VDCCwu are superimposed on the arm voltage command value by the action of the capacitor voltage balance control means 1304 shown in FIG. The effective power generated by the correction voltage and the direct current component of the arm current can be controlled so that the voltage balance of the two capacitors 203P and 203 inside the half-bridge type unit converter 108 is maintained.

  On the other hand, if the voltage balance between the two capacitors 203P and N can be maintained, as a result, the DC components contained in the arm currents Iuv, Iwu, and Iwu can be made substantially zero. That is, it is possible to prevent the transformer 105 from being demagnetized.

  This is because the voltage balance between the two capacitors 203P and 203 in the half-bridge type unit converter 108 is lost when the DC component contained in Iuv, Iwu, and Iwu does not reach zero. In other words, maintaining the voltage balance of the two capacitors 203P, N and making the DC components of the arm currents Iuv, Ivw, Iwu zero are generally equivalent.

  This completes the description of the internal configuration and operation of the central control means 110a shown in FIG.

  Hereinafter, another example of the capacitor voltage balance control will be described with reference to FIG. However, only differences from FIG. 13 will be described.

  FIG. 14 has a function of correcting the current detection values of the arms 107uv, vw, and wu based on the voltages of the two capacitors 203P and N provided in the half-bridge type unit converter 108.

  In the central control means 110b of FIG. 14, the capacitor voltage balance control means 1401 calculates the corrected current detection values IDCCuv, IDCCvw, IDCCwu, unlike FIG.

  The obtained IDCCuv, IDCCvw, and IDCCwu are respectively added to the arm current detection values Iuv, Ivw, and Iwu by the adder 1307 to obtain Iuv ′, Ivw ′, and Iwu ′.

  The obtained Iuv ′, Ivw ′, and Iwu ′ are input to the current control unit 1303. Similarly to FIG. 13, the current control unit 1303 controls the corrected arm current detection values Iuv ′, Ivw ′, and Iwu ′ to match the command values Iuv *, Ivw *, and Iwu *, respectively.

  As described above, the voltage balance of the two capacitors 203P and 203 inside the half-bridge type unit converter 108 is also maintained by using the output signal of the capacitor voltage balance control means 1401 as a correction value of the arm current detection value. As a result, the direct current components contained in the arm currents Iuv, Iwu, and Iwu can be made substantially zero. That is, it is possible to prevent the transformer 105 from being demagnetized.

  Further, instead of adding the IDCCuv, IDCCvw, IDCCwu to the arm current detection values Iuv, Ivw, Iwu, respectively, as in the central control means 110c shown in FIG. The same effect can be obtained when subtracting IDCCuv, IDCCvw, and IDCCwu, respectively.

  In other words, FIG. 15 has a function of correcting the current command values of the arms 107uv, vw, wu based on the voltages of the two capacitors 203P, 203 provided in the half-bridge type unit converter 108.

  In addition, similar effects can be obtained if they are mathematically equivalent.

  13, FIG. 14, and FIG. 15 described above are the central control means 110 in FIG. 1, the central control means 402 in FIG. 4, the central control means 504 in FIG. 5, the central control means 702 in FIG. 7, and the central control means in FIG. The present invention can also be applied to the control means 807, and as described above, in any case, it is possible to prevent the transformer 105 from being demagnetized.

DESCRIPTION OF SYMBOLS 101 ... AC system 102 ... System impedance 103 ... Interconnection bus 104 ... Power converter 105 ... Transformer 106 ... Reactor 107 ... Arm 108 ... Half bridge type unit Converter 109 ... Full bridge unit converter 110 ... Central control means 111 ... Transmission communication path 112 ... Reception communication path 201 ... Switching element 202 ... Free-wheeling diode 203 ... · Capacitor 204 ··· Half-bridge unit converter control means 205 ··· Voltage detection means 301 ··· Full bridge type unit converter control means 401 ··· Power converter 402 ··· Central control means 501 ··· Power converter 502 ... Arm 503 ... Double half bridge type unit converter 504 ... Central control means 60 ... half bridge 602 ... double half bridge type unit converter control means 701 ... power converter 702 ... central control means 801 ... power converter 802 ... leg 803 ... arm 804 ... Reactor 805 ... Bidirectional chopper type unit converter 806 ... DC device 807 ... Central control means 901 ... Capacitor 902 ... Bidirectional chopper type unit converter control means 1301 ... Total capacitor voltage control means 1302 ... Power control means 1303 ... Current control means 1304 ... Capacitor voltage balance control means 1305 ... Gate pulse generation means 1306 ... Gain 1307 ... Subtractor 1308 ... .Adder 1401 .. capacitor voltage balance control means

Claims (11)

A plurality of unit converters power conversion device in which a plurality of unit converters group connected in series is connected to the transformer,
Each circuit passing through the plurality of windings of the transformer includes a first capacitor and a second capacitor connected in series with the first capacitor as the unit converter or separately from the unit converter. and the capacitor, a first switching element and the first capacitor connectable to said circuit, a second switching element and the second capacitor connectable to said circuit, a unit converter comprising Have
When the DC current flows in the circuit, the power conversion device wherein such current flows in a direction opposite to the said direct current first switching element and the second switching elements operate. The power conversion device according to claim 1 , wherein the first capacitor and the second capacitor are arranged so as to be stored at different voltages when a direct current flows through the circuit . When a direct current flows through the circuit, of the first capacitor and the second capacitor , the capacitor on the downstream side of the current has a higher voltage than the capacitor on the upstream side. The power conversion device according to claim 2, wherein the second capacitor is disposed . Wherein the first switching element and the second switching element are connected in series,
The first switching element and the second switching element, and the first capacitor and the second capacitor are connected in parallel,
The first capacitor and the connection point of said second capacitor, said connection point of the first switching element and the second switching element, but the power conversion apparatus according to claim 1 Ru Tei is configured as a terminal . The first on the basis of the capacitor and the voltage of the second capacitor, the power converter according to claim 1 for controlling the first switching element or the second switching element. The power conversion device according to claim 5, wherein the first switching element or the second switching element is controlled to control a current flowing through the circuit. The power converter according to claim 1, wherein a series circuit of the unit converter group and the reactor is Δ-connected, and a connection point of the Δ-connection is connected to the transformer . The power converter according to claim 1, wherein the unit converter group is Y-connected, and a connection point of the Y connection is connected to the transformer . The power converter according to claim 8, further comprising a reactor between the unit converter group Y-connected and the transformer. Two reactors are connected between the plurality of unit converters constituting each of the plurality of unit converter groups ,
The power converter according to claim 1, wherein a connection point between the two reactors is connected in parallel to the transformer via the unit converter . A switching element , a first capacitor, a second capacitor, a first switching element that allows the first capacitor to be connected to the circuit, and a second capacitor in a circuit that passes through the winding of the transformer In the power conversion method of the power conversion device in which the second switching element that can be connected to the circuit is arranged,
Power conversion is performed by operating the switching element,
A power conversion method of operating the first switching element and the second switching element so as to attenuate the direct current when a direct current flows in the circuit.