JP6201613B2 - INVERTER DEVICE, POWER CONDITIONER, POWER GENERATION SYSTEM, AND INVERTER DEVICE CONTROL METHOD - Google Patents

Description

  The present invention relates to an inverter device that converts a DC voltage into an AC voltage, a power conditioner incorporating the inverter device, a power generation system having the inverter device, and a control method for the inverter device.

  In recent years, photovoltaic power generation has been spreading as a countermeasure for environmental problems. Since the power generated by the solar cell is DC power, the power used at home is AC, so the DC power generated by the solar cell is boosted by a booster such as a DC-DC converter, It is converted into AC power by an inverter device included in the conditioner. Moreover, in photovoltaic power generation, improvement of conversion efficiency of an inverter device for improving power generation efficiency is an urgent issue. With regard to improving the conversion efficiency of the inverter device, a grid-connected inverter device that improves the conversion efficiency by providing a power supply line short circuit for short-circuiting the power supply line between the full-bridge inverter and the single-phase three-wire power supply system Known (for example, see Patent Document 1).

  In general, a semiconductor switching element is used in the inverter device, but the semiconductor switching element tends to have a slower falling speed from ON to OFF than a rising speed from OFF to ON. Therefore, in order to prevent a power supply short circuit, it may be necessary to provide a dead time during which all semiconductor switching elements are turned off. However, when the dead time is provided, there is a disadvantage that the output waveform of the inverter device during that time shifts from an ideal waveform. With respect to this problem, there has been a proposal for performing dead time compensation for compensating for distortion of an output waveform caused by providing a dead time (see, for example, Patent Document 2).

  In the technique described in Patent Document 1, the switching element in the power supply line short circuit is always PWM controlled. However, when PWM control is performed, the power consumed by the switching element increases and conversion efficiency decreases. Therefore, it is desirable not to perform PWM control as much as possible in order to improve the conversion efficiency. Patent Document 2 discloses dead time compensation in a full-bridge inverter as described above, but disclosure of dead time compensation when there is a switching element that does not perform PWM control in order to improve conversion efficiency. There is no.

JP 2009-89541 A Japanese Patent No. 3397138

  The present invention has been invented in view of the above-described background art, and an object thereof is to provide a technique related to an inverter device that can obtain a more ideal output waveform with higher conversion efficiency.

The present invention for solving the above-described problems has the following features. That is, it has a full-bridge inverter unit that converts DC power into AC power, and a short-circuit unit that increases the conversion efficiency by short-circuiting the output of the full-bridge inverter unit. Are controlled by a plurality of switching patterns including a switching pattern in which PWM control is performed and a switching pattern in which the short circuit portion is not PWM controlled. A dead time for preventing a power supply short circuit is provided according to the switching pattern. When this dead time is provided, the duty of the PWM control is corrected to compensate for distortion of the output waveform due to the dead time.

More specifically, a full bridge inverter unit that has a first switching element group and converts DC power to AC power;
A short-circuit unit having a second switching element group and short-circuiting the output of the full-bridge inverter unit;
A controller that performs PWM control of the full-bridge inverter unit and the short-circuit unit by switching ON / OFF of the first switching element group and the second switching element group;
In an inverter device equipped with
The control unit controls the full-bridge inverter unit and the short-circuit unit by a plurality of switching patterns including a switching pattern that PWM-controls the short-circuit unit and a switching pattern that does not PWM-control the short-circuit unit. In response, a dead time is generated between the ON period of the first switching element group and the ON period of the second switching element group,
When the dead time is provided, it further includes a dead time compensator for performing dead time compensation for correcting a duty of the PWM control and compensating for distortion of an output waveform due to the dead time.

  The present invention relates to an inverter device having a HERIC circuit having a full bridge inverter part and a short-circuit part. In the present invention, by adopting the HERIC circuit, the switching voltage of the switching element can be lowered and the current passing path at 0V output can be shortened, so that the efficiency of the inverter device can be improved. Is possible.

  Further, the present invention controls the HERIC circuit by a plurality of switching patterns including a switching pattern that PWM-controls the short-circuit portion and a switching pattern that does not PWM-control the short-circuit portion, so that the short-circuit portion is not always PWM-controlled. It is possible to improve the conversion efficiency of the inverter device.

  Furthermore, according to the present invention, while using a HERIC circuit, a dead time is generated to prevent a power supply short circuit, and when a dead time is provided, the duty of PWM control is corrected to compensate for the dead time. Since dead time compensation for compensating for distortion of the output waveform is performed, it is possible to prevent a power supply short circuit and to obtain an ideal output waveform with less distortion.

In the present invention, the controller is
When linked to the power supply system to supply power to the load, and during independent operation to supply power to the load independently of the power supply system,
The contents of the switching pattern may be changed.

Here, unlike the case of grid connection, the power factor may decrease when a load that consumes a large amount of reactive power is connected during autonomous operation. When the power factor decreases, a large current flows when 0V is output. Further, when 0V is output, the ON time of the switching elements US and WS becomes long. Therefore, when PWM control is performed on the HERIC circuit during the self-sustained operation, the time during which a large current flows through the switching element in the short circuit part becomes long, and the switching element in the short circuit part may generate heat.

  On the other hand, in this invention, it controlled by the switching pattern different from the time of grid connection at the time of independent operation, for example, decided to make ON time of the 2nd switching element group which comprises a short circuit part relatively short. According to this, even when PWM control is performed on the HERIC circuit during the self-sustained operation, it is possible to suppress the switching element forming the short-circuit portion from being heated or damaged.

  In the present invention, the dead time compensation unit may calculate the compensation amount based on at least one of the output current value and the phase of the output current when the sign of the compensation amount in the dead time compensation is reversed. You may make it change with a predetermined | prescribed inclination.

  That is, when the dead time duty compensation amount is ΔDuty, the absolute value | ΔDuty | of the dead time compensation amount may be ideally constant. However, in reality, the sign of the dead time compensation amount may be reversed from | ΔDuty | to − | ΔDuty | or − | ΔDuty | to | ΔDuty |. In such a case, the output voltage may be reduced by dead time compensation. May be distorted. On the other hand, in the present invention, the dead time compensation unit, when the sign of the compensation amount in the dead time compensation is reversed, based on at least one of the output current value and the phase of the output current, either before or after the reversal. In this case, the compensation amount is changed with time at a predetermined inclination.

  According to this, when the dead time compensation amount is switched from positive to negative and from negative to positive, the dead time compensation amount can be gradually changed, and the output voltage is distorted by the reverse of the sign of the dead time compensation amount. Can be suppressed. Here, the predetermined inclination means an inclination in a range in which a significant distortion of the output voltage does not occur due to reversal of the sign of the dead time compensation amount, and may be obtained in advance by calculation or experimentally. Further, the predetermined inclination includes not only a case of changing to a linear shape, ie, a taper shape, but also a case of changing to a curved shape. Here, the phase of the output current value and the output current may be the actual output current value and the phase of the output current, or the phase of the output current command value Iref and the output current command value Iref may be substituted. Absent.

Moreover, this invention has a 1st switching element group, the full bridge inverter part which converts direct-current power into alternating current power,
A second switching element group, and a short-circuit unit that short-circuits the output of the full-bridge inverter unit,
By switching ON / OFF of the first switching element group and the second switching element group, the full bridge inverter unit and the short circuit unit are PWM-controlled,
An inverter device control method comprising:
The full-bridge inverter unit and the short-circuit unit are controlled by a plurality of switching patterns including a switching pattern that PWM-controls the short-circuit unit and a switching pattern that does not PWM-control the short-circuit unit,
According to the switching pattern, a dead time is provided between the ON period of the first switching element group and the ON period of the second switching element group,
When the dead time is provided, the duty of the PWM control is corrected to compensate for output waveform distortion due to the dead time, and dead time compensation is performed.
It may be a control method of the inverter device.

The present invention also includes the above inverter device,
A DC-DC converter that boosts the output voltage of a distributed DC power source such as a solar cell and inputs the boosted voltage to the inverter device;
A filter for reducing noise in the output of the inverter device;
It may be a power conditioner including the power conditioner, or a power generation system including the power conditioner.

  Note that means for solving the above-described problems can be used in combination as much as possible.

  According to the present invention, the conversion efficiency of the inverter device can be improved, or a more ideal output waveform can be obtained.

It is a block diagram of the solar energy power generation system which concerns on an Example. It is a block diagram which shows the control content at the time of controlling ON / OFF of a switching element. It is a figure which shows the relationship between the current command value and voltage command value of an inverter apparatus at the time of a grid connection, switching of the switching pattern accompanying it, and a change of a state. It is a figure which shows the electric current flow of the inverter in the state 1 at the time of grid connection. It is a figure which shows the electric current flow of the inverter in the state 2 at the time of grid connection. It is a figure which shows the electric current flow of the inverter in the state 3 at the time of grid connection. It is a figure which shows the electric current flow of the inverter in the state 4 at the time of grid connection. It is a figure which shows the electric current flow of the inverter in the state 5 at the time of grid connection. It is a figure which shows the electric current flow of the inverter in the state 6 at the time of grid connection. It is a figure which shows the relationship between the current command value and voltage command value of an inverter apparatus at the time of grid connection, and the relationship of switching of a switching pattern, a state change, and dead time compensation amount. It is a figure which shows the electric current flow of an inverter when the electric current at the time of self-supporting operation is a positive direction. It is a figure which shows the electric current flow of an inverter when the electric current at the time of self-supporting operation is a negative direction. It is a figure which shows the change of the dead time compensation amount based on the command electric current value Iref.

  DETAILED DESCRIPTION Exemplary embodiments for carrying out the present invention will be described in detail below with reference to the drawings.

<Example 1>
FIG. 1 shows a solar power generation system 1 in the present embodiment. The solar power generation system 1 includes a solar battery (not shown) and a power conditioner 10 that converts a DC voltage output from the solar battery into an AC voltage and enables an interconnection operation with an electric system. The power conditioner 10 includes a DC-DC converter 11, an inverter device 13, and a filter circuit 15. In FIG. 1, a capacitor 12 is charged by a direct current output from a solar cell, and has a function of smoothing the output from the solar cell.

  As the DC-DC converter 11, for example, a chopper booster circuit is used. In this embodiment, the DC-DC converter 11 includes an inductor 11a, a switching element 11b, a backflow prevention diode 11c, and a capacitor 11d. The DC-DC converter 11 has a function of boosting the DC voltage output from the solar cell. The output voltage DDV of the DC-DC converter 11 is detected by a voltage sensor (not shown) and input to the control unit 17. The output of the DC-DC converter 11 is input to the inverter device 13.

The inverter device 13 converts the DC voltage output from the DC-DC converter 11 into an AC voltage and outputs the AC voltage to the filter circuit 15. The inverter device 13 of the present invention includes a full-bridge inverter 13a as a full-bridge inverter unit composed of switching elements UH, UL, WH and WL, and a short-circuit circuit 13b as a short-circuit unit composed of switching elements US and WS for short-circuiting the outputs thereof. Have A control method of the inverter device 13 which is a feature of the present invention will be described later. The output current IL of the inverter device 13 is detected by a current sensor (not shown) and input to the control unit 17.

  The filter circuit 15 includes inductors 15a and 15b and a capacitor 15c. The filter circuit 15 has a function of suppressing the noise of the output current output from the inverter device 13 and flowing backward to an electric system (not shown). The system voltage Vs is detected by a voltage sensor (not shown) and input to the control unit 17.

<Explanation of block diagram>
FIG. 2 is a block diagram showing the control contents when the control unit 17 controls ON / OFF of the switching element. The control unit 17 obtains a deviation ΔI between the current command value Iref and the actual current output value IL of the inverter device 13. The output current control unit 17b in the control unit 17 calculates a voltage command value Vref that is a voltage value to be output by the inverter device 11 from the deviation ΔI. The controller 17 calculates Duty by dividing the voltage command value Vref by DDV. In addition, the control unit 17 includes a pattern generation unit 17c. The pattern generation unit 17c generates the current switching pattern from the current command value Iref, the voltage command value Vref, and the past switching pattern output from the pattern storage unit 17d. A method for generating this switching pattern will be described later. Then, the pattern generation unit 17c outputs the generated switching pattern. The pattern storage unit 17d stores the latest output from the pattern generation unit 17c.

  The control unit 17 of the present embodiment is provided with a dead time compensation unit 17e. The dead time compensation unit 17e outputs a duty compensation amount ΔDuty to be corrected from the current command value Iref output from the DDV control unit 17a and the switching pattern output from the pattern generation unit 17c. The PWM signal generation unit 17f generates a PWM signal from the calculated duty and the sum of the duty compensation amount ΔDuty and outputs the PWM signal to the logic circuit 17g. Based on the PWM signal output from the PWM signal generation unit 17f and the switching pattern output from the pattern generation unit 17c, the logic circuit 17g turns on / off the switching element or performs PWM control.

<Switching pattern during grid connection>
FIG. 3 is a diagram showing the relationship between the voltage command value Vref and the current command value Iref of the inverter device 13 of the present embodiment at the time of grid connection. The solid line in the figure indicates the current command value Iref, and the broken line indicates the voltage command value Vref. Further, the upper alphabet in FIG. 3 represents a switching pattern. Numbers arranged below the alphabet represent “states” to be described later. As shown in the figure, the inverter 13 switches the switching pattern in one cycle. Further, the state is classified into six states according to the switching pattern and the current command value Iref.

  Here, switching of the switching pattern will be described first. As shown in Table 1, the switching pattern is determined by the relationship between the current command value Iref and the voltage command value Vref. However, in the part with “hysteresis part” in the table, the switching pattern immediately before the condition of the hysteresis part is maintained. "-" In the table is a condition that does not exist due to the sign determination of the voltage command value and the current command value.

In the switching pattern A, the two sub patterns Aa and Ab are alternately switched by PWM control. As shown in Table 2, in the sub-pattern Aa, the switching elements UH, WL, WS are turned on and the switching elements UL, WH, US are turned off. In the sub-pattern Ab, only the switching element WS is turned on, and the switching elements UH, UL, WH, WL, and US are turned off. In the switching pattern A, the switching elements US and WS are not PWM driven, so that the conversion efficiency is high. However, the voltage cannot be controlled while the current flows in the negative direction.

In the switching pattern B, as shown in Table 3, the three sub patterns Ba, Bb, and Bc are switched by PWM control. In the sub-pattern Ba, the switching elements UH and WL are turned on, and the switching elements UL, WH, US and WS are turned off. In the sub-pattern B-b, the switching elements UH, UL, WH, WL, US, WS are turned off. In the sub-pattern Bc, the switching elements US and WS are turned on, and the switching elements UH, UL, WH, and WL are turned off. In the switching pattern B, a cycle of sub pattern Ba → sub pattern B−b → sub pattern B−c → sub pattern B−b is repeated. In the switching pattern B, since the switching elements US and WS are PWM driven, the conversion efficiency is lowered. However, voltage control can be performed both when the current flows in the positive direction and when the current flows in the negative direction.

In the switching pattern C, as shown in Table 4, the three sub patterns Ca, Cb, and Cc are switched by PWM control. In the sub-pattern Ca, the switching elements UL and WH are turned on, and the switching elements UH, WL, US, and WS are turned off. In the sub pattern Cb, the switching elements UH, UL, WH, WL, US, WS are turned off. In the sub-pattern Cc, the switching elements US and WS are turned on, and the switching elements UH, UL, WH, and WL are turned off. In the switching pattern C, a cycle of sub-pattern C-> sub-pattern C-b-> sub-pattern C-> sub-pattern C-b is repeated. In the switching pattern C, since the switching elements US and WS are PWM driven, the conversion efficiency is lowered. However, voltage control can be performed both when the current flows in the positive direction and when the current flows in the negative direction.

In the switching pattern D, as shown in Table 5, two sub-patterns Da and Db are alternately switched by PWM control. In the sub pattern Da, the switching elements UL, WH, and US are turned on, and the switching elements UH, WL, and WS are turned off. In the sub-pattern Db, only the switching element US is turned on, and the switching elements UH, UL, WH, WL, WS are each turned off. In the switching pattern D, since the switching elements of the switching elements US and WS are not PWM driven, the conversion efficiency is high. However, the voltage cannot be controlled while the current is flowing in the positive direction.

  Next, each state 1-6 is demonstrated using FIG. In state 1, the switching pattern is C, and the current command value Iref is positive. In state 2, the switching pattern is A and the current command value Iref is positive. In state 3, the switching pattern is B and the current command value Iref is positive. In state 4, the switching pattern is B and the current command value Iref is negative. In state 5, the switching pattern is D, and the current command value Iref is negative. In state 6, the switching pattern is C and the current command value Iref is negative.

  As described later, a dead time occurs in the switching patterns B and C. Therefore, the dead time compensation unit estimates states 1 to 6 from the current command value Iref and the switching pattern, and calculates a dead time compensation amount corresponding to each state. As described later, the dead time compensation amount is positive in states 1 and 3, the dead time compensation amount is 0 in states 2 and 5, and the dead time compensation amount is negative in states 4 and 6. Next, the reason why the dead time compensation amount becomes positive in states 1 and 3 and becomes negative in states 4 and 6 will be described. The reason why the dead time compensation amount becomes 0 in states 2 and 5 is that no dead time occurs in switching patterns A and D.

<State 1>
First, state 1 will be described with reference to FIGS. FIG. 4A shows the ON / OFF state of each switching element and the current flow in the sub-pattern Ca. Similarly, FIG. 4B shows the sub-pattern Cb, and FIG. 4C shows the sub-pattern C-c. Switching elements that are turned on are indicated by solid lines, and switching elements that are turned off are indicated by broken lines.

  In the state 1, the switching pattern is the switching pattern C, and the cycle of the above-described sub-patterns Ca → Cb → Cc → Cb is repeated by PWM control. The current command value Iref is positive. In the sub-pattern Ca, the switching elements UL and WH are turned on, and the switching elements UH, WL, US, and WS are turned off. The current flow at this time is: inductor 15b → reflux diode of switching element WH → capacitor 11d → reflux diode of switching element UL → inductor 15a. The output voltage at this time is -DDV having the opposite sign to the output voltage DDV of the DC-DC converter 11.

  In the sub-pattern Cb, the switching elements UH, UL, WH, WL, US, and WS are all turned off. The current flow at this time is: inductor 15b → reflux diode of switching element WH → capacitor 11d → reflux diode of switching element UL → inductor 15a. The output voltage at this time is -DDV having the opposite sign to the output voltage DDV of the DC-DC converter 11.

In the sub-pattern Cc, the switching elements US and WS are turned on, and the switching elements UH, UL, WH, and WL are turned off. The flow of current at this time is: inductor 15b → switching element WS → return diode of switching element US → inductor 15a. The output voltage at this time is zero. Here, the sub-pattern Cb corresponds to dead time. In the state 1, in order to provide a dead time, the duty that becomes the sub-pattern Cc is reduced. That is, in the state 1, a part of the period that should ideally be the sub pattern Cc is actually the sub pattern Cb. As a result, the output voltage is actually −DDV in a part of the period in which the output voltage should ideally be 0, and the output voltage of the inverter device 13 is distorted from the sine wave. Therefore, in the switching pattern C, distortion of the output voltage due to dead time must be taken into consideration. Here, in order to cancel the difference -DDV, it is necessary to add a positive dead time compensation amount ΔDuty to the original duty.

<State 2>
Next, state 2 will be described with reference to FIGS. In state 2, the switching pattern is switching pattern A, and the above-described sub-patterns Aa and Ab are alternately switched by PWM control. In the sub-pattern A-a, the switching elements UH, WL, WS are turned on, and the switching elements UL, WH, US are turned off. The flow of current at this time is inductor 15b → switching element WL → capacitor 11d → switching element UH → inductor 15a. The output voltage at this time is the same as the output voltage DDV of the DC-DC converter 11.

  In the sub-pattern Ab, only the switching element WS is turned on, and the switching elements UH, UL, WH, WS, and US are turned off. The flow of current at this time is: inductor 15b → switching element WS → return diode of switching element US → inductor 15a. The output voltage at this time is the same as zero. In this switching pattern A, there is no possibility of a power supply short circuit, so there is no need to provide a dead time.

<State 3>
Next, the state 3 will be described with reference to FIGS. In the state 3, the switching pattern is the switching pattern B, and the cycle of the sub-pattern Ba → BB → BC → BB is repeated by the PWM control. The current command value Iref is positive. In the sub-pattern Ba, the switching elements UH and WL are turned on, and the switching elements UL, WH, US and WS are turned off. The current flow at this time is: inductance 15b → switching element WL → capacitor 11d → switching element UH → inductor 15a. The output voltage at this time is the same as the output voltage DDV of the DC-DC converter 11. In the sub-pattern B-b, the switching elements UH, UL, WH, WL, US, WS are turned off.

  The flow of current at this time is: inductance 15b → reflux diode of switching element WH → capacitor 11d → reflux diode of switching element UL → inductor 15a. The output voltage at this time is -DDV having the opposite sign to the output voltage DDV of the DC-DC converter 11. In the sub-pattern Bc, the switching elements US and WS are turned on, and the switching elements UH, UL, WH, and WL are turned off. The flow of current at this time is inductance 15b → switching element WS → return diode of switching element US → inductance 15a. The output voltage at this time is zero. Here, the sub-pattern B-b corresponds to a dead time.

In the state 3, in order to provide a dead time, the duty that becomes the sub-pattern Bc is reduced. That is, in the state 3, a part of the period that should ideally be the sub-pattern Bc is actually the sub-pattern B-b. As a result, the output voltage is actually -DDV in part of the period in which the output voltage should ideally be 0,
The output voltage of the inverter device 13 is distorted from a sine wave. Therefore, in the switching pattern B, distortion of the output voltage due to dead time must be taken into consideration. Here, in order to cancel the difference -DDV, it is necessary to add a positive dead time compensation amount ΔDuty to the original duty.

<State 4>
Next, the state 4 will be described with reference to FIGS. Even in the state 4, the switching pattern is the switching pattern B, and the cycle of the sub-pattern Ba → B−b → B−c → B−b is repeated by the PWM control. The current command value Iref is negative. In the sub-pattern Ba, the switching elements UH and WL are turned on, and the switching elements UL, WH, US and WS are turned off. The current flow at this time is: inductor 15a → reflux diode of switching element UH → capacitor 11d → reflux diode of switching element WL → inductor 15b. The output voltage at this time is the same as the output voltage DDV of the DC-DC converter 11.

  In the sub-pattern B-b, the switching elements UH, UL, WH, WL, US, WS are turned off. The flow of current at this time is: inductance 15a → reflux diode of switching element UH → capacitor 11d → reflux diode of switching element WL → inductor 15b. The output voltage at this time is the same as the output voltage DDV of the DC-DC converter 11. In the sub-pattern Bc, the switching elements US and WS are turned on, and the switching elements UH, UL, WH, and WL are turned off. The flow of current at this time is: inductance 15a → switching element US → return diode of switching element WS → inductance 15b. The output voltage at this time is zero. Here, the sub-pattern Bb is a dead time.

  In the state 4, in order to provide a dead time, the duty that becomes the sub-pattern B-c is decreased. That is, in the state 4, a part of the period that should ideally be the sub-pattern Bc is actually the sub-pattern B-b. As a result, ideally, the output voltage becomes DDV in a part of the period in which the output voltage should be 0, and the output voltage of the inverter device 13 is distorted from the sine wave. Therefore, in the switching pattern B, distortion of the output voltage due to dead time must be taken into consideration. Here, in order to cancel out the difference DDV, it is necessary to add a negative dead time compensation amount ΔDuty to the original duty.

<State 5>
Next, the state 5 will be described with reference to FIGS. In the state 5, the switching pattern is the switching pattern D, and the above-described sub patterns Da and Db are alternately switched by PWM control. In the sub pattern Da, the switching elements UL, WH, and US are turned on, and the switching elements UH, WL, and WS are turned off. The flow of current at this time is inductor 15a → switching element UL → capacitor 11d → switching element WH → inductor 15b.

  The output voltage at this time is -DDV having the opposite sign to the output voltage DDV of the DC-DC converter 11. In the sub-pattern Db, only the switching element US is turned on, and the switching elements UH, UL, WH, WL, WS are each turned off. The current flow at this time is: inductor 15a → switching element US → return diode of switching element WS → inductor 15b. The output voltage at this time is zero. In this switching pattern D, there is no possibility of a power supply short circuit, so there is no need to provide a dead time.

<State 6>
Next, the state 6 will be described with reference to FIGS. In the state 6, the switching pattern is the switching pattern C, and the cycle of the above-described sub-patterns Ca → Cb → Cc → Cb is repeated by PWM control. The current command value Iref is negative. In the sub-pattern Ca, the switching elements UL and WH are turned on, and the switching elements UH, WL, US, and WS are turned off. The flow of current at this time is inductor 15a → switching element UL → capacitor 11d → switching element WH → inductor 15b. The output voltage at this time is -DDV having the opposite sign to the output voltage DDV of the DC-DC converter 11.

  In the sub pattern Cb, the switching elements UH, UL, WH, WL, US, WS are turned off. The current flow at this time is: inductor 15a → reflux diode of switching element UH → capacitor 11d → reflux diode of switching element WL → inductor 15b. The output voltage at this time is the same as the output voltage DDV of the DC-DC converter 11. In the sub-pattern Cc, the switching elements US and WS are turned on, and the switching elements UH, UL, WH, and WL are turned off. The current flow at this time is: inductor 15a → switching element US → return diode of switching element WS → inductor 15b. The output voltage at this time is zero. Here, the sub-pattern Cb corresponds to dead time.

  In state 6, in order to provide a dead time, the duty that becomes the sub-pattern Cc is reduced. That is, in the state 6, a part of the period that should ideally be the sub pattern Cc is actually the sub pattern Cb. As a result, ideally, the output voltage becomes DDV in a part of the period in which the output voltage should be 0, and the output voltage of the inverter device 13 is distorted from the sine wave. Therefore, in the switching pattern C, distortion of the output voltage due to dead time must be taken into consideration. Here, in order to cancel out the difference DDV, it is necessary to add a negative dead time compensation amount ΔDuty to the original duty.

As described above, it has been described that the output voltage is distorted due to the dead time in the states 1 to 6. The results are summarized in the table.

  FIG. 10 shows the relationship between the voltage command value Vref and the current command value Iref of the inverter device 13 of this embodiment, the switching pattern, the state, and the dead time compensation during grid connection. A curve indicated by a solid line in FIG. 10 is a current command value Iref of the inverter device 11. Also, the alphabet arranged at the top of FIG. 10 is a switching pattern, and the numbers arranged below the alphabet represent “state”. In the drawing, the dead time compensation amount ΔDuty is represented by a thick solid line. It can be seen that in states 1 and 3, the duty is compensated to the plus side, and in states 4 and 6, it is compensated to the minus side. The duty compensation amount ΔDuty may be, for example, about DDV 2 μs (dead time) in the plus side, and may be, for example, about −DDV 2 μs (dead time) in the minus side.

<Switching pattern during autonomous operation>
Next, a switching pattern at the time of a self-sustained operation, and dead time and dead time compensation at that time will be described.

  During autonomous operation, the power factor may decrease when a load that consumes a large amount of reactive power is connected. When the power factor decreases, a large current flows when 0V is output. Further, when 0V is output, the ON time of the switching elements US and WS becomes long. As a result, the time during which a large current flows through the switching elements US and WS becomes long, and the switching elements US and WS may generate heat and be damaged. Therefore, the inverter device should be controlled in a switching pattern that does not increase the ON time of the switching elements US and WS, which is different from that in the grid connection during the independent operation.

In this embodiment, the switching element is controlled by one switching pattern consisting of four sub-patterns during the self-sustaining operation. Hereinafter, the switching pattern during the self-sustaining operation is referred to as a switching pattern E. In the sub-pattern Ea, the switching elements UH and WL are turned on, and the switching elements UL, WH, US and WS are turned off. In the sub-pattern Eb, the switching elements UL and WH are turned on, and the switching elements UH, WL, US, and WS are turned off. In the sub-pattern Ec, the switching elements US and WS are turned on, and the switching elements UH, UL, WH, and WL are turned off. In the sub pattern Ed, the switching elements UH, UL, WH, WL, US, WS are turned off. In the switching pattern E, the sub pattern Ea → the sub pattern Ed → the sub pattern Ec → the sub pattern Ed → the sub pattern Eb → the sub pattern Ed → the sub pattern Ec → the sub pattern E− The cycle d is repeated within one carrier.

<Current in the positive direction>
11A to 11D, how the output voltage of the switching pattern E changes in a state where current flows in the positive direction will be described. As shown in FIG. 11A, the current flow in the case of the sub-pattern Ea is as follows: inductor 15b → switching element WL → capacitor 11d → switching element UH → inductor 15a. The output voltage at this time is the same as the output voltage DDV of the DC-DC converter 11. As shown in FIG. 11B, the current flow in the case of the sub-pattern Eb changes from the inductor 15b → the free wheel diode of the switching element WH → the capacitor 11d → the free wheel diode of the switching element UL → the inductor 15a. The output voltage at this time is -DDV having the opposite sign of the output voltage DDV of the DC-DC converter 11.

As shown in FIG. 11C, the current flow in the case of the sub-pattern Ec changes from the inductor 15b → the switching element WS → the freewheeling diode of the switching element US → the inductor 15a. The output voltage at this time is zero. As shown in FIG. 11 (d), the current flow in the case of the sub-pattern Ed is as follows: inductor 15b → freewheeling diode of switching element WH → capacitor 11d → freewheeling diode of switching element UL → inductor 15a. The output voltage at this time is -DDV having the opposite sign of the output voltage DDV of the DC-DC converter 11.

<Dead time compensation>
Here, the sub-pattern Ed corresponds to the dead time. In this state, in order to provide a dead time, the times of the sub-patterns Ea, Eb, and Ec are shortened. That is, a part of the period that should originally be the sub-patterns Ea, E-b, and E-c becomes the sub-pattern Ed due to the dead time, so that the output voltage is shifted. Therefore, by adding the dead time compensation amount ΔDuty to the duty by the amount of deviation of the output voltage, the output voltage can be brought close to a sine wave with less noise.

<Current is in the negative direction>
With reference to FIGS. 12A to 12D, how the output voltage of the switching pattern E changes in a state where the current flows in the negative direction will be described. As shown in FIG. 12A, the current flow in the case of the sub-pattern Ea changes from the inductor 15a → the free wheel diode of the switching element UH → the capacitor 11d → the free wheel diode of the switching element WL → the inductor 15b. The output voltage at this time is the same as the output voltage DDV of the DC-DC converter 11. As shown in FIG. 12 (b), the current flow in the case of the sub-pattern Eb is as follows: inductor 15a → switching element UL → capacitor 11b → switching element WH → inductor 15b. The output voltage at this time is -DDV having the opposite sign of the output voltage DDV of the DC-DC converter 11.

  As shown in FIG. 12C, the current flow in the case of the sub-pattern Ec is as follows: inductor 15a → switching element US → return diode of switching element WS → inductor 15b. The output voltage at this time is zero. As shown in FIG. 12 (d), the current flow in the case of the sub-pattern Ed is as follows: inductor 15a → freewheeling diode of switching element UH → capacitor 11d → freewheeling diode of switching element WL → inductor 15b. The output voltage at this time is the same as the output voltage DDV of the DC-DC converter 11.

<Dead time compensation>
Here, the sub-pattern Ed corresponds to the dead time. In this state, in order to provide a dead time, the times of the sub-patterns Ea, Eb, and Ec are shortened. That is, a part of the period that should originally be the sub patterns Eb, Eb, and Ec becomes the sub pattern Ed due to the dead time, so that the output voltage is shifted. Accordingly, by subtracting the dead time compensation amount ΔDuty from the Duty by the total amount of deviation of the output voltage within one carrier, the output voltage can be brought close to a sine wave with less noise. The duty compensation amount ΔDuty may be about 4 μs when the current is positive, for example, if the dead time is 2 μs, and may be about 4 μs, for example, when the dead time is 2 μs.

  As described above, in this embodiment, in the inverter device having the HERIC circuit having the full bridge inverter unit and the short circuit unit, the switching patterns B and C which are switching patterns for PWM control of the short circuit unit, and the short circuit unit Is controlled by switching patterns A and D which are switching patterns not subjected to PWM control. Therefore, it has become possible to further improve the conversion efficiency of the inverter device by using the switching patterns A and D, which are switching patterns in which the short circuit portion is not subjected to PWM control.

In addition, when there is a high possibility that the direction of the output current will change, switching patterns B and C capable of voltage control should be used even if the polarity of the current direction changes. In such a case, In contrast to the inconvenience that the waveform may be distorted by setting the dead time, in this embodiment, the dead time is compensated by correcting the duty. As a result, waveform distortion can be suppressed, and an output waveform closer to the ideal form can be obtained.

<Example 2>
Next, a second embodiment of the present invention will be described. In the present embodiment, when the sign of the compensation amount of the dead time compensation is reversed, an example will be described in which the dead time compensation amount is not changed to a rectangular shape but gradually changed with an inclination.

  A change in the magnitude of the dead time compensation amount ΔDuty during grid connection will be described with reference to FIG. When the dead time compensation amount is ΔDuty, the absolute value | ΔDuty | of the dead times compensation amount in the states 1, 3, 4 and 6 described in the first embodiment may ideally be a constant value. However, in reality, when the state changes from state 3 to 4 or from state 6 to 1, the dead time compensation amount changes in a step form from | ΔDuty | to − | ΔDuty | or − | ΔDuty | to | ΔDuty |. Since the sign is reversed, the output voltage may be distorted by dead time compensation. On the other hand, in this embodiment, when the dead time compensation amount is switched from positive to negative and from negative to positive with the sign reversed, the dead time compensation amount is changed at a predetermined rate of change.

  Here, the curve by the solid line in FIG. 13 represents the current command value Iref of the inverter device 11. Moreover, the alphabet arrange | positioned above FIG. 13 represents a switching pattern. The numbers placed below the alphabet represent the state. In the drawing, the dead time compensation amount ΔDuty is represented by a thick solid line. The dead time compensation amount ΔDuty is switched from positive to negative or from negative to positive at the same time as the current command value Iref is switched from positive to negative and from negative to positive. In the present embodiment, when the value of the current command value Iref approaches 0, the absolute value of the dead time compensation amount is gradually decreased from a constant value. The criterion for gradually reducing the absolute value of the dead time compensation amount from a fixed value may be the phase of the current command value Iref, not the value of the current command value Iref itself. Or it is good also as both of the phase of electric current command value Iref and electric current command value Iref.

  More specifically, the dead time compensation amount ΔDuty is switched from positive to negative in a state where the phase in the curve of the current command value Iref is within a predetermined range, for example, a range of ± several tens of degrees around 180 °. Alternatively, it may be changed with a taper inclination. Further, when the dead time compensation amount ΔDuty is switched from negative to positive in a state where the phase in the curve of the current command value Iref is in another predetermined range, for example, a range of ± several tens of degrees around 360 °, It may be changed with a taper inclination.

  When the current command value Iref is a predetermined value on the plus side, for example, several amperes or less, and the dead time compensation amount ΔDuty is switched from positive to negative, change with a taper-like slope. It may be. Further, when the dead time compensation amount ΔDuty is switched from positive to negative when the current command value Iref is a predetermined value on the negative side, for example, minus several amperes or more, it is changed with a taper-like inclination. You may decide.

Further, when the dead time compensation amount ΔDuty is switched from positive to negative in a state where the phase in the curve of the current command value Iref is within the predetermined range and the value of the current command value Iref is not more than the predetermined value on the plus side. May be changed with a taper-like inclination. Further, the dead time compensation amount ΔDuty is switched from negative to positive when the phase in the curve of the current command value Iref is within the other predetermined range and the value of the current command value Iref is equal to or greater than the predetermined value on the minus side. In this case, the change may be made with a taper-like inclination. Further, the inclination of the taper-shaped portion may be an inclination that switches within a phase range of several tens of degrees, for example, when the dead time compensation amount ΔDuty is switched from negative to positive. Further, the inclination is not necessarily constant, that is, not a linear taper, and may be changed to a curved line by changing the inclination.

  Thus, by changing the dead time compensation amount ΔDuty even in the same state, it is possible to more reliably suppress the output voltage from being distorted when the sign of the dead time compensation amount is switched.

  In addition, this invention is not limited to the structure of said Example, According to the intended purpose, various deformation | transformation are possible. For example, when the current command value Iref and the voltage command value Vref are used as a reference for determining the switching pattern and state of the inverter device 13 and a reference for switching the dead time compensation amount ΔDuty in the above embodiment, this reference is used. Substituting the actual output current IL and the actual output voltage Vinv is not excluded.

DESCRIPTION OF SYMBOLS 1 ... Photovoltaic power generation system 10 ... Power conditioner for photovoltaic power generation 11 ... DC-DC converter 11d ... Capacitor 13 ... Inverter device 15 ... Filter circuit 15a, 15b ... Inductor 17 ... Control unit 17a ... DDV control unit 17b ... Output current control unit 17c ... Pattern generation unit 17d ... Pattern storage unit 17e ... Dead time compensation unit 17f ... PWM signal Generation unit 17g: logic circuit UH, UL, WH, WL, US, WS: switching element

Claims (6)

A full bridge inverter unit having a first switching element group for converting DC power to AC power;
A short-circuit unit having a second switching element group and short-circuiting the output of the full-bridge inverter unit;
A controller that performs PWM control of the full-bridge inverter unit and the short-circuit unit by switching ON / OFF of the first switching element group and the second switching element group;
In an inverter device equipped with
The control unit controls the full-bridge inverter unit and the short-circuit unit by a plurality of switching patterns including a switching pattern that PWM-controls the short-circuit unit and a switching pattern that does not PWM-control the short-circuit unit. In response, a dead time is generated between the ON period of the first switching element group and the ON period of the second switching element group,
When the dead time is provided, a dead time compensator is further provided that performs dead time compensation that corrects the duty of the PWM control by an amount corresponding to the switching pattern and compensates for distortion of the output waveform due to the dead time. An inverter device characterized by that. The controller is
At the time of grid connection that supplies power to the load in conjunction with the power supply system, and at the time of independent operation that supplies power to the load independently of the power supply system,
The inverter device according to claim 1, wherein contents of the switching pattern are changed.   When the sign of the compensation amount in the dead time compensation is reversed, the dead time compensation unit changes the compensation amount with a predetermined gradient based on at least one of an output current value and an output current phase. The inverter device according to claim 1, wherein: A full bridge inverter unit having a first switching element group for converting DC power to AC power;
A second switching element group, and a short-circuit unit that short-circuits the output of the full-bridge inverter unit,
By switching ON / OFF of the first switching element group and the second switching element group, the full bridge inverter unit and the short circuit unit are PWM-controlled,
An inverter device control method comprising:
The full-bridge inverter unit and the short-circuit unit are controlled by a plurality of switching patterns including a switching pattern that PWM-controls the short-circuit unit and a switching pattern that does not PWM-control the short-circuit unit,
According to the switching pattern, a dead time is provided between the ON period of the first switching element group and the ON period of the second switching element group,
When the dead time is provided, the dead time compensation for correcting the output waveform distortion due to the dead time by correcting the duty of the PWM control by an amount corresponding to the switching pattern ,
Inverter device control method. The inverter device according to any one of claims 1 to 3,
A DC-DC converter that boosts the output voltage of a distributed DC power source such as a solar cell and inputs the boosted voltage to the inverter device;
A filter for reducing noise in the output of the inverter device;
A power conditioner characterized by comprising   A power generation system comprising the power conditioner according to claim 5.

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